PI6LC48P0401LEX

PI6LC48P0401 4-Output LVPECL Networking Clock Generator Features Description ÎÎFour differential LVPECL output pairs The PI6LC48P0401 is a 4-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions. Using a 25MHz crystal, the following frequencies can be generated based on the settings of 2 frequency select pins (N_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal The PI6LC48P0401 uses Pericom’s proprietary low phase noise VCO technology and can achieve less than 1ps typical rms phase jitter, so it is ideal for Ethernet interface in all kind of systems. (1.875MHz – 20MHz): 0.23ps (typical) ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.28ps (typical) ÎÎFull 3.3V or 2.5V supply modes ÎÎ-40°C to 85°C ambient operating temperature ÎÎAvailable in lead-free packages Applications ÎÎNetworking systems Block Diagram 2 N_SEL[1:0] PLL_Bypass XTAL_IN CLK0 CLK0# OSC XTAL_OUT Ref_IN Phase Detector VCO N_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used CLK1 CLK1# CLK2 CLK2# IN_SEL M = 25 (fixed) CLK3 CLK3# M_reset 14-0203 1 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator Pin Configuration CLK1# 1 24 CLK2# CLK1 2 23 CLK2 VDDO 3 22 VDDO CLK3 CLK0 4 21 CLK0# 5 20 CLK3# M_reset 6 19 GND PLL_Bypass 7 18 VDD NC 8 17 IN_SEL VDDA 9 16 Ref_IN N_SEL0 10 15 GND VDD 11 14 XTAL_IN N_SEL1 12 13 XTAL_OUT Pinout Table Pin No. Pin Name I/O Type Description 1, 2 CLK1#, CLK1 Output LVPECL Output Clock 1 3, 22 VDDO Power Output supply pins 4, 5 CLK0, CLK0# Output LVPECL Output Clock 0 6 M_reset Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and outputs are enabled. 7 PLL_Bypass Input Pulldown Selects either the PLL or the active input reference to be routed to the output dividers. When LOW, selects PLL (PLL enable). When HIGH, selects the reference clock (PLL bypass). 8 NC 9 VDDA Power 10, 12 N_SEL0, N_SEL1 Input 11, 18 VDD Power Core power supply 13, 14 XTAL_OUT, XTAL_IN Output / Input Parallel resonant crystal interface. XTAL_OUT is the output, and XTAL_IN is the input. 15, 19 GND Power Ground 16 Ref_IN Input Pulldown CMOS reference clock input 17 IN_SEL Input Pulldown Selects between the single-ended Ref_IN or crystal interface as the PLL reference source. When HIGH, selects Ref_IN. When LOW selects XTAL inputs. 20, 21 CLK3#, CLK3 Output LVPECL Output Clock 3 23, 24 CLK2, CLK2# Output LVPECL Output Clock 2 14-0203 Not connected Analog power supply Pulldown Frequency select pins 2 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator Frequency Select Function Table Inputs N_SEL1 N_SEL0 M Div. Value N Div. Value M/N Div. Value Output Frequency (MHz) (25MHz Reference) 0 0 25 4 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 Not Used Not Used Typical Crystal Requirement Parameter Test Conditions Minimum Typical Mode of Oscillation Fundamental Frequency 25 Maximum Units MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Recommended Crystal Specification Pericom recommends: a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf 14-0203 3 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator Maximum Ratings (Over operating free-air temperature range) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature............................................... -65ºC to+155ºC Ambient Temperature with Power Applied..........-40ºC to+85ºC 3.3V Analog Supply Voltage.......................................-0.5 to +3.6V ESD Protection (HBM).......................................................... 2000V DC Specifications Power Supply DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter VDD Condition Min Typ Max Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IGND Power Supply Current 130 mA IDDA Analog Supply Current 30 mA Included in IGND Power Supply DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter VDD Condition Min Typ Max Units Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IGND Power Supply Current 125 mA IDDA Analog Supply Current 30 mA Max Units Included in IGND LVCMOS/LVTTL DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Ref_IN, M_reset, N_SEL[0:1], PLL_Bypass, IN_SEL, VDD = VIN = 3.465V IIL Input Low Current Ref_IN, M_reset, N_SEL[0:1], PLL_Bypass, IN_SEL, VDD = VIN = 0V CIN Input Capacitance 4 pF Input Pulldown Resistor 51 kΩ R PULLDOWN 14-0203 Condition Min VDD = 3.3V ± 5% 2 VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 3.3V ± 5% -0.3 0.8 V VDD = 2.5V ± 5% -0.3 0.7 V 150 µA 4 Typ -5 µA www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator LVPECL DC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, TA = -40 to 85ºC) Symbol Parameter VOH Output High Voltage(1) VOL Output Low Voltage(1) Condition Min Typ Max VDD = 3.3V 1.9 2.4 VDD = 2.5V 1.1 1.6 VDD = 3.3V 1.2 1.6 VDD = 2.5V 0.4 0.8 Units V V Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#. AC Electrical Characteristics LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND AC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, TA = -40 to 85ºC) Symbol Parameter fOUT Output Frequency Range tsk(o) Output Skew t jit(Ø) Condition Min. N_SEL[1:0] = 00 Typ. Max Units 140 170 MHz N_SEL[1:0] = 01 112 136 MHz N_SEL[1:0] = 10 56 68 MHz 120 ps (1, 2) RMS Phase Jitter, (Random)(3) tR / tF Output Rise/Fall Time odc Output Duty Cycle 156.25MHz, (1.875MHz - 20MHz) 0.23 ps 156.25MHz, (12kHz - 20MHz) 0.28 ps 125MHz, (1.875MHz - 20MHz) 0.14 ps 125MHz, (12kMHz - 20MHz) 0.32 ps 62.5MHz, (637kHz - 10MHz) 0.29 ps 62.5MHz, (12kHz - 10MHz) 0.47 ps 20% to 80% 48 400 ps 52 % Note: Electrical parameters are quaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Note1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. Note2: This parameter is defined in accordance with JEDEC Standard 65. Note3: Please refer to the Phase Noise Plots. 14-0203 5 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator AC Characterisitcs, (VDD = VDDO = 2.5V ± 5%, TA = -40 to 85ºC) Symbol Parameter Output Frequency Range fOUT Condition Min. N_SEL[1:0] = 00 Typ. Max Units 140 170 MHz N_SEL[1:0] = 01 112 136 MHz N_SEL[1:0] = 10 56 68 MHz 120 ps Output Skew(1, 2) tsk(o) RMS Phase Jitter, (Random)(3) t jit(Ø) tR / tF Output Rise/Fall Time odc Output Duty Cycle 156.25MHz, (1.875MHz - 20MHz) 0.21 ps 156.25MHz, (12kHz - 20MHz) 0.28 ps 125MHz, (1.875MHz - 20MHz) 0.14 ps 125MHz, (12kMHz - 20MHz) 0.32 ps 62.5MHz, (637kHz - 10MHz) 0.28 ps 62.5MHz, (12kHz - 10MHz) 0.47 ps 20% to 80% 48 400 ps 52 % Note: Electrical parameters are quaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Note1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. Note2: This parameter is defined in accordance with JEDEC Standard 65. Note3: Please refer to the Phase Noise Plots. Phase Noise Plot 156.25MHz 14-0203 125MHz 62.5MHz 6 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator LVPECL Test Circuit Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The PI6LC48P0401 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. 3.3V or 2.5V VDD 0.1µF 10Ω VDDA 0.1µF 14-0203 10µF 7 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. A 1kΩ resistor can be tied from XTAL_IN to ground for additional protection. Ref_IN Input: For applications not requiring the use of the clock, it can be left floating. A 1kΩ resistor tied from the Ref_IN to ground can provide additional protection. LVCMOS Control Pins: All control pins have internal pulldowns; A 1kΩ resistor tied from each control pin to ground can provide additional protection. Outputs: LVPECL Outputs: All unused LVPECL outputs can be left floating. Crystal Input Interface The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 33pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF 14-0203 8 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. VDD VDD R1 Rs Ro 50Ω 0.1µF XTAL_IN Zo = Ro + Rs R2 XTAL_OUT 14-0203 9 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 PI6LC48P0401 4-Output LVPECL Networking Clock Generator Packaging Mechanical: 24-Contact TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC: MO-153F/AD 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 24-pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1312 REVISION: F 12-0374 Ordering Information Ordering Code Packaging Type Package Description Operating Temperature PI6LC48P0401LE L Pb-free & Green, 24-pin TSSOP Commercial PI6LC48P0401LIE L Pb-free & Green, 24-pin TSSOP Industrial Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336  •  www.pericom.com 14-0203 10 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014