PI6LC48P21LIE

PI6LC48P21 Single Output LVPECL Clock Generator Features Description ÎÎSingle The PI6LC48P21 is a single output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions. Using a 25MHz or 26.6MHz crystal, it can generate 125MHz or 133MHz output frequencies. differential LVPECL output ÎÎSupports the following output frequencies: 125MHz or 133MHz O ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) The PI6LC48P21 uses Pericom’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for Ethernet interface in all kind of systems. ÎÎFull 3.3V or 2.5V supply modes ÎÎCommercial and industrial ambient operating temperature BS ÎÎAvailable in lead-free package: 8-TSSOP Applications ÎÎNetworking systems O Block Diagram OSC XTAL_OUT PFD VCO /25 /5 T LE XTAL_IN Pin Configuration CLK CLK# VDDA 1 8 VDD GND 2 7 CLK XTAL_OUT 3 6 CLK# XTAL_IN 4 5 NC E 13-0096 1 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator Pinout Table Pin No. Pin Name I/O Type Description 1 VDDA Power Analog Power Supply 2 GND Power Ground 3, 4 XTAL_OUT, XTAL_IN Crystal Crystal Input and Output 5 NC 6, 7 CLK#, CLK Output Output Clock 8 VDD Power Core Power Supply No Connect O BS Output Frequency Table Xtal Frequency (MHz) Output Frequency (MHz) 25 125 26.6 133 Parameter Mode of Oscillation Minimum Typical Maximum Units 28 MHz 50 Ω 7 pF 1 mW Fundamental 22.4 Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Recomended Crystal Specification 25 T LE Frequency O Typical Crystal Requirement E Pericom recommends: a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm http://www.pericom.com/pdf/datasheets/se/FL.pdf b) b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf 13-0096 2 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator Maximum Ratings (Over operating free-air temperature range) Note: Storage Temperature............................................... -65ºC to+155ºC Ambient Temperature with Power Applied..........-40ºC to+85ºC 3.3V Analog Supply Voltage.......................................-0.5 to +3.6V ESD Protection (HBM).......................................................... 2000V Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. O DC Electrical Characteristics Symbol VDD, VDDA VDD, VDDA GND IDDA BS Power Supply DC Characterisitcs, (VDD = VDDA , TA = -40 to 85ºC) Parameter Condition Typ Max Units Core, Analog Supply Voltage 3.0 3.3 3.6 V Core, Analog Supply Voltage 2.375 2.5 2.625 V Power Supply Current 85 mA Analog Supply Current 25 mA Max Units O Min LVPECL DC Electrical Characteristics Parameter VOH Output High Voltage(1) VOL Output Low Voltage(1) Condition Min Typ VDD = 3.3V 1.9 2.4 VDD = 2.5V 1.1 1.6 VDD = 3.3V 1.2 1.6 VDD = 2.5V 0.4 0.8 T LE Symbol V V Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#. LVPECL AC Electrical Characteristics LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND Parameter fOUT Output Frequency RMS Phase Jitter, (Random)(1) t jit(Ø) tR / tF Output Rise/Fall Time oDC Output Duty Cycle Condition 125MHz, (1.875MHz - 20MHz) E Symbol Min. Typ. Max Units 112 125 140 MHz 125MHz, (12kHz - 20MHz) 0.15 ps 0.3 ps 20% to 80% 48 400 ps 52 % Note: 1. Please refer to the Phase Noise Plots. 13-0096 3 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator Phase Nosie Plot 133MHz Output 125MHz Output O O BS E T LE 13-0096 4 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator LVPECL Test Circuit ZO = 50Ω 0.01µF L = 0 ~ 10in Device O 0.01µF 50Ω 150Ω BS 150Ω ZO = 50Ω 50Ω Power Supply Filtering Techniques O As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The PI6LC48P21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. T LE 3.3V or 2.5V VDD 0.1µF 0.1µF E VDDA 10Ω * 10µF * If VDD is 2.5V, the resistor value will be different, see app note for details 13-0096 5 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator Crystal Input Interface The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. O XTAL_IN C1 33pF BS X1 18pF Parallel Crystal XTAL_OUT C2 22pF O LVCMOS to XTAL Interface VDD VDD E T LE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. R1 Rs Ro 50Ω 0.1µF XTAL_IN Zo = Ro + Rs R2 XTAL_OUT 13-0096 6 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Single Output LVPECL Clock Generator Packaging Mechanical: 8-Contact TSSOP (L) O O BS 12-0370 Ordering Information Packaging Type PI6LC48P21LE L PI6LC48P21LIE L DESCRIPTION: 8 pin, 173mil wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1308 REVISION: F Package Description Operating Temperature Pb-free & Green, 8-pin TSSOP Commercial Pb-free & Green, 8-pin TSSOP Industrial E Ordering Code T LE Notes: 1. Refer JEDEC MO-153F/AA 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DATE: 05/03/12 Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336  •  www.pericom.com 13-0096 7 www.pericom.com PI6LC48P21 Rev. A 06/19/13