PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Features
Description
ÎÎ3.3V & 2.5V supply voltage
The PI6LC48S25A is an LC VCO based low phase noise design
intended for 10GbE applications. Typical 10GbE usage assumes
a 25MHz crystal input, while the PLL loop is used to generate
the 156.25MHz and other Ethernet clock frequencies. An additional buffered crystal oscillator output is provided to serve as
a low noise reference for other circuitry.
ÎÎCrystal/CMOS input: 25 MHz
ÎÎDifferential input: 25MHz, 125MHz, and 156.25 MHz
ÎÎOutput frequencies: 312.5, 156.25, 125, 100, 50, 25MHz
ÎÎ4 Output banks with selectable output signaling: LVPECL or
LVDS
For Ethernet applications other than 10GbE, programmable
dividers allow for simultaneous output of 312.5, 156.25, 125, 100,
50, and 25MHz. This device offers both pin selection and I2C
interface to give more options to meet various system needs.
ÎÎLow 0.3ps typical integrated phase noise design: 156.25MHz
(12kHz to 20MHz)
ÎÎPLL Bypass mode for test
ÎÎPower supply noise rejection: -52 dBc typical @ VDD
ÎÎPackaging (Pb-free & Green): 56-lead 8×8mm TQFN
ÎÎIndustrial temperature support: -40C to 85C
Pin Configuration
QB_Mode0
VDD
QA_Mode
VDD_OA
QA-
QA+
FS_A
QC_Mode
VDD_OC
QC1-
QC1+
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
1
QB0+
VDD
2
41
QB0-
IN_SEL
3
40
QB1+
IN+
4
39
QB1-
IN-
5
38
VDD_OB
VDD_OSC
X_IN/CLK
6
37
QB2+
7
36
QB2-
X_OUT
8
35
QB3+
PLL_BYPASS
9
34
QB3-
I2C_ADR_SEL
10
33
VDD_OB
VDDA
11
32
QB4+
INFREQ_SEL
12
31
QB4-
FS_D0
13
30
QB5+
FS_D1
29
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
QB5-
GND
SLEW_CMOS
VDD
QB_Mode1
VDD_OD
QD0+
1
QD0-
QD_Mode
VDD_ODC
QD1
GND_ODC
FS_B
NC
SDATA
SCLK
14-0129
QC0-
QC0+
VDD_OC
FS_C
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Block Diagram
PLL_BYPASS
/A
100/125/156.25/312.5
Bank A
QA_Mode
QA
X_IN/CLK
OSC
/M
X_OUT
PLL
/B
IN+
Bank B
3
QB_Mode0
3
QB_Mode1
QB[0:2]
50/100/125/156.25
ININ_SEL
/C
50/100/125/156.25
Bank C
2
QB[3:5]
QC_Mode
QC[0:1]
INFREQ_SEL
FS_A
/D0
FS_B
FS_C
/D1
25/100/125/156.25
Bank D
25/100/125
QD_Mode
QD0
QD1
FS_D1
FS_D0
Some output frequencies can be selected only in I2C mode
Pin Description
Pin Number Pin Name
Type
1
FS_C
Input
Tri-level
Output frequency select for Bank C output
2, 27, 44
VDD
Power
–
Core supply
3
IN_SEL
Input
CMOS
Input select between Xtal and differential input
4
IN+
Input
5
IN-
Input
LVPECL
Differential reference input, also accepts AC-coupled LVDS, CML, HCSL
or LVPECL. Differential inputs have an internal 100Ω cross resistor.
6
VDD_OSC
Power
-
Power supply for Xtal Oscillator circuit
7
X_IN/CLK
Input
Xtal or clock input, connect to a 25MHz Xtal or single-ended clock
8
X_OUT
Output
Xtal output
9
PLL_BYPASS
Input
CMOS
PLL bypass, provide input frequency to Bank A, BankB, and Bank C
10
I2C_ADR_SEL Input
CMOS
I2C address selection.
11
VDDA
Power
–
Analog supply
12
INFREQ_SEL
Input
Tri-level
Input frequency selection for reference input
13
FS_D0
Input
Tri-level
Output frequency select for Bank D differential output
14
FS_D1
Input
Tri-level
Output frequency select for Bank D CMOS output
15
SCLK
Input
I2C clock input
16
SDATA
Input/
Output
I2C Data line
14-0129
Description
2
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Pin Description (cont.)
Pin Number Pin Name
Type
Description
17
NC
18
FS_B
Input
19
GND_ODC
Power
20
QD1
Output
21
VDD_ODC
Power
22
QD_Mode
Input
Tri-level
23, 24
QD0-, QD0+
Output
LVPECL/
Bank D differential output
LVDS
25
VDD_OD
Power
26
QB_Mode1
Input
Tri-level
Bank B QB3 ~ QB5 differential output control
28
SLEW_CMOS
Input
CMOS
Output slew rate control for the CMOS output
29, 30
QB5-, QB5+
Output
LVPECL/
Bank B differential output
LVDS
31, 32
QB4-, QB4+
Output
LVPECL/
Bank B differential output
LVDS
33, 38
VDD_OB
Power
34, 35
QB3-, QB3+
Output
LVPECL/
Bank B differential output
LVDS
36, 37
QB2-, QB2+
Output
LVPECL/
Bank B differential output
LVDS
39, 40
QB1-, QB1+
Output
LVPECL/
Bank B differential output
LVDS
41, 42
QB0-, QB0+
Output
LVPECL/
Bank B differential output
LVDS
43
QB_Mode0
Input
Tri-level
Bank B QB0 ~ QB2 differential output control
45
QA_Mode
Input
Tri-level
Bank A differential output control
46
VDD_OA
Power
47, 48
QA-, QA+
Output
LVPECL/
Bank A differential output
LVDS
49
FS_A
Input
Tri-level
Output frequency select for Bank A
50
QC_Mode
Input
Tri-level
Bank C differential output control
51, 56
VDD_OC
Power
52, 53
QC1-, QC1+
Output
LVPECL/
Bank C differential output
LVDS
54, 55
QC0-, QC0+
Output
LVPECL/
Bank C differential output
LVDS
E-pad
GND
Power
14-0129
Reserved pin. Do not connect this pin
Tri-level
Output frequency select for Bank B
Ground for bank D CMOS output
CMOS
Bank D output 1
Power supply for bank D CMOS output
Bank D differential output control
Power supply for bank D differential outputs
Power supply for bank B differential outputs
Power supply for bank A differential outputs
Power supply for bank A differential outputs
Connect to ground, use thermal vias
3
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Reference Input Frequency Select Table
Input MUX Selection
IN_SEL
Input Source
INFREQ_SEL
Reference Input
0
Crystal Input (X_IN/CLK, X_OUT)
0
25MHz
1
Differential Input (IN+, IN-)
1
125MHz
NC
Crystal Input (X_IN/CLK, X_OUT)
NC
156.25MHz
PLL Bypass Control Function
PLL_BYPASS
PLL operation
0
PLL enabled
1
PLL bypassed
Bank A/B/C/D Differential Output Control
QA_
Mode
QA
QB_
Mode0
QB[2:0]
QB_
Mode1
QB[5:3]
QC_
Mode
QC[1:0]
QD_
Mode
QD0
0
LVPECL
0
LVPECL
0
LVPECL
0
LVPECL
0
LVPECL
1
LVDS
1
LVDS
1
LVDS
1
LVDS
1
LVDS
NC
Hi-Z
NC
Hi-Z
NC
Hi-Z
NC
Hi-Z
NC
Hi-Z
Bank A/B/C Output Frequency Control Table
FS_A
Bank A Output
Freq.
FS_B
Bank B Output
Freq.
FS_C
Bank C Output
Freq.
0
156.25MHz
0
156.25MHz
0
156.25MHz
1
125MHz
1
125MHz
1
125MHz
NC
312.5MHz
NC
50MHz
NC
100MHz
Bank D Output Frequency Control Table
FS_D0
Bank D Diff.
Output Freq.
FS_D1
Bank D CMOS
Output Freq.
0
156.25MHz
0
Hi-Z
1
125MHz
1
125MHz
NC
f IN
NC
f IN
Output Slew Rate Control Table
I2C Address Selection Table
SLEW_CMOS
Output Slew rate
I2C_ADR_SEL
I2C Address
0
Normal mode
0
DC (h)
1
Slow mode
1
DE (h)
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PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................... –65°C to +150°C
Supply Voltage to Ground Potential, VDD .......................–0.5V to +4.6V
ESD Protection (HBM) ...................................................................... 2000 V
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Operating Conditions
Symbol
Parameters
VDD
Core Power Supply Voltage
VDD_OX
Output Power Supply Voltage
VDDA
Analog Power Supply Voltage
IDD
Power Supply Current
IDD_O
Power Supply Current for Outputs
IDDA
Analog Power Supply Current
TA
Ambient Temperature
Conditions
Min..
Typ.
Max.
Units
2.97
3.3
3.63
V
2.375
2.5
2.625
V
2.97
3.3
3.63
V
2.375
2.5
2.625
V
2.97
3.3
3.63
V
2.375
2.5
2.625
V
50
mA
All outputs loaded, Diff.
outputs are LVPECL
525
mA
All outputs loaded, Diff.
outputs are LVDS
242
mA
45
mA
85
°C
Max.
Units
–40
Input Electrical Characteristics
Symbol
Parameters
Rpu
Internal pull up resistance
51
KW
Rdn
Internal pull down resistance
51
KW
CXTAL
Internal capacitance on X_IN and
X_OUT pins
12
pF
14-0129
Conditions
5
Min.
Typ.
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
LVCMOS DC Electrical Characteristics
Symbol
Parameters
Conditions
Min..
VIH
Input High Voltage
VDD = 3.3V ±10%
VIL
Input Low Voltage
IIH
Input High Current
VIN = VDD max.
IIL
Input Low Current
VIN = 0V
Max.
Units
2
VDD +0.3
V
VDD = 2.5V ±5%
1.7
VDD +0.3
V
VDD = 3.3V ±10%
-0.3
0.8
V
VDD = 2.5V ±5%
-0.3
0.5
V
150
mA
VDD = VDD_ODC =3.3V ±10%;
VOH
Output High Voltage
IOH = -12mA
VDD = VDD_ODC =2.5V ±5%;
IOH = -8mA
Typ.
-150
µA
2.6
V
1.8
V
VDD = VDD_ODC =3.3V ±10%;
VOL
Output Low Voltage
IOH = 12mA
VDD = VDD_ODC =2.5V ±5%;
IOH = 8mA
TDC
Input Duty Cycle
ROUT
CMOS Output impedance
CIN
Input Capacitance
35
VDD_ODC =3.3V
24
VDD_ODC =2.5V
30
0.5
V
0.5
V
65
%
W
3.5
pF
Differential Input DC Characteristics
Symbol
Parameters
Conditions
Min..
VIH
Input High Voltage
VIL
Input Low Voltage
VDD - 2.0
VCM
Input Bias Voltage
0.5
R IN
Input Differential Impedance1
80
VIN-PP
Input Differential Swing
Differential peak to peak
Typ.
Max.
Units
VDD - 0.7
V
V
100
0.3
VDD - 0.85
V
120
W
2.6
V
Note: 1. Differential input can be AC or DC coupled.
Crystal Characteristic
Parameters
Description
Min.
Typ
Max.
Units
OSCmode
Mode of Oscillation
FREQ
Frequency
ESR1
Equivalent Series Resistance
Cload
Load Capacitance
Cshunt
Shunt Capacitance
7
pF
Drive Level
250
uW
Fundamental
10
25
40
MHz
50
W
18
pF
Note: 1. ESR value is dependent upon frequency of oscillation
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PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
LVPECL Output DC Characteristics
(1)
Symbol
Parameters
Condition
Min.
VOPP
Output peak-peak Voltage
Single-ended
VOH
Output High Voltage
VOL
Output Low Voltage
Outputs terminated with 50Ω to
VDD_OX - 2V
Typ.
Max.
0.78
Units
V
VDD_OX - 1.4
VDD_OX - 0.7
V
VDD_OX - 2.0
VDD_OX - 1.3
V
Max.
Units
0.454
V
50
mV
1.375
V
50
mV
LVDS Output DC Characteristics (1)
Symbol
Parameters
Condition
Min.
VOPP
Output Peak-peak Voltage
Single-ended
0.247
DVOPP
VOPP Magnitude Change
VOS
Output Offset Voltage
DVOS
VOS Magnitude Change
Typ.
1.125
AC Output Characteristics (see test configurations)
(1)
TA=-40C to 85C; V DD =3.3V+10%, V DD_O =3.3V+10%
Symbol
fOUT
Parameters
Output Frequency
Condition
Min..
Typ.
Max.
Units
LVCMOS
125
MHz
LVPECL
312.5
MHz
312.5
MHz
850
ps
2.0
ns
400
ps
LVDS
Rise and Fall Time;
tR / tF
20% ~80%
tDC
Duty Cycle
tjPHASE
Integrated phase jitter (RMS)
Single-Side Band Phase
Noise
fN
Power Supply Noise Rejection
PSNR
LVCMOS
Normal Mode(2)
150
400
Slow Mode(3)
LVPECL, LVDS
250
LVCMOS
45
55
%
LVPECL, LVDS
48
52
%
Bank A at 312.5MHz only
47
53
%
12kHz-20MHz @ 156.25MHz,
25MHz Xtal input
0.3
ps
10kHz-5MHz @ 25MHz, 25MHz
Xtal input
0.33
ps
156.25MHz,
25MHz Xtal
input
Offset 1kHz
-117
Offset 10kHz
-130
Offset 100kHz
-134
Offset 1MHz
-139
Offset 10MHz
-154
VDD, 50mVpp, 10k-1.5MHz
-52
VDDA, 50mVpp, 10k-1.5MHz
-65
VDD_Ox, 50mVpp, 10k-1.5MHz
-50
dBc/
Hz
dBc
tSTARTUP
Start time
10
ms
tLOCK
PLL lock time
20
ms
14-0129
7
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Note:
1. VDD_O = 3.3 is not valid with V DD = 2.5V
2. Normal mode: All measurements are based on 20% to 80% of the single-ended waveform, Load is 4" trace and 4pF.
3. Slow mode: All measurements are based on 20% to 80% of the single-ended waveform, Load is 8" trace and 7pF.
14-0129
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PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Serial Data Interface (I2C compatible)
PI6LC48S25A is a slave only device that supports block read and block write protocol using a single 7-bit address and read/write bit as
shown below.
Read and write block transfers can be stopped after any complete byte transfer.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal
pull-up resistors have a size of 50kW typical.
Address Assignment
A6
A5
1
A4
1
A3
0
A2
1
1
A1
A0
R/W
1
I2C_ADR_SEL
1/0
How to Write
1 bit
7 bits
1 bit
1 bit
Start bit
Address
W(0)
Ack
8 bits
1 bit
Data Byte
(D)
Ack
8 bits
Data Byte
(D+1)
1 bit
Ack
8 bits
Data Byte
.......
(D+N)
1 bit
1 bit
NAck
Stop bit
1 bit
1 bit
Ack
Stop bit
How to Read
1 bit
7 bits
1 bit
1 bit
Start bit
Address
R(1)
Ack
8 bits
1 bit
Data Byte
(D)
Ack
8 bits
1 bit
Data Byte
Ack
(D+1)
8 bits
Data Byte
.....
(D+N)
Output Frequency I2C bit Control Table
FS_A (2-bit) Bank A Freq.
FS_B (2-bit) Bank B Freq.
FS_C (2-bit) Bank C Freq.
00
156.25MHz
00
156.25MHz
00
156.25MHz
01
312.5MHz
01
50MHz
01
100MHz
10
125MHz
10
125MHz
10
125MHz
11
100MHz
11
100MHz
11
50MHz
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PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Output Frequency I2C bit Control Table (cont.)
Input Freq. I2C bit Control Table
FS_D0 (2-bit)
Diff Freq.
FS_D1 (2-bit) CMOS Freq.
INFREQ_SEL (2-bit)
Input Freq.
00
156.25MHz
00
Output disabled
00
25MHz
01
f IN
01
f IN
01
156.25MHz
10
125MHz
10
125MHz
10
125MHz
11
100MHz
11
100MHz
11
100MHz
Byte 0: Output Frequency Selection Register
Bit
Control Function Description
Type
Power Up
Condition
7
FS_C (1)
RW
0
6
FS_C (0)
RW
0
5
FS_B (1)
RW
0
4
FS_B (0)
RW
0
3
FS_A (1)
RW
0
2
FS_A (0)
RW
0
1
Vendor ID
RW
0
0
Vendor ID
RW
0
Bank C output divider
Bank B output divider
Bank A output divider
0
1
See FS_C I2C control table
See FS_B I2C control table
See FS_A I2C control table
Byte 1: Output Frequency Selection and Misc. Register
Bit
Control Function Description
Type
Power Up
Condition
0
1
7
I2C pin control
Determine external pins or I2C control mode
RW
0
External pins
I 2C
6
I2C_ADR_SEL
Select I2C write address
RW
0
DC(h)
DE(h)
5
INFREQ_SEL (1)
RW
0
4
INFREQ_SEL (0)
RW
0
See INFREQ_SEL I2C control
table
3
FS_D1 (1)
RW
1
2
FS_D1 (0)
RW
1
1
FS_D0 (1)
RW
1
0
FS_D0 (0)
RW
1
14-0129
Input frequency selection
Bank D CMOS output divider
Bank D Diff. output divider
10
See FS_D1 I2C control table
See FS_D0 I2C control table
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Byte 2: Output Enable Selection for Bank A and Bank B Register
Type
Power Up
Condition
0
1
Output enable bit for QB5
RW
0
Enable
Disable
OE for QB4
Output enable bit for QB4
RW
0
Enable
Disable
4
OE for QB3
Output enable bit for QB3
RW
0
Enable
Disable
3
OE for QB2
Output enable bit for QB2
RW
0
Enable
Disable
2
OE for QB1
Output enable bit for QB1
RW
0
Enable
Disable
1
OE for QB0
Output enable bit for QB0
RW
0
Enable
Disable
0
OE for QA
Output enable bit for QA
RW
0
Enable
Disable
Bit
Control Function Description
7
Reserved
6
OE for QB5
5
Byte 3: Output Enable and Output Type Selection for Bank C and D Register
Type
Power Up
Condition
0
1
Output Type Select QD Diff. output
RW
0
LVPECL
LVDS
QC1
Output Type Select QC1
RW
0
LVPECL
LVDS
4
QC0
Output Type Select QC0
RW
0
LVPECL
LVDS
3
OE for QD1
Output enable bit for QD1
RW
0
Enable
Disable
2
OE for QD0
Output enable bit for QD0
RW
0
Enable
Disable
1
OE for QC1
Output enable bit for QC1
RW
0
Enable
Disable
0
OE for QC0
Output enable bit for QC0
RW
0
Enable
Disable
Bit
Control Function Description
7
Reserved
6
QD0
5
Byte 4: Output Type Selection for Bank A and Bank B Register
Type
Power Up
Condition
0
1
Output Type Select QB5
RW
0
LVPECL
LVDS
QB4
Output Type Select QB4
RW
0
LVPECL
LVDS
4
QB3
Output Type Select QB3
RW
0
LVPECL
LVDS
3
QB2
Output Type Select QB2
RW
0
LVPECL
LVDS
2
QB1
Output Type Select QB1
RW
0
LVPECL
LVDS
1
QB0
Output Type Select QB0
RW
0
LVPECL
LVDS
0
QA
Output Type Select QA
RW
0
LVPECL
LVDS
Bit
Control Function Description
7
Reserved
6
QB5
5
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PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Byte 5: Misc. Register
Control Function Description
7
Reserved
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
PLL_BYPASS
PLL bypass function
RW
2
SLEW_CMOS
Output slew rate control for the CMOS output
RW
1
Reserved
0
IN_SEL
14-0129
Type
Power Up
Condition
Bit
0
1
0
PLL is enabled
PLL is bypassed
0
Normal mode
Slow mode
Crystal
Reference
0
Input selection
RW
12
0
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Phase Noise Plots
156.25MHz LVDS Clock
25MHz LVPECL Clock
14-0129
13
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
LVPECL/LVDS Buffer
VDD_Ox
Z o = 50
L = 0 ~ 10 in.
100
Z o = 50
150*
150*
* remove for LVDS
Figure 1. LVPECL and LVDS Test Circuit
[+VDD]
[+VDD_O]
VDDA
VDD
VDD_O
GND
R = 22Ω
Z = 50Ω
4” ~ 8” trace
4~7pF
Figure 2. CMOS Test Circuit
3.3V ± 10%
2.5V ± 5%
VDD_Ox
0.1µF
10Ω∗
VDDA
0.1µF
10µF
* The resistor value may be
different for 2.5V supply
Figure 3. Power Supply Filter
14-0129
14
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Crystal circuit connection
The following diagram shows PI6LC48S25A crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1=18pF, C2=18pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different
board layouts.
Crystal Oscillator Circuit
X_IN
C1
18pF
SaRonix-eCera
FL2500047
Crystal�(CL�=�18pF)
X_OUT
C2
18pF
Crystal Circuit Oscillator
Recommended Crystal Specification
Pericom recommends:
a) FY2500081, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
b) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
14-0129
15
PI6LC48S25A Rev A
07/23/14
PI6LC48S25A
Next Generation HiFlexTM Ethernet Network Clock Generator
Packaging Mechanical: 56-Pin TQFN (ZBB)
Note:
1. For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
Operating Temperature
PI6LC48S25AZBBIE
ZBB
56-Pin, Pb-free & Green (TQFN)
Industrial
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
14-0129
16
PI6LC48S25A Rev A
07/23/14
