PI74ALVCH16501A

PI74ALVCH16501 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16501 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE eliminating the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 300 mil wide plastic SSOP (V) The 18-bit PI74ALVCH16501 univeral bus transceiver is designed for 2.3V to 3.6V VCC operation. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and CLOCK (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The Output Enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1 PS8133A 01/31/00 PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE LE CLK Ax Bx GND VCC Truth Table(1)† Description Output Enable Input (Active HIGH) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power Inputs Output B Product Pin Configuration 1 2 56 55 GND CLKAB 3 4 5 54 53 52 B1 6 7 8 51 50 56-PIN 49 B3 48 47 B5 11 12 13 46 45 44 GND 14 15 16 43 42 41 B9 17 18 40 39 B12 GND A13 19 A14 A15 20 21 38 37 36 VCC A16 22 23 24 35 34 33 25 26 32 31 27 28 30 29 OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 A17 GND A18 OEBA LEBA 9 10 V-56 A-56 OEAB LEAB CLKAB A L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0‡ H L L X B0§ Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = LOW-to-HIGH Transition † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB is HIGH before LEAB goes LOW. § Output level before the indicated steady-state input conditions were established. GND B2 VCC B4 B6 B7 B8 B10 B11 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND 2 PS8133A 01/31/00 PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... –65°C to +150°C Ambient Temperature with Power Applied ........................ –40°C to +85°C Input Voltage Range, VIN ...................................................... –0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... –0.5V to VCC +0.5V DC Input Voltage .................................................................... –0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions(1) Parame te rs De s cription Te s t Conditions M in. M ax. VCC Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIN Input Voltage 0 VCC VOUT Output Voltage 0 VCC IOH IOL TA High- level Output Current Low- level Output Current 2.3 Typ. VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 Operating Free- Air Temperature Units V mA - 40 85 °C Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8133A 01/31/00 PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%) Parame te rs VCC(1) M in. Min. to Max. VCC - 0.2 VIH = 1.7V 2.3V 2.0 VIH = 1.7V 2.3V 1.7 VIH = 2.0V 2.7V 2.2 VIH = 2.0V 3.0V 2.4 VIH = 2.0V 3.0V 2.0 Te s t Conditions IOH = - 100 µA IOH = - 6 MA VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 µA IOL = 6 mA VOL IOL = 12 mA IOL = 24 mA II V Min. to Max. 0.2 VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.7 VIL = 0.8V 2.7V 0.4 VIL = 0.8V 3.0V 0.55 3.6V ±5 VI = VCC or GND VI = 0.7V 45 2.3V VI = 1.7V II (Hold)(3) Typ.(2) M ax. Units - 45 VI = 0.8V 75 3.0V VI = 2.0V µA - 75 VI = 0 to 3.6V 3.6V ±500 IOZ(4) VO = VCC or GND 3.6V ±10 ICC VI = VCC or GND 3.6V 40 3V to 3.6V 750 ∆ICC IO = 0 One input at VCC - 0.6V, Other inputs at VCC or GND CI Control Inputs VI = VCC or GND 3.3V 4 pF CIO A or B ports VO = VCC or GND 3.3V 8 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Bus Hold maximum dynamic current required to switch the input from one state to another. 4. For I/O ports, the IOZ includes the input leakage current. 4 PS8133A 01/31/00 PI74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over Operating Range Parame te rs De s cription Conditions (1) VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V M in. M ax. M in. M ax. M in. M ax. 150 0 150 0 15 0 fCLOCK Clock frequency 0 tW Pulse Duration LE high 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 2.2 2.1 1.7 1.9 1.6 1.5 1.3 1.1 1.0 Data before CLK ↑ tSU Setup time Data before LE ↓, CLK high Data before LE ↓, CLK low C L = 50pF RL = 500Ω tH Hold time Data after CLK ↑ 0.6 0.6 0.7 Data after LE ↓ CLK high or low 1.4 1.7 1.4 ∆t/∆v(2) Input Transition Rise or Fall 0 10 0 10 Units MHz ns 0 10 ns/V Notes: 1. See test circuit and waveforms. 2. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics Over Operating Range(1) Parame te rs VCC = 2.5V ± 0.2V From To Conditions (1) (Input) (Output) M in.(2) M ax. VCC = 2.7V M in.(2) 150 fMAX VCC = 3.3V ± 0.V M ax. M in.(2) 150 150 MHz A or B B or A 1.2 5.4 4.5 1 3.9 LE A or B 1.6 6.3 5.3 1.3 4.6 CLK A or B 1.7 6.7 5.6 1.4 4.9 tEN OEAB B 1.1 6.3 5.3 1.0 4.6 tDIS OEAB B 2.2 6.4 5.7 1.4 5.0 tEN OEBA A 1.4 6.8 6.0 1.1 5.0 tDIS OEBA A 2.0 5.5 4.6 1.3 4.2 tPD C L = 50pF RL = 500Ω Units M ax. ns Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r Te s t Conditions VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Units Typical CPD Power Dissipation Capacitance Outputs Enabled 44 54 6 6 CL = 50pF, f = 10 MHz Outputs Disabled pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8133A 01/31/00