PI74ALVCH16652A

PI74ALVCH16652 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-Bit Bus Transceiver and Register with 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16652 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-State, eliminating the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH16652 is a 16-bit bus transceiver and register designed for low 2.3V to 3.6V Vcc operation. It consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The device can be used as two 8-bit transceivers or one 16bit transceiver. Complementary Output Enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select Control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Circuitry used for Select Control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Product Pin Configuration 1OEAB 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2OEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin A,V 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 31 2SBA 30 29 2CLKBA Data on the A or B bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the Select Control or Output Enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-lops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are in the highimpedance state, each set of bus lines remains at its last level configuration. 1OEBA 1CLKBA Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OEBA should be tied to Vcc through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking current sourcing capability of the driver. 2OEBA 1 PS8135B 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Logic Block Diagrams 1OEBA 1OEAB 1CLKBA 56 1 55 1SBA 54 1CLKAB 2 1SAB 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 TO SEVEN OTHER CHANNELS 2OEBA 2OEAB 2CLKBA 29 28 30 2SBA 31 2CLKAB 27 2SAB 26 One of Eight Channels 1D C1 2A1 15 42 2B1 1D C1 TO SEVEN OTHER CHANNELS 2 PS8135B 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name D e s cription O EAB O utput Enable Inputs (Active HIGH) O EBA O utput Enable Inputs (Active LO W) xCLK AB, xCLK BA Clock Pulse Inputs xSAB, xSBA Select Control Inputs xAx Data Register A Inputs, Data Register B O utputs xBx Data Register B Inputs, Data Register A O utputs GND Ground VCC Power Truth Table(1) Inputs Data I/O* OEAB OEBA CLKAB CLKBA SAB SBA A1 - A8 B1 - B8 Ope ration or Function L H H or L H or L X X Input Input Isolation L H ↑ ↑ X X Input Input Store A and B data X H ↑ H or L X X Input H H ↑ ↑ X* * X Input Output L X H or L ↑ X X Unspecified* * Input Hold A, store B L L ↑ ↑ X X* * Output Input Store B in both registers L L X X X L Output Input Real- time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real- time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus & stored B data to A bus Unspecified* * Store A, hold B Store A in both registers Notes: 1. H = High Voltage Level, X = Don’t Care, L = Low Voltage Level, ↑ = LOW-to-HIGH Transition * The data output functions may be enabled or disabled by a varietyof level combinations at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. ** Select control = L; clocks can occur simultaneously. Select control = H; to load both registers, clocks must be staggered. 3 PS8135B 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 REAL-TIME TRANSFER BUS A TO B REAL-TIME TRANSFER BUS B TO A BUS BUS BUS BUS A B A B OEAB OEBA xCLKAB xCLKBA L L X X xSAB X xSBA L OEAB OEBA xCLKAB xCLKBA H H X X STORAGE FROM A AND/OR B xSBA X xSAB H xSBA X TRANSFER STORED DATA TO A AND/OR B BUS BUS BUS BUS A B A B OEAB OEBA xCLKAB xCLKBA X H ↑ X L X X ↑ L H ↑ ↑ xSAB L xSAB X X X xSBA X X X OEAB OEBA xCLKAB H L H or L xCLKBA H or L Note: 1. Cannot transfer data to A bus and B bus simultaneously. 4 PS8135B 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................. –65°C to +150°C Ambient Temperature with Power Applied ................. –40°C to +85°C Input Voltage Range, VIN ............................................ –0.5V to VCC +0.5V Output Voltage Range, VOUT ..................................... –0.5V to VCC +0.5V DC Input Voltage .......................................................... –0.5V to +5.0V DC Output Current ................................................................... 100 mA Power Dissipation ........................................................................ 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Te s t Conditions (1) De s cription VCC Supply Voltage VIH(3) Input HIGH Voltage VIL(3) Input LOW Voltage VIN(3) Input Voltage 0 VCC VOUT(3) Output Voltage 0 VCC 2.3 VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 VOL IOH(3) IOL(3) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current M ax. 0.7 VCC = 2.7V to 3.6V 0.8 VCC –0.2 VIH = 1.7V, IOH = –6mA, VCC = 2.3V 2.0 VIH = 1.7V, IOH = –12mA, VCC = 2.3V 1.7 VIH = 2.0V, IOH = –12mA, VCC = 2.7V 2.2 VIH = 2.0V, IOH = –12mA, VCC = 3.0V 2.4 VIH = 2.0V, IOH = –24mA, VCC = 3.0V 2.0 V IOL = 100µA, VIL = Min. to Max. 0.2 VIL = 0.7V, IOL = 6mA, VCC = 2.3V 0.4 VIL = 0.7V, IOL = 12mA, VCC = 2.3V 0.7 VIL = 0.8V, IOL = 12mA, VCC = 2.7V 0.4 VIL = 0.8V, IOL = 24mA, VCC = 3.0V 0.55 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 5 Units 3.6 VCC = 2.3V to 2.7V IOH = - 100µA, VCC = Min. to Max. VOH M in. Typ.(2) Parame te rs PS8135B mA 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Parame te rs D e s cription IIN Input Current IIN (HOLD) Input Hold Current Te s t Conditions (1) Typ.(2) M in. VIN = VCC or GND, VCC = 3.6V M ax. Units ±5 VIN = 0.7V, VCC = 2.3V 45 VIN = 1.7V, VCC = 2.3V –45 VIN = 0.8V, VCC = 3.0V 75 VIN = 2.0V, VCC = 3.0V –75 VIN = 0 to 3.6V, VCC = 3.6V ±500 VOUT = VCC or GND, VCC = 3.6V ±10 VCC = 3.6V, IOUT = 0µA, VIN = GND or VCC 40 VCC = 3.0V to 3.6V O ne Input at VCC - 0.6V O ther Inputs at VCC or GND 750 IOZ O utput Current (3- State O utputs) ICC Supply Current ∆ICC Supply Current per Input @ TTL HIGH CI Control Inputs VIN = VCC or GND, VCC = 3.3V 3.5 CIO A or B Ports VO = VCC or GND, VCC = 3.3V 8.5 µA pF Notes: 1. For Max or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. Timing Requirements over Operating Range Parame te rs fCLOCK tW De s cription Conditions Clock Frequency Pulse Duration CLKAB or CLKBA HIGH or LOW tSU Setup Time A before CLKAB↑ or B before CLKBA↑ tH Hold Time A after CLKAB↑ or B after CLKBA↑ VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V M in. M ax. M in. M ax. M in. M ax. 0 150 0 150 0 150 Units MHz 2.5 CL = 50pF RL = 500Ω 0.9 ns 0.9 Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 6 PS8135B 11/06/00 PI74ALVCH16652 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) Parame te rs From (INPUT) To (OUTPUT) Conditions fMAX M in. VCC = 3.3V ± 0.3V M ax. M in.(2) 150 A or B B or A CLKAB or CLKBA A or B SAB or SBA B to A tEN OE or OE tDIS OE or OE tPD VCC = 2.7V M ax. 150 MHz 5.7 1.4 5.2 7.3 2.4 6.6 7.4 1.9 6.7 A or B 5.0 1.6 4.5 A or B 5.3 1.2 4.8 10 0 10 CL = 50pF RL = 500Ω Units ns De s cription ∆t/∆v(3) Input transition Rise or Fall 0 ns/V Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r CPD Power Dissipation Capacitance Te s t Conditions Outputs Enabled Outputs Disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical CL = 50pF f = 10 MHz Units pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS8135B 11/06/00