PI74AVC+16820AE

厂商：
BCDSEMI(美台)
封装：
TSSOP56
描述：
IC FF D-TYPE SNGL 10BIT 56TSSOP

数据手册：

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数据手册
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PI74AVC+16820AE 数据手册

PI74AVC+16820 2.5V 10-Bit Flip-Flop with Dual and 3-State Outputs Features Description • PI74AVC+16820 is designed for low-voltage operation, VCC = 1.65V to 3.6V • True ±24mA Balanced Drive @ 3.3V • IOFF supports Partial power-down operation • 3.6V I/O Tolerant inputs and outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. • Industrial operation: –40°C to +85°C • Packaging (Pb-free & Green available): – 56-pin 240-mil wide plastic TSSOP (A) – 56-pin 173-mil wide plastic TVSOP (K) Pericom Semiconductor’s PI74AVC+16820, a 10-bit flip-flop designed for 1.65V to 3.6V VCC operation. It is designed with edge-triggered D-type flip- flops. On the positive transition of clock (CLK) input. The device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power-up or powerdown, OE should be tied to VCC through a pullup resistor whose minimum value is determined by the current sinking capability of the driver. Pin Configuration �� Block Diagram 1OE 2OE CLK D1 1 28 2 56 55 C1 1D 3 1Q1 1Q2 TO 9 OTHER CHANNELS 1 PS8446D 08/18/04 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs Maximum Ratings Truth Table each Flip-Flop(1) (Above which the useful life may be impaired. For user guidelines, not tested.) Inputs Supply voltage range, VCC ...................................... –0.5V to +4.6V Input voltage range, VI ............................................. –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................... –0.5V to VCC +0.5V Input clamp current, IIK (VI

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