PI74FCT273ATS

PI74FCT273T 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS Octal D Flip-Flop with Master Reset Features Description • Pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption • TTL input and output levels • Low ground bounce outputs • Extremely low static power • Hysteresis on all inputs • Industrial operating temperature range: –40°C to +85°C • Packaging (Pb-free & Green available): – 20-pin 173-mil wide plastic TSSOP (L) – 20-pin 150-mil wide plastic QSOP (Q) – 20-pin 300-mil wide plastic SOIC (S) Pericom Semiconductor’s PI74FCT273T is a 8-bit wide octal designed with eight edge-triggered D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) load and resets (clear) all flip-flops simultaneously. The register is fully edge-triggered. The D input state, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. Device models available upon request. Block Diagram D0 D1 D2 D3 D4 D5 D6 D7 CP D Q D CP Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q CP RD RD MR O0 Pin Configuration MR O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 08-0291 20 19 18 17 16 15 14 13 12 11 O1 O2 O3 Pin Description Vcc O7 D7 D6 O6 O5 D5 D4 O4 CP Pin Name MR CP D0-D7 O0-O7 GND VCC O4 O5 O6 O7 Truth Table(1) Description Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Inputs Data Outputs Ground Power 1 Mode MR Reset (Clear) L Load "1" H Load "0" H Inputs CP X ↑ ↑ DN X h l Outputs ON L H L 1. H = High Voltage Level h = High Voltage Level one setup time prior to the LOW-to-HIGH Clock transition L = Low Voltage Level l = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Don’t Care ↑ = LOW-to-HIGH Clock Transition PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ –65°C to +150°C Ambient Temperature with Power Applied ............................ -40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) ..... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V DC Input Voltage .................................................................... –0.5V to +7.0V DC Output Current .............................................................................. 120 mA Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Dissipation .....................................................................................0.5W DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 5%) Parameters Description Test Conditions(1) Min. Typ(2) Max. Units VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –15.0mA 2.4 3.0 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 64mA 0.3 0.55 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 12mA 0.3 0.50 V VIH Input HIGH Voltage Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level IIH Input HIGH Current VCC = Max. IIL Input LOW Current IOZH High Impedance IOZL Output Current VIK Clamp Diode Voltage VCC = Min., IIN = –18mA IOFF Power Down Disable VCC = GND, VOUT = 4.5V IOS Short Circuit Current VCC = Max.(3), VOUT = GND VH Input Hysteresis 2.0 V 0.8 V VIN = VCC 1 μA VCC = Max. VIN = GND –1 μA VCC = MAX. VOUT = 2.7V 1 μA VOUT = 0.5V –1 μA –1.2 V 100 μA –0.7 –60 –120 mA 200 mV Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF Notes: 1. This parameter is determined by device characterization but is not production tested. 08-0291 2 PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Test Conditions(1) Parameters Description Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 500 μA ΔICC Supply Current per per Input @ TTL HIGH VCC = Max. VIN = 3.4V(3) 0.5 2.0 mA ICCD Supply Current per Input per MHx(4) VCC = Max., Outputs Open VIN = VCC MR = Vcc, One Input Toggling VIN = GND 50% Duty Cycle 0.15 0.25 mA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fCP = 10 MHZ, 50% Duty Cycle MR = Vcc, 50% Duty Cycle One Bit toggling at fI = 5 MHZ VCC = Max., Outputs Open fCP = 10 MHZ, 50% Duty Cycle MR = VCC, 50% Duty Cycle Eight Bits toggling at fI = 2.5 MHZ, 50% Duty Cycle VIN = VCC VIN = GND VIN = 3.4V VIN = GND 1.5 3.5(5) mA 2.0 3.5(5) VIN = VCC VIN = GND VIN = 3.4V VIN = GND 3.8 7.3(5) 6.0 16.3(5) Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 08-0291 3 PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range 273T 273AT Com. 273CT Com. Com. Parameters Description Conditions Min Max Min Max Min Max Unit t PLH t PHL t PHL t PLH tSU Propagation Delay(1) CP to ON Propagation Delay(1) MR to ON Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width(2) HIGHorLOW MR Pulse Width(2) LOW CL = 50pF RL = 500Ω 2.0 13.0 2.0 7.2 2.0 5.8 ns 2.0 13.0 2.0 7.2 2.0 6.1 ns tH tw tW tREM Recovery Time MR to CP (2) 3.0 2.0 2.0 ns 2.0 1.5 1.5 ns 7.0 6.0 6.0 ns 7.0 6.0 6.0 ns 4.0 2.0 2.0 ns Notes: 1. Minimum limits are guaranteed but not tested on Propagation Delays. 2. This parameter guaranteed but not production tested. Packaging Mechanical: 20-pin SOIC (S) $/#5-%.4#/.42/,./ 0$   2%6)3)/.$ $!4%        Xƒ        2%&                    888 $%./4%3#/.42/,,).' 888 $)-%.3)/.3).-),,)-%4%23 3HULFRP6HPLFRQGXFWRU&RUSRUDWLRQ 1VW6WUHHW6DQ-RVH&$ ‡ZZZSHULFRPFRP .OTES  #ONTROLLINGDIMENSIONSINMILLIMETERS  2EF*%$%#-3 $!# 08-0291       3%!4).' 0,!.%  "3#     ƒ $%3#2)04)/. 0IN -IL7IDE3/)# 0!#+!'%#/$%3 4 PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 20-Pin TSSOP (L) DOCUMENT CONTROL NO. PD - 1311 20 REVISION: E DATE: 03/09/05 .169 .177 1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 1 .0256 BSC 0.65 4.3 4.5 .007 .012 0.19 0.30 0.45 0.75 SEATING PLANE .018 .030 .238 .269 6.1 6.7 .002 0.05 .006 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AC DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L 08-0291 5 PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 20-pin QSOP (Q) DOCUMENT CONTROL NO. 3' 20 REVISION: H .008 0.20 MIN. .150 .157 3.81 3.99 Guage Plane .010 0.254 1 .041 1.04 REF [Û 0.38 .053 1.35 .069 1.75 Detail A 1 SEATING PLANE .025 BSC 0.635 ÛÛ .016 .035 0.41 0.89 Detail A .337 8.56 .344 8.74 .058 REF 1.47 DATE: 10/22/07 .008 .013 0.20 0.33 .008 0.203 .012 0.305 .004 0.101 .010 0.254 .007 .010 0.178 0.254 .228 .244 5.79 6.19 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 • www.pericom.com Note: 1) Controlling dimensions in inches. 2) Ref:-('(&02%$' 3) Dimensions do not include mold flash, protrusions or gate burrs DESCRIPTION:3LQ,0LO Wide, QSOP PACKAGE CODE: Q 08-0291 6 PS2013F 11/10/08 PI74FCT273T Octal D Flip-Flop with Master Reset 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Ordering Code PI74FCT273TQ PI74FCT273TSE PI74FCT273ATL PI74FCT273ATS PI74FCT273ATSE PI74FCT273ATQ Package Code Q S L S S Q Speed Grade Blank Blank A A A A Package Type 20-pin QSOP Pb-free & Green, 20-pin SOIC 20-pin TSSOP 20-pin SOIC Pb-free & Green, 20-pin SOIC 20-pin QSOP Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free & Green • Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation 08-0291 • 1-800-435-2336 • www.pericom.com 7 PS2013F 11/10/08