PI74SSTVF16857
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14-Bit Registered Buffer
Product Features
Product Description
• PI74 SSTVF16857 is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Pb-free available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74SSTVF16857 series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
Logic Block Diagram
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
The 14-bit PI74SSTVF16857 universal bus driver is designed
for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
38
39
CLK
CLK
34
R
V
RESET
48
35
D1
VREF
1
CLK
Q1
Pericom’s PI74SSTVF16857 is characterized for operation from
0° to 70°C.
D
Product Pin Configuration
TO 13 OTHER CHANNELS
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
VDD
VDDQ
VREF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
1
48
D1
Q2
2
47
D2
GND
3
46
GND
VDDQ
4
45
VDD
Q3
5
44
D3
Q4
6
43
D4
Q5
7
42
D5
GND
8
41
D6
VDDQ
9
40
D7
Q6
Q7
Truth Table(1)
Inputs
Q1
Outputs
48-Pin 39
A, K 38
11
CLK
10
CLK
VDDQ
12
37
VDD
GND
13
36
GND
Q8
14
35
VREF
Q9
15
34
RESET
RESET
CLK
CLK
D
Q
VDDQ
16
33
D8
L
X
X
X
L
GND
17
32
D9
H
Q10
18
31
D10
Q11
19
30
D11
Q12
20
29
D12
VDDQ
21
28
VDD
GND
22
27
GND
Q13
23
26
D13
Q14
24
25
D14
H
↑
↓
H
Η
↑
↓
L
L
H
L or H
L or H
X
Q o( 2 )
Notes:
2. Output level before the
1. H = High Signal Level
indicated steady state
L = Low Signal Level
input conditions were
↑ = Transition LOW-to-HIGH
established.
↓ = Transition HIGH-to-LOW
X = Irrelevant
1
PS8656A
05/27/03
PI74SSTVF16857
14-Bit
Registered
Buffer
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Parame te r
Symbol
Ratings
Units
Tstg
–65 to 150
oC
VDD or VDDQ
– 0.5 to 3.6
VI
– 0.5 to VDD + 0.5
VO
– 0.5 to VDDQ + 0.5
Input Clamp Current
II K, VI < 0
– 50
Output Clamp Current
IO K, VO < 0
± 50
Continuous Output Current
IO, VO = 0 to VDDQ
± 50
VDD, VDDQ, or GND current/pin
IDD, IDDQ or GND
±100
Storage Temperature
Supply Voltage
Input
Voltage(1)
Output Voltage(1,2)
Package Thermal Impedance
A- Package
Ø JA
K- Package
V
mA
70
o
58
C/W
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level VO > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
PS8656A
05/27/03
PI74SSTVF16857
14-Bit
Registered
Buffer
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Recommended Operating Conditions
Parame te rs
VDD/VDDQ
VREF
De s cription
Core/Output Supply Voltage
Reference Voltage VREF = 0.5X
VDDQ
M in.
Nom.
M ax.
PC1600
P C 2700
2.3
2.5
2.7
P C 3200
2.5
2.6
2.7
PC1600
P C 2700
1.15
1.25
1.35
P C 3200
1.25
1.3
1.35
VREF +0.31
VIH
AC input High Voltage
Data Inputs
VIL
AC input Low Voltage
Data Inputs
VI
Input Voltage
VIH
DC Input High Voltage
VIL
DC Input Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VREF - 0.31
0
Data Inputs
VREF
Units
V
VDD
VREF +0.15
VREF –0.15
RESET
1.7
0.7
VICR
Common- Mode Input Voltage Range
VID
Peak- to- Peak Input Voltage
IOH
High- Level Output Current
–16
IOL
Low- Level Output Current
16
TA
Operating Free- Air Temperature
CLK,CLK
0.97
1.53
0.36
VDDQ +0.6
0
3
70
PS8656A
mA
ºC
05/27/03
PI74SSTVF16857
14-Bit
Registered
Buffer
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DC Electrical Characteristics for PC1600 ~ PC2700
(Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ±200mV, VDDQ = 2.5V ±200mV)
Pa ra me te rs
VIK
VO H
IDD
II = –1 8 mA
M in.
Typ. (1)
2.3V
IOH = –10 0 µA
M ax.
Units
–1.2
2 . 3 V- 2 . 7 V VDD –0 . 2 V
V
2.3V
IOL = 10 0 µA
2 . 3 V- 2 . 7 V
0.2
IOH = 8mA
2.3V
0.35
All Inp uts,
VI = VDD o r GN D
2.7V
5
S tand b y (S tatic)
RES ET = GN D
10
O p erating S tatic
VI = VIH (AC ) o r VI (AC ),
RES ET = VDD
25
Dynamic
O p erating C lo ck o nly
RES ET = VDD
VI = VIH (AC ) o r VIL(AC ),
C K and C K switching
5 0 % d uty cycle
Dynamic
O p erating - p er
each d ata inp ut
RES ET = VDD
VI = VIH (AC ) o r VIL(AC ),
C K and C K switching
5 0 % d uty cycle. O ne d ata
inp ut switching at half clo ck
freq uency, 5 0 % d uty cycle
Data inp uts
VI = VREF ± 3 10 mV
C K and C K
VIC R= 1. 2 5 V, VI(PP) = 3 6 0 mV
RES ET
VI = VC C o r GN D
IDDD
CI
VCC
IOH = –8 mA
VO L
II
Te s t Co nditio ns
IO = 0
1.95
mA
28
µA/
clo ck
MHz
9
µA/
clo ck
MHz
Data
2.7V
2.5V
µA
2.5
3.5
2.5
3.5
2.5
3.5
pF
Notes:
4. Typical values are at VDD = Nominal VDD, TA = +25°C.
4
PS8656A
05/27/03
PI74SSTVF16857
14-Bit
Registered
Buffer
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DC Electrical Characteristics for PC3200
(Over the Operating Range, TA = 0°C to +70°C, VDD = 2.6V ±100mV, VDDQ = 2.6V ±100mV)
Pa ra me te rs
VIK
VO H
IDD
II = –1 8 mA
M in.
Typ. (1)
2.5V
IOH = –10 0 µA
M ax.
Units
–1.2
2 . 5 V- 2 . 7 V VDD –0 . 2 V
V
2.5V
IOL = 10 0 µA
2 . 5 V- 2 . 7 V
0.2
IOH = 8mA
2.5V
0.35
All Inp uts,
VI = VDD o r GN D
2.7V
5
S tand b y (S tatic)
RES ET = GN D
10
O p erating S tatic
VI = VIH (AC ) o r VI (AC ),
RES ET = VDD
25
Dynamic
O p erating C lo ck o nly
RES ET = VDD
VI = VIH (AC ) o r VIL(AC ),
C K and C K switching
5 0 % d uty cycle
Dynamic
O p erating - p er
each d ata inp ut
RES ET = VDD
VI = VIH (AC ) o r VIL(AC ),
C K and C K switching
5 0 % d uty cycle. O ne d ata
inp ut switching at half clo ck
freq uency, 5 0 % d uty cycle
Data inp uts
VI = VREF ± 3 10 mV
C K and C K
VIC R= 1. 2 5 V, VI(PP) = 3 6 0 mV
RES ET
VI = VC C o r GN D
IDDD
CI
VCC
IOH = –8 mA
VO L
II
Te s t Co nditio ns
IO = 0
1.95
mA
28
µA/
clo ck
MHz
9
µA/
clo ck
MHz
Data
2.7V
2.6V
µA
2.5
3.5
2.5
3.5
2.5
3.5
pF
Notes:
4. Typical values are at VDD = Nominal VDD, TA = +25°C.
5
PS8656A
05/27/03
PI74SSTVF16857
14-Bit
Registered
Buffer
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
fclo ck
VDD =2 .5 V ± 0 . 2 V
VDD =2 .6 V ± 0 . 1 V
M in.
M in.
C lo ck F req uency
M ax.
270
2.5
270
tW
P ulse Duratio n
ta c t
Differential inp uts active time (5)
22
22
tinact
O utp ut slew rate d ifferential inp uts inactive time(6)
22
22
S etup time, fast slew rate(7, 9)
tS U
S etup time, slo w slew rate(8, 9)
Ho ld time , fast slew rate(7, 9)
th
Ho ld time, slo w slew rate(8, 9)
Data b efo re C K ↑ , C K
↑
↑
Data b efo re C K↑ , C K
Units
M ax.
MHz
2.5
0.75
0.75
0.9
0.9
0.75
0.75
0.9
0.9
ns
Notes:
5. Data inputs must be held low for a minimum time of tact min , after RESET is taken high
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low.
7. Data signal input slew rate ≥ 1 V/ns
8. Data signal input slew rate ≥ 0.5V/ns and
