PI74VCX16374
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16-Bit D-Type Flip-Flop
with 3-State Outputs
Product Features
Product Description
• The PI74VCX Family is designed for low voltage
operation, VDD = 1.8V to 3.6V
• 3.6V I/O Tolerant Inputs and Outputs
The PI74VCX16374 is particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as two 8-bit Flip-Flops or one 16-bit flipflop. On the positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up at the date
(D) inputs.
• Supports Live Insertion
• Balanced Drive, ±24mA
• Uses patented Noise Reduction Circuitry
• Typical VOLP (Output Ground Bounce)
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither load
nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the flip-flop. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
< 0.6V at VDD = 2.5V, TA = 25ºC
• Typical VOHV (Output VOH Undershoot)
< –0.6V at VDD = 2.5V, TA = 25ºC
• Power-Off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packaging (Pb-free & Green available):
To ensure the high-impedance state during power up or power
down, OE should be tied to VDD through a pullup resistor; the
minimum value of the resistor is determined by the currentsinking capability of the driver.
– 48-pin 240 mil. wide plastic TSSOP (A)
The PI74VCX family is I/O Tolerant, allowing it to operate in
mixed 1.8V/3.6V systems.
Logic Block Diagram
1OE
1CLK
1
48
>C1
2
1D1
47
1Q1
1D
To Seven Other Channels
2OE
2CLK
24
25
>C1
13
2D1
36
2Q1
1D
To Seven Other Channels
06-0204
1
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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Truth Table(1)
Product Pin Description
Pin Name
Description
OE
CLK
Output Enable Input (Active LOW)
Clock Input
Dx
Qx
Data Inputs
3-State Outputs
GND
VDD
Ground
Power
Inputs
OE
CLK
D
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Don’t Care or Irrelevant
Z = High Impedance
Product Pin Configuration
1OE
1
48
1CLK
1Q1
2
47
1D1
1Q2
3
46
1D2
GND
4
45
GND
1Q3
5
44
1D3
1Q4
6
43
1D4
VDD
7
42
VDD
1Q5
8
41
1D5
1Q6
9
40
1D6
GND
10
39
GND
1Q7
11
38
1D7
1Q8
12
37
1D8
2Q1
13
36
2D1
2Q2
14
35
2D2
GND
15
34
GND
2Q3
16
33
2D3
2Q4
17
32
2D4
VDD
18
31
VDD
2Q5
19
30
2D5
2Q6
20
29
2D6
GND
21
28
GND
2Q7
22
27
2D7
2Q8
23
26
2D8
2OE
24
25
2CLK
06-0204
Outputs
2
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD .............................................. –0.5V to 4.6V
Input Voltage Range, VI ....................................................... -0.5V to 4.6V
Output Voltage Range, VO (3-Stated) .......................... -0.5V to 4.6V
Output Voltage Range, VO(1) (Active) ............ –0.5V to VDD + 0.5V
DC Input Diode Current (IIK) VI < 0V .................................... -50mA
DC Output Diode Current (IOK)
VO < 0V ................................................................................ -50mA
VO > VDD ......................................................................................... -50mA
DC Output Source/Sink Current (IOH/IOL) ............................ ±50mA
DC VDD or GND Current per Supply Pin (ICC or GND) .... ±100mA
Storage Temperature Range, TSTG ............................ –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Notes:
1. Absolute maximum of IO must be observed.
Recommended Operating Conditions(1)
Parame te rs
De s cription
Conditions
M in.
M a x.
Operating
1.8
3.6
Data Retention Only
1.2
3.6
2. 0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
Output voltage
Output current in IOH/IOL
Δt/Δv
TA
0.8
- 0.3
3 .6
Active State
0
VDD
Off State
0
3.6
Operating free- air temperature
V
± 24
±18
±6
mA
0
10
ns/V
− 40
85
C
VDD = 3.0V to 3.6V
VDD = 2.3V to 2.7V
VDD = 1.8V
Input transistion rise or fall rate(2)
Units
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2 As measured between 0.8V and 2.0V, VDD = 3.0V.
06-0204
3
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V < VDD ≤ 3.6V)
Parame te rs
De s cription
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
Conditions
VDD
HIGH Level
Output Voltage
2.7 - 3.6
LOW Level
Output Voltage
IOH = −12mA
2. 7
IOH = −18mA
IOL = 100μA
2.7 - 3.6
0.2
IOL = 12mA
2.7
0 .4
IOL = 18mA
3 .0
0.4
0. 5
IOZ
3- STATE Output
Leakage
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
IOFF
Power- OFF
Leakage Current
0 ≤ (VI,VO) ≤ 3.6V
IDD
Quiescent Supply Current
06-0204
V
2 .2
VI = 0.0V, V1 = 3.6V
Increase in IDD per input
2.2
2.4
Input Leakage Current
ΔIDD
Units
0.8
3.0
IOL = 24mA
II
M a x.
VDD - 0.2
IOH = −24mA
VOL
Typ.
2.0
IOH = −100μA
VOH
M in.
3 .6
± 5. 0
2.7 - 3.6
±10
0
10
VI = VDD to GND
μA
20
VDD ≤ (VI,VO) ≤ 3.6V
VIH = VDD - 0.6V,
Other inputs at VDD or GND
4
2.7 - 3.6
± 20
750
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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DC Characteristics (2.3V ≤ VDD ≤ 2.7V)
Parame te rs
De s cription
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
Conditions
VDD
HIGH Level Output Voltage
LOW Level Output Voltage
Units
VDD - 0.2
IOH = - 6mA
2. 3
2 .0
IOH = - 12mA
1.8
IOH = - 18mA
1.7
V
2 . 3 - 2 .7
IOL = 12mA
0.2
0.4
2.3
IOL = 18mA
II
M ax.
0.7
2.3 - 2.7
IOL = 100μA
VOL
Typ.
1.6
IOH = - 100μA
VOH
M in.
0. 4
Input Leakage Current
V1 = 0.0V, V1 = 2.7V
IOZ
3- STATE Output Leakage
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
IOFF
Power- OFF Leakage Current 0 ≤ (VI,VO) ≤ 3.6V
IDD
Quiescent Supply Current
2 .7
± 5 .0
2.3 - 2.7
±10
0
10
VI = VDD or GND
μA
20
VDD ≤ (VI,VO) ≤ 3.6V
2.3 - 2.7
± 20
DC Characteristics (1.8V ≤ VDD ≤ 2.3V)
Parame te rs
De s cription
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
Conditions
VDD
1.8 - 2.3
LOW Level Output Voltage
IOH = - 100μA
Input Leakage Current
M a x.
V
1.4
IOL = 100μA
0.2
1.8
0.3
± 5.0
V1 = 0.0V, V1 = 1.8V
IOZ
3- STATE Output Leakage
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
IOFF
Power- OFF Leakage Current
0 ≤ (VI,VO) ≤ 3.6V
0
10
20
Quiescent Supply Current
VI = VDD or GND
1.8
IDD
VDD ≤ (VI,VO) ≤ 3.6V
1.8
± 20
06-0204
Units
0.7 x VDD
VDD - 0.2
IOL = 6mA
II
Typ.
0.2 x VDD
IOH = - 6mA
VOL
M in.
±10
5
μA
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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AC Electrical Characteristics(1)
TA = -40°C to +85°C, CL = 30pF, RL = 500Ω
VDD = 3.3V ± 0.3V
Symbol
Parame te rs
M in.
VDD = 2.5V ± 0.2V
M a x.
M in.
VDD = 1.8V
M ax.
M in.
fMAX
Maximum Clock Frequency
250
tPLH, tPHL
Prop Delay, CLK to Q
0.8
3. 0
1.0
3.9
1.5
6 .0
tPZH, tPZL
Output Enable Time
0.8
3. 5
1.0
4.6
1.5
7.0
tPHZ, tPLZ
Output Disable Time
0.8
3. 5
1. 0
3.8
1.5
5 .0
250
Units
M ax.
250
MHz
ns
tOSHL, tOSLH Output to Output Skew(2)
0.5
0.5
0.5
Notes:
1. For CL = 50pF add approximatly 300ps to AC maximum specification.
2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the same direction, either HIGH or LOW (tOSHL) or LOW to HIGH (tOSLH).
AC Setup Requirements
TA = -40ºC to +85ºC, CL = 30pF, RL = 500Ω
Symbol
Parame te rs
VDD = 3.3V ± 0.3V VDD = 2.5V ± 0.2V
M in.
Typ.
M in.
Typ.
VDD = 1.8V
M in.
tSU
Setup Time
1.5
1. 5
2.5
tH
Hold Time
1.0
1. 0
1. 0
tW
Pulse Width
1. 5
1. 5
3.0
Typ.
Units
ns
Dynamic Switching Characteristics
Symbol
Parame te rs
Conditions
VDD
TA= +25°C Typical
VOLP
Quiet Output Dynamic Peak VOL
C L = 50pF
VIH = VDD
VIL = 0V
1.8
2.5
3.3
0.25
0.6
0.8
VOLP
Quiet Output Dynamic Valley VOL
C L = 50pF
VIH = VDD
VIL = 0V
1.8
2.5
3.3
- 0.25
- 0.6
- 0.8
VOLP
C L = 50pF
Quiet Output Dynamic Valley VOH VIH = VDD
VIL = 0V
1.8
2.5
3.3
1.5
1.9
2.2
Units
V
Capacitance
Symbol
Parame te rs
Conditions
TA = +25°C Typical
CIN
Input Capacitance
VDD = 1.8, 2.5V or 3.3V, VI = 0V or VDD
6
COUT
Output Capacitance
VI = 0V or VDD, VDD = 1.8V, 2.5V or 3.3V
7
C PD
Power Dissipation
Capacitance
VI = 0V or VDD, F = 10 MHz
VDD = 1.8V, 2.5V or 3.3V
20
06-0204
6
Units
pF
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.8V - 3.6V)
2 x VDD
R1
500Ω
From Output
Under Test
Open
RL
500Ω
30pF
CL
GND
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
Setup, Hold, and Release Timing
Data
Input
tSU
tH
VDD
High-Low-High
Pulse
VDD/2
0V
VDD
VDD/2
0V
Propagaton Delay
VDD
VDD/2
0V
Timing
Input
VDD
VDD/2
Input
0V
tPHL
tPLH
VDD
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
• All input pulses are supplied by generators having the follow
ing characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2ns,
tF ≤ 2ns, measured from 10% to 90%, unless otherwise
specified.
• The outputs are measured one at a time with one transition per
measurement.
Output
VDD/2
VOL
tPHL
tPLH
VDD
Opposite Phase
Input Transition
VDD/2
0V
Enable Disable Timing
VDD
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
-0.15V
7
VOH
VDD/2
0V
(see Note B)
06-0204
VOL
tPHZ
PS8327B
10/27/06
PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-State Outputs
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Packaging Mechanical: 48-pin TSSOP (A)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.002
.006
0.05
0.15
.007
.010
.0197
BSC
0.50
0.17
0.27
0.45 .018
0.75 .030
.319
BSC
8.1
Ordering Information
Ordering Code
PI74VCX16374A
PI74VCX16374AE
Package Code
A
Package Type
48-pin TSSOP
A
Pb-free & Green, 48-pin TSSOP
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
06-0204
8
PS8327B
10/27/06