PI7C9X110
PCI Express-to-PCI
Reversible Bridge
DATASHEET
Revision 8
January 2021
1545 Barber Lane Milpitas, CA 95035
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Document Number DS40251 Rev 8-2
PI7C9X110
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Copyright © 2021 Diodes Incorporated
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PI7C9X110
Page 2 of 142
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Document Number DS40251 Rev 8-2
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© Diodes Incorporated
PI7C9X110
REVISION HISTORY
DATE
REVISION #
09/08/2006
11/21/2006
03/06/2007
2.0
2.1
2.2
05/02/2007
2.3
11/02/2007
01/03/2008
2.4
2.5
05/16/2008
2.6
09/25/2008
08/21/2009
09/14/2009
10/10/2009
04/28/2010
03/22/2011
2.6
2.7
2.8
2.9
3.0
3.1
04/27/2011
3.2
12/07/2011
3.3
02/16/2015
4.0
04/15/2015
4.1
04/21/2016
4.2
05/12/2017
4.3
09/27/2017
5
10/16/2018
6
04/22/2020
7
01/07/2021
8
DESCRIPTION
First release of 9X110 datasheet without revision suffix
Removed references to PI7C9X110A
Revised ESD ratings in “DC Specifications” section 16.2
Revised table 8-1 in section 8
Address bit[5] corrected to equal 0
Address bit[4] corrected to equal GPIO[3]
Revised logos and font types and added Industrial Temp Compliancy
Revised Industrial Temp Compliancy
Revised Minimum PCI Frequency Support to 10MHz
Added Leaded Part Number – PI7C9X110BNB
Added additional pin description to GPIO [3:0]
Revised Ordering Info Section for Leaded Part
Revised Revision ID Register definition
Updated the pin description of PCI Express Signals
PCIX Feature is removed from Datasheets
Updated Section 17 Package Information
Updated Section 1 Introduction
Updated Section 2.2 PCI Express Signals
Updated Section 7.4.38 Express Transmitter/Receiver Register – Offset 68H (bit[5:2])
Updated Section 7.5.41 Express Transmitter/Receiver Register – Offset 68H (bit[5:2])
Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode
Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode
Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode
Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode
Updated Section 2.5 JTAG Boundary Scan Signals
Updated Section 16.1 Absolute Maximum ratings
Updated Table 16-2 DC Electrical Characteristics
Added Table 16-4 PCI Express Interface - Differential Transmitter (TX) Output Characteristics
Added Table 16-5 PCI Express Interface - Differential Receiver (RX) Input Characteristics
Added Section 16.4 Operating Ambient Temperature
Added Table 16-4 PCIe Reference Clock Timing Parameters
Added Section 16 Power Sequencing
Updated Section 19 Ordering Information
Revision numbering system changed to whole number
Updated Section 19 Ordering Information
Updated Section 1.3 General Features
Added Figure 18-2 Part Marking
Updated Section 16 Power Sequencing
Added Section 16.2 Power-Off Sequence
Updated Section 16 Power Sequencing
Updated Figure 16-1 and 16-2
PREFACE
The datasheet of PI7C9X110 will be enhanced periodically when updated information is available. The technical
information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X110
(PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X110.
PI7C9X110
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© Diodes Incorporated
PI7C9X110
TABLE OF CONTENTS
1
INTRODUCTION ........................................................................................................................ 14
1.1
1.2
1.3
2
PIN DEFINITIONS ...................................................................................................................... 15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
PCI EXPRESS FEATURES ................................................................................................... 14
PCI FEATURES ..................................................................................................................... 15
GENERAL FEATURES ......................................................................................................... 15
SIGNAL TYPES ..................................................................................................................... 16
PCI EXPRESS SIGNALS ...................................................................................................... 16
PCI SIGNALS ........................................................................................................................ 16
MODE SELECT AND STRAPPING SIGNALS ................................................................... 18
JTAG BOUNDARY SCAN SIGNALS .................................................................................. 18
MISCELLANEOUS SIGNALS ............................................................................................. 18
POWER AND GROUND PINS ............................................................................................. 19
PIN ASSIGNMENTS ............................................................................................................. 20
MODE SELECTION AND PIN STRAPPING .......................................................................... 21
3.1
3.2
FUNCTIONAL MODE SELECTION .................................................................................... 21
PIN STRAPPING ................................................................................................................... 21
4
FORWARD AND REVERSE BRIDGING ................................................................................ 22
5
TRANSPARENT AND NON-TRANSPARENT BRIDGING .................................................. 24
5.1
5.2
6
PCI EXPRESS FUNCTIONAL OVERVIEW ........................................................................... 26
6.1
6.2
7
TRANSPARENT MODE ....................................................................................................... 24
NON-TRANSPARENT MODE ............................................................................................. 24
TLP STRUCTURE ................................................................................................................. 26
VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 26
CONFIGURATION REGISTERS.............................................................................................. 27
7.1
7.2
7.3
7.4
CONFIGURATION REGISTER MAP .................................................................................. 27
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 30
CONTROL AND STATUS REGISTER MAP ....................................................................... 31
PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE ................ 33
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
VENDOR ID – OFFSET 00h ................................................................................................................ 33
DEVICE ID – OFFSET 00h .................................................................................................................. 33
COMMAND REGISTER – OFFSET 04h .............................................................................................. 33
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 34
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 35
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 35
CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 36
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 36
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 36
RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 36
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 36
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 36
PI7C9X110
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PI7C9X110
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7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.4.19
7.4.20
7.4.21
7.4.22
7.4.23
7.4.24
7.4.25
7.4.26
7.4.27
7.4.28
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7.4.38
7.4.39
7.4.40
7.4.41
7.4.42
7.4.43
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7.4.59
7.4.60
7.4.61
7.4.62
7.4.63
7.4.64
7.4.65
7.4.66
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 36
SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 37
I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 37
I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 37
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 37
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 38
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 38
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 38
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 39
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 39
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 39
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 39
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 39
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 39
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 39
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 40
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 40
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 40
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 41
CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 43
RESERVED REGISTER – OFFSET 44h............................................................................................... 44
ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 44
ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 44
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 45
RESERVED REGISTERS – OFFSET 4Ch – 64h .................................................................................. 46
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h .................................................... 46
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 47
RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 47
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 47
RESERVED REGISTER – OFFSET 74h............................................................................................... 48
GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 48
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 48
CAPABILITY ID REGISTER – OFFSET 80h ....................................................................................... 48
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 48
SECONDARY STATUS REGISTER – OFFSET 80h ............................................................................. 48
BRIDGE STATUS REGISTER – OFFSET 84h ..................................................................................... 49
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 50
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 50
POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 51
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 51
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 51
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 52
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 52
RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 52
CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 52
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 52
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 53
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 53
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 53
CAPABILITY ID REGISTER – OFFSET A8h ....................................................................................... 54
NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 54
RESERVED REGISTER – OFFSET A8h .............................................................................................. 54
SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh ...................................................................... 55
SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 55
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7.4.112
7.4.113
7.4.114
7.4.115
7.4.116
7.4.117
7.4.118
7.4.119
7.4.120
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 55
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 55
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h.................................................................... 55
DEVICE CAPABILITY REGISTER – OFFSET B4h ............................................................................. 55
DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 56
DEVICE STATUS REGISTER – OFFSET B8h ..................................................................................... 57
LINK CAPABILITY REGISTER – OFFSET BCh.................................................................................. 57
LINK CONTROL REGISTER – OFFSET C0h ...................................................................................... 58
LINK STATUS REGISTER – OFFSET C0h .......................................................................................... 58
SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................. 59
SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................... 59
SLOT STATUS REGISTER – OFFSET C8h ......................................................................................... 60
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh ..................................................................... 60
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 60
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 60
HOT SWAP SWITCH DEBOUNCE COUNTER – OFFSET D4h......................................................... 61
CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 61
NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 61
VPD REGISTER – OFFSET D8h ......................................................................................................... 61
VPD DATA REGISTER – OFFSET DCh .............................................................................................. 61
RESERVED REGISTERS – OFFSET E0h – ECh ................................................................................. 61
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h ............................................................... 62
NEXT CAPABILITIES POINTER REGISTER – F0h ............................................................................ 62
MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 62
MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 62
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h ................................................................. 62
MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 62
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 63
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 63
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 63
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 63
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 63
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................... 64
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h ......................................................... 64
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 64
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ........................ 64
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 65
HEADER LOG REGISTER 2 – OFFSET 120h ..................................................................................... 65
HEADER LOG REGISTER 3 – OFFSET 124h ..................................................................................... 65
HEADER LOG REGISTER 4 – OFFSET 128h ..................................................................................... 65
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 65
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 66
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 66
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 67
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 67
RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 67
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 67
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 67
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 67
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 68
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 68
PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 68
PORT VC STATUS REGISTER – OFFSET 15Ch ................................................................................. 68
VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 68
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7.4.127
7.5
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 68
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 69
RESERVED REGISTERS – OFFSET 16Ch – 300h .............................................................................. 69
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h............................................. 69
RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 69
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 69
RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 69
PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE ...... 70
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.5.14
7.5.15
7.5.16
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7.5.37
7.5.38
7.5.39
7.5.40
7.5.41
7.5.42
7.5.43
7.5.44
7.5.45
7.5.46
VENDOR ID – OFFSET 00h ................................................................................................................ 70
DEVICE ID – OFFSET 00h .................................................................................................................. 70
COMMAND REGISTER – OFFSET 04h .............................................................................................. 70
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 71
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 72
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 72
CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 73
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 73
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 73
PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 10h ................................ 73
PRIMARY CSR I/O BASE ADDRESS REGISTER – OFFSET 14h ....................................................... 74
DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 18h .......................... 74
DONWSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 1Ch ...................................... 74
DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h ....................................... 75
DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 24h ......................... 75
RESERVED REGISTER – OFFSET 28h............................................................................................... 76
SUBSYTEM ID AND SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch .................................... 76
RESERVED REGISTER – OFFSET 30h............................................................................................... 76
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 76
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 76
PRIMARY INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................. 76
PRIMARY INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................... 76
PRIMARY MINIMUM GRANT REGISTER – OFFSET 3Ch ................................................................ 76
PRIMARY MAXIMUM LATENCY TIME REGISTER – OFFSET 3Ch ................................................. 77
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 77
CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 78
SECONDARY COMMAND REGISTER – OFFSET 44h ...................................................................... 79
SECONDARY STATUS REGISTER – OFFSET 44h ............................................................................. 80
ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 81
ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 82
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 83
SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch .......................................................... 83
SECONDARY LATENCY TIME REGISTER – OFFSET 4Ch ............................................................... 84
SECONDARY HEADER TYPE REGISTER – OFFSET 4Ch ................................................................ 84
SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 50h .......................... 84
SECONDARY CSR I/O BASE ADDRESS REGISTER – OFFSET 54h ................................................. 85
UPSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 58h ................................. 85
UPSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 5Ch............................................. 85
UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h ............................................. 86
UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 64h ................................ 86
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h .................................................... 87
MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h .................................. 88
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 88
SUBSYSTEM VENDOR ID REGISTER – OFFSET 6Ch ...................................................................... 88
SUBSYSTEM ID REGISTER – OFFSET 6Ch ....................................................................................... 89
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 89
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7.5.95
7.5.96
7.5.97
7.5.98
7.5.99
7.5.100
RESERVED REGISTER – OFFSET 74h............................................................................................... 89
BRIDGE CONTROL AND STATUS REGISTER – OFFSET 78h ......................................................... 89
GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 90
SECONDARY INTERRUPT LINE REGISTER – OFFSET 7Ch ........................................................... 91
SECONDARY INTERRUPT PIN REGISTER – OFFSET 7Ch.............................................................. 91
SECONDARY MINIMUM GRANT REGISTER – OFFSET 7Ch .......................................................... 91
SECONDARY MAXIMUM LATENCY TIMER REGISTER – OFFSET 7Ch ........................................ 91
CAPABILITY ID REGISTER – OFFSET 80h ....................................................................................... 91
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 91
SECONDARY STATUS REGISTER – OFFSET 80h ............................................................................. 91
BRIDGE STATUS REGISTER – OFFSET 84h ..................................................................................... 92
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 93
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 94
POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 94
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 94
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 94
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 95
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 95
DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET 98h ................................ 95
DOWNSTREAM MEMORY 0 SETUP REGISTER – OFFSET 9Ch...................................................... 96
CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 96
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 96
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 96
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 96
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 97
DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET A8h ................... 98
DOWSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ACh ........................................... 98
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 98
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 99
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h.................................................................... 99
DEVICE CAPABILITY REGISTER – OFFSET B4h ............................................................................. 99
DEVICE CONTROL REGISTER – OFFSET B8h............................................................................... 100
DEVICE STATUS REGISTER – OFFSET B8h ................................................................................... 101
LINK CAPABILITY REGISTER – OFFSET BCh................................................................................ 101
LINK CONTROL REGISTER – OFFSET C0h .................................................................................... 102
LINK STATUS REGISTER – OFFSET C0h ........................................................................................ 102
SLOT CAPABILITY REGISTER – OFFSET C4h ............................................................................... 102
SLOT CONTROL REGISTER – OFFSET C8h ................................................................................... 103
SLOT STATUS REGISTER – OFFSET C8h ....................................................................................... 103
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh ................................................................... 103
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ................................................................... 104
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ................................................................... 104
CAPABILITY ID REGISTER – OFFSET D8h .................................................................................... 104
NEXT POINTER REGISTER – OFFSET D8h .................................................................................... 104
VPD REGISTER – OFFSET D8h ....................................................................................................... 104
VPD DATA REGISTER – OFFSET DCh ............................................................................................ 105
UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h .................................... 105
UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h .......................................................... 105
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h ....................... 105
UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh ............................................. 106
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h ............................................................. 106
NEXT CAPABILITIES POINTER REGISTER – F0h .......................................................................... 106
MESSAGE CONTROL REGISTER – OFFSET F0h ........................................................................... 106
MESSAGE ADDRESS REGISTER – OFFSET F4h ............................................................................ 107
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7.5.101
7.5.102
7.5.103
7.5.104
7.5.105
7.5.106
7.5.107
7.5.108
7.5.109
7.5.110
7.5.111
7.5.112
7.5.113
7.5.114
7.5.115
7.5.116
7.5.117
7.5.118
7.5.119
7.5.120
7.5.121
7.5.122
7.5.123
7.5.124
7.5.125
7.5.126
7.5.127
7.5.128
7.5.129
7.5.130
7.5.131
7.5.132
7.5.133
7.5.134
7.5.135
7.5.136
7.6
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h ............................................................... 107
MESSAGE DATA REGISTER – OFFSET FCh................................................................................... 107
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h ............................ 107
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h ................ 107
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h .............................................................. 107
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 107
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 108
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................. 108
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h ....................................................... 109
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .......................................................... 109
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ...................... 109
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................. 109
HEADER LOG REGISTER 2 – OFFSET 120h ................................................................................... 109
HEADER LOG REGISTER 3 – OFFSET 124h ................................................................................... 109
HEADER LOG REGISTER 4 – OFFSET 128h ................................................................................... 110
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ......................... 110
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................. 110
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ...................... 111
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h........................ 111
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................. 111
RESERVED REGISTER – OFFSET 14Ch .......................................................................................... 112
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................. 112
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................. 112
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h .............................................................. 112
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h .................................................................... 112
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h .................................................................... 112
PORT VC CONTROL REGISTER – OFFSET 15Ch........................................................................... 112
PORT VC STATUS REGISTER – OFFSET 15Ch ............................................................................... 113
VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ........................................................... 113
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ............................................................... 113
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ................................................................... 113
RESERVED REGISTERS – OFFSET 16Ch – 300h ............................................................................ 113
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h........................................... 113
RESERVED REGISTERS – OFFSET 308h – 30Ch ............................................................................ 113
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ........................................... 114
RESERVED REGISTERS – OFFSET 314h – FFCh ........................................................................... 114
CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE 115
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
7.6.10
7.6.11
7.6.12
7.6.13
7.6.14
7.6.15
7.6.16
7.6.17
RESERVED REGISTERS – OFFSET 000h TO 004h .......................................................................... 115
DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER – OFFSET 008h ............................ 115
DOWNSTREAM MEMORY 2 SETUP REGISTER – OFFSET 00Ch.................................................. 115
DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER – OFFSET 010h ............................ 115
DOWNSTREAM MEMORY 3 SETUP REGISTER – OFFSET 014h .................................................. 116
DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 018h ........................ 116
RESERVED REGISTERS – OFFSET 01Ch TO 030h ......................................................................... 116
UPSTREAM MEMORY 3 SETUP REGISTER – OFFSET 34h........................................................... 116
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 038h ............................... 117
RESERVED REGISTERS – OFFSET 03Ch TO 04Ch ........................................................................ 117
LOOKUP TABLE OFFSET – OFFSET 050h ..................................................................................... 117
LOOKUP TABLE DATA – OFFSET 054h .......................................................................................... 117
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER – OFFSET 058h ............................ 118
UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER – OFFSET 05Ch ............................ 118
UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER – OFFSET 060h ................................... 119
UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER – OFFSET 064h ................................... 119
RESERVED REGISTER – OFFSET 068C .......................................................................................... 119
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7.6.18
7.6.19
7.6.20
7.6.21
7.6.22
7.6.23
7.6.24
7.6.25
7.6.26
7.6.27
7.6.28
7.6.29
7.6.30
7.6.31
7.6.32
7.6.33
7.6.34
7.6.35
7.6.36
7.6.37
PRIMARY CLEAR IRQ REGISTER – OFFSET 070h ......................................................................... 119
SECONDARY CLEAR IRQ REGISTER – OFFSET 070h ................................................................... 119
PRIMARY SET IRQ REGISTER – OFFSET 074h .............................................................................. 120
SECONDARY SET IRQ REGISTER – OFFSET 074h ........................................................................ 120
PRIMARY CLEAR IRQ MASK REGISTER – OFFSET 078h ............................................................. 120
SECONDARY CLEAR IRQ MASK REGISTER – OFFSET 078h ....................................................... 120
PRIMARY SET IRQ MASK REGISTER – OFFSET 07Ch .................................................................. 121
SECONDARY SET IRQ MASK REGISTER – OFFSET 07Ch ............................................................ 121
RESERVED REGISTERS – OFFSET 080h TO 09Ch ......................................................................... 121
SCRATCHPAD 0 REGISTER – OFFSET 0A0h .................................................................................. 121
SCRATCHPAD 1 REGISTER – OFFSET 0A4h .................................................................................. 121
SCRATCHPAD 2 REGISTER – OFFSET 0A8h .................................................................................. 122
SCRATCHPAD 3 REGISTER – OFFSET 0ACh ................................................................................. 122
SCRATCHPAD 4 REGISTER – OFFSET 0B0h .................................................................................. 122
SCRATCHPAD 5 REGISTER – OFFSET 0B4h .................................................................................. 122
SCRATCHPAD 6 REGISTER – OFFSET 0B8h .................................................................................. 122
SCRATCHPAD 7 REGISTER – OFFSET 0BCh ................................................................................. 123
RESERVED REGISTERS – OFFSET 0C0h TO 0FCh ........................................................................ 123
LOOKUP TABLE REGISTERS – OFFSET 100h TO 1FCh ............................................................... 123
RESERVED REGISTERS – OFFSET 200h TO FFCh ........................................................................ 123
8
GPIO PINS AND SM BUS ADDRESS ..................................................................................... 124
9
CLOCK SCHEME ..................................................................................................................... 125
10
INTERRUPTS......................................................................................................................... 126
11
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ........................... 127
11.1
11.2
EEPROM (I2C) INTERFACE .............................................................................................. 127
SYSTEM MANAGEMENT BUS ........................................................................................ 127
12
HOT PLUG OPERATION .................................................................................................... 128
13
RESET SCHEME ................................................................................................................... 129
14
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ....................................................... 130
14.1
14.2
14.3
14.4
14.5
INSTRUCTION REGISTER ................................................................................................ 130
BYPASS REGISTER ........................................................................................................... 130
DEVICE ID REGISTER ....................................................................................................... 130
BOUNDARY SCAN REGISTER ........................................................................................ 131
JTAG BOUNDARY SCAN REGISTER ORDER ............................................................... 131
15
POWER MANAGEMENT .................................................................................................... 134
16
POWER SEQUENCING ....................................................................................................... 135
16.1
16.2
17
INITIAL POWER-UP (G3 TO L0) ....................................................................................... 136
POWER-OFF SEQUENCE ......................................................................................................... 137
ELECTRICAL AND TIMING SPECIFICATIONS ........................................................... 138
17.1
17.2
17.3
ABSOLUTE MAXIMUM RATINGS .................................................................................. 138
DC SPECIFICATIONS ........................................................................................................ 138
AC SPECIFICATIONS ........................................................................................................ 139
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17.4
OPERATING AMBIENT TEMPERATURE ....................................................................... 140
18
PACKAGE INFORMATION................................................................................................ 141
19
ORDERING INFORMATION.............................................................................................. 142
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PI7C9X110
TABLE OF FIGURES
FIGURE 1-1 PI7C9X110 TOPOLOGY ....................................................................................................... 14
FIGURE 4-1 FORWARD AND NON-TRANSPARENT BRIDGE MODE ............................................................. 22
FIGURE 4-2 REVERSE AND TRANSPARENT BRIDGE MODE ....................................................................... 23
FIGURE 16-1 TIMING SEQUENCE WITH UNDETERMINED I/O STATE ....................................................... 135
FIGURE 16-2 RECOMMENDED POWER SEQUENCE .................................................................................. 135
FIGURE 16-3 INITIAL POWER-UP ............................................................................................................ 136
FIGURE 17-1 PCI SIGNAL TIMING CONDITIONS....................................................................................... 139
FIGURE 18-1 PACKAGE OUTLINE DRAWING .......................................................................................... 141
FIGURE 18-2 PART MARKING ................................................................................................................ 141
LIST OF TABLES
TABLE 2-1 PIN ASSIGNMENTS.................................................................................................................. 20
TABLE 3-1 MODE SELECTION .................................................................................................................. 21
TABLE 3-2 PIN STRAPPING ....................................................................................................................... 21
TABLE 5-1 NON-TRANSPARENT REGISTERS ............................................................................................. 25
TABLE 6-1 TLP FORMAT ......................................................................................................................... 26
TABLE 7-1 CONFIGURATION REGISTER MAP (00H – FFH) ....................................................................... 27
TABLE 7-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H – FFFH) .................................. 30
TABLE 7-3 CONTROL AND STATUS REGISTER (CSR) MAP (000H – FFFH) .............................................. 31
TABLE 8-1 SM BUS DEVICE ID STRAPPING ........................................................................................... 124
TABLE 10-1 PCIE INTERRUPT MESSAGE TO PCI INTERRUPT MAPPING IN REVERSE BRIDGE MODE .......... 126
TABLE 10-2 PCI INTERRUPT TO PCIE INTERRUPT MESSAGE MAPPING IN FORWARD BRIDGE MODE ........ 126
TABLE 14-1 INSTRUCTION REGISTER CODES .......................................................................................... 130
TABLE 14-2 JTAG DEVICE ID REGISTER................................................................................................ 130
TABLE 14-3 JTAG BOUNDARY SCAR REGISTER DEFINITION ................................................................. 131
TABLE 16-1 POWER SEQUENCING AND RESET SIGNAL TIMINGS ............................................................ 136
TABLE 17-1 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 138
TABLE 17-2 DC ELECTRICAL CHARACTERISTICS ................................................................................... 138
TABLE 17-3 PCI BUS TIMING PARAMETERS .......................................................................................... 139
TABLE 17-4 PCIE REFERENCE CLOCK TIMING PARAMETERS ................................................................ 139
TABLE 17-5 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT CHARACTERISTICS
...................................................................................................................................................... 139
TABLE 17-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT CHARACTERISTICS ....... 140
TABLE 17-7 OPERATING AMBIENT TEMPERATURE ................................................................................ 140
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PI7C9X110
1
INTRODUCTION
PI7C9X110 is a PCIe-to-PCI bridge. PI7C9X110 is compliant with the PCI Express Base Specification, Revision 1.0a, the
PCI Express Card Electromechanical Specification, Revision 1.0a, the PCI Local Bus Specification, Revision 3.0 and PCI
Express to PCI Bridge Specification, Revision 1.0. PI7C9X110 supports transparent and non-transparent mode of
operations. Also, PI7C9X110B supports forward and reverse bridging. In forward bridge mode, PI7C9X110 has an x1 PCI
Express upstream port and a 32-bit PCI downstream port. The 32-bit PCI downstream port is 66MHz capable (see figure 11). In reverse bridge mode, PI7C9X110 has a 32-bit PCI upstream port and an x1 PCI Express downstream port.
PI7C9X110 configuration registers are backward compatible with existing PCI bridge software and firmware. No
modification of PCI bridge software and firmware is needed for the original operation. The PCIe port of the PI7C9X110
bridge always has higher priority over the PCI ports if the configuration registers are accessed simultaneously via the PCIe
and PCI ports.
Figure 1-1 PI7C9X110 Topology
Tx
Rx
x1 PCI Express Port
PI7C9X110
PCI 32bit / 66MHz Bus
PCI
Device
PCI
Device
PCI
Device
PCI
Device
PCI
Device
PCI
Device
PCI
Device
PCI
Device
1.1 PCI EXPRESS FEATURES
Compliant with PCI Express Base Specification, Revision 1.0a
Compliant with PCI Express Card Electromechanical Specification, Revision 1.0a
Compliant with PCI Express to PCI Bridge Specification, Revision 1.0
Physical Layer interface (x1 link with 2.5Gb/s data rate)
Lane polarity toggle
Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping)
ASPM support
Beacon support
CRC (16-bit), LCRC (32-bit)
ECRC and advanced error reporting
PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing
Maximum payload size to 512 bytes
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PI7C9X110
1.2 PCI FEATURES
Compliant with PCI Local Bus Specification, Revision 3.0
Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2
Compliant with PCI Bus PM Interface Specification, Revision 1.1
Compliant with PCI Hot-Plug Specification, Revision 1.1
Compliant with PCI Mobile Design Guide, Version 1.1
PME support
3.3V PCI signaling with 5V I/O tolerance
Provides two level arbitration support for eight PCI Bus masters
16-bit address decode for VGA
Subsystem Vendor and Subsystem Device IDs support
Capable of supporting minimum PCI Frequency of 10MHz
PCI INT interrupt or MSI Function support
1.3 GENERAL FEATURES
Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b
Compliant with System Management (SM) Bus, Version 2.0
Forward bridging (PCI Express as primary bus, PCI as secondary bus)
Reverse bridging (PCI as primary bus, PCI Express as secondary bus)
Transparent mode support
Non-transparent mode Support
GPIO support (4 bi-directional pins)
Power Management (including ACPI, CLKRUN_L, PCI_PM)
Masquerade Mode (pre-loadable vendor, device, and revision IDs)
EEPROM (I2C) Interface
SM Bus Interface
Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support
Power consumption at about 1.0 Watt in typical condition
Extended commercial/industrial temperature range (-40C to 85C)
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200,
PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local
Diodes representative.
https://www.diodes.com/quality/product-definitions/
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain
