PI7C9X111SLBFDEX

PI7C9X111SL PCI Express-to-PCI Reversible Bridge Datasheet January 2021 Revision 8 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS40298 Rev 8-2 PI7C9X111SL PR IMPORTANT NOTICE 1. DIODES INCORPORATED AND ITS SUBSIDIARIES (“DIODES”) MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. 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Copyright © 2021 Diodes Incorporated www.diodes.com PI7C9X111SL Document Number DS40298 Rev 8-2 Page 2 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR REVISION HISTORY Date Revision # 10/18/2008 04/14/2009 10/10/2009 12/14/2009 02/08/2009 02/22/2010 05/20/2010 04/27/2011 06/29/2011 05/19/2015 04/21/2016 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 01/23/2017 2.1 09/27/2017 3 07/30/2018 4 10/31/2018 5 04/09/2020 6 07/03/2020 01/18/2021 7 8 Description Released Version 1.0 Datasheets Revised General Feature to reflect I-temp Updated Pin Description of PCI Express Signals Updated Pin Description of Power and Ground Pins Updated Section 10.2 System Management Bus Updated ESD Capability Updated Section 7 GPIO Pins and SM Bus Address Updated Section 2.2 PCI Express Signals Updated Section 2.3 PCI Signals (REQ_L [3:0], GNT_L [3:0]) Added Section 15.4 PCIe Reference clock timing parameter Updated the Section 2.5 JTAG Boundary Scan Signals Updated Logo Added 6.3.93 Extended Configuration Access Address Register – Offset E0h Added 6.3.94 Extended Configuration Access Data Register – Offset E4h Added Table 15-5 PCI Express Interface - Differential Transmitter (TX) Output Characteristics AddedTable 15-6 PCI Express Interface - Differential Receiver (RX) Input Characteristics Added Section 15.4 Operating Ambient Temperature Updated Section 2.8 Pin Assignments Updated 6.3.95 Reserved Registers – Offset E8h – ECh Updated Section 15.1 AbsolutE Maximum Ratings Updated Section 15.2 DC Specifications Added Section 15 Power Sequencing Updated Section 18 Ordering Information Revision numbering system changed to whole number Updated Section 1.3 General Features Updated Section 6.3 PCI Configuration Registers Added 17-2 Part Marking Updated 6.3.76 Device Capability Register – OFFSET B4h Updated Section 18 Ordering Information Updated Section 15 Power Sequencing Added Section 15.2 Power-Off Sequence Updated 6.3.87 XPIP Configuration Register 2 – OFFSET D4h Updated Section 15 Power Sequencing PREFACE The datasheet of PI7C9X111SL will be enhanced periodically when updated information is available. Thetechnical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X111SL (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X111SL. PI7C9X111SL Document Number DS40298 Rev 8-2 Page 3 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR TABLE OF CONTENTS 1 INTRODUCTION ........................................................................................................................ 10 1.1 1.2 1.3 2 PIN DEFINITIONS ...................................................................................................................... 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 PCI EXPRESS FEATURES ................................................................................................... 11 PCI FEATURES ..................................................................................................................... 11 GENERAL FEATURES ......................................................................................................... 11 SIGNAL TYPES ..................................................................................................................... 12 PCI EXPRESS SIGNALS ...................................................................................................... 12 PCI SIGNALS ........................................................................................................................ 12 MODE SELECT AND STRAPPING SIGNALS ................................................................... 14 JTAG BOUNDARY SCAN SIGNALS .................................................................................. 14 MISCELLANEOUS SIGNALS ............................................................................................. 14 POWER AND GROUND PINS ............................................................................................. 14 PIN ASSIGNMENTS ............................................................................................................. 15 MODE SELECTION AND PIN STRAPPING.......................................................................... 16 3.1 3.2 FUNCTIONAL MODE SELECTION .................................................................................... 16 PIN STRAPPING ................................................................................................................... 16 4 FORWARD AND REVERSE BRIDGING ................................................................................ 17 5 PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 19 5.1 5.2 6 TLP STRUCTURE ................................................................................................................. 19 VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 19 CONFIGURATION REGISTER ACCESS............................................................................... 20 6.1 6.2 6.3 CONFIGURATION REGISTER MAP .................................................................................. 20 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 22 PCI CONFIGURATION REGISTERS .................................................................................. 24 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 VENDOR ID – OFFSET 00h ................................................................................................................ 24 DEVICE ID – OFFSET 00h .................................................................................................................. 24 COMMAND REGISTER – OFFSET 04h .............................................................................................. 24 PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 25 REVISION ID REGISTER – OFFSET 08h ........................................................................................... 26 CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 26 CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 27 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 27 PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 27 RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 27 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 27 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 27 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 27 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 28 I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 28 I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 28 PI7C9X111SL Document Number DS40298 Rev 8-2 Page 4 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR 6.3.17 6.3.18 6.3.19 6.3.20 6.3.21 6.3.22 6.3.23 6.3.24 6.3.25 6.3.26 6.3.27 6.3.28 6.3.29 6.3.30 6.3.31 6.3.32 6.3.33 6.3.34 6.3.35 6.3.36 6.3.37 6.3.38 6.3.39 6.3.40 6.3.41 6.3.42 6.3.43 6.3.44 6.3.45 6.3.46 6.3.47 6.3.48 6.3.49 6.3.50 6.3.51 6.3.52 6.3.53 6.3.54 6.3.55 6.3.56 6.3.57 6.3.58 6.3.59 6.3.60 6.3.61 6.3.62 6.3.63 6.3.64 6.3.65 6.3.66 6.3.67 6.3.68 6.3.69 SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 28 MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 29 MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 29 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 30 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 30 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 30 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 30 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 30 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 30 CAPABILITY POINTER – OFFSET 34h .............................................................................................. 30 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 31 INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 31 INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 31 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 31 PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 32 CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 34 RESERVED REGISTER – OFFSET 44h............................................................................................... 35 ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 35 ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 35 ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 36 RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 37 MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 37 MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 37 MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 37 MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 37 MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 37 MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 37 EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h .................................................... 38 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 39 RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 39 EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 39 RESERVED REGISTER – OFFSET 74h............................................................................................... 40 GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 40 RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 40 PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 40 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 40 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h .................................................................. 40 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h .......................................................................... 41 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 42 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 42 POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 42 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 43 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 43 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 43 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 44 RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 44 CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 44 NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 44 SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 44 CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 44 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 45 CAPABILITY ID REGISTER – OFFSET A8h ....................................................................................... 46 NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 46 PI7C9X111SL Document Number DS40298 Rev 8-2 Page 5 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR 6.3.70 6.3.71 6.3.72 6.3.73 6.3.74 6.3.75 6.3.76 6.3.77 6.3.78 6.3.79 6.3.80 6.3.81 6.3.82 6.3.83 6.3.84 6.3.85 6.3.86 6.3.87 6.3.88 6.3.89 6.3.90 6.3.91 6.3.92 6.3.93 6.3.94 6.3.95 6.3.96 6.3.97 6.3.98 6.3.99 6.3.100 6.3.101 6.3.102 6.3.103 6.3.104 6.3.105 6.3.106 6.3.107 6.3.108 6.3.109 6.3.110 6.3.111 6.3.112 6.3.113 6.3.114 6.3.115 6.3.116 6.3.117 6.3.118 6.3.119 6.3.120 6.3.121 6.3.122 RESERVED REGISTER – OFFSET A8h .............................................................................................. 46 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh ...................................................................... 46 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 46 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 46 NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 46 PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h.................................................................... 46 DEVICE CAPABILITY REGISTER – OFFSET B4h ............................................................................. 47 DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 48 DEVICE STATUS REGISTER – OFFSET B8h ..................................................................................... 49 LINK CAPABILITY REGISTER – OFFSET BCh.................................................................................. 49 LINK CONTROL REGISTER – OFFSET C0h ...................................................................................... 50 LINK STATUS REGISTER – OFFSET C0h .......................................................................................... 50 SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................. 50 SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................... 51 SLOT STATUS REGISTER – OFFSET C8h ......................................................................................... 51 XPIP CONFIGURATION REGISTER 0 – OFFSET CCh ..................................................................... 51 XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 52 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 52 L0 ENTER L1 WAITING PERIOD COUNTER – OFFSET D4h .......................................................... 52 CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 52 NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 53 VPD REGISTER – OFFSET D8h ......................................................................................................... 53 VPD DATA REGISTER – OFFSET DCh .............................................................................................. 53 EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h ............................ 53 EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h ................................... 53 RESERVED REGISTERS – OFFSET E8h – ECh ................................................................................. 53 MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h ............................................................... 54 NEXT CAPABILITIES POINTER REGISTER – F0h ............................................................................ 54 MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 54 MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 54 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h ................................................................. 54 MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 55 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 55 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 55 NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 55 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 55 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 55 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................... 56 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h ......................................................... 56 CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 56 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ........................ 57 HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 57 HEADER LOG REGISTER 2 – OFFSET 120h ..................................................................................... 57 HEADER LOG REGISTER 3 – OFFSET 124h ..................................................................................... 57 HEADER LOG REGISTER 4 – OFFSET 128h ..................................................................................... 57 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 57 SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 58 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 58 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 59 SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 59 RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 59 VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 59 VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 59 PI7C9X111SL Document Number DS40298 Rev 8-2 Page 6 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR 6.3.123 6.3.124 6.3.125 6.3.126 6.3.127 6.3.128 6.3.129 6.3.130 6.3.131 6.3.132 6.3.133 6.3.134 6.3.135 NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 60 PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 60 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 60 PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 60 PORT VC STATUS REGISTER – OFFSET 15Ch ................................................................................. 60 VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 60 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 60 VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 61 RESERVED REGISTERS – OFFSET 16Ch – 300h .............................................................................. 61 EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h............................................. 61 RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 61 REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 61 RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 61 7 GPIO PINS AND SM BUS ADDRESS....................................................................................... 62 8 CLOCK SCHEME ....................................................................................................................... 64 9 INTERRUPTS .............................................................................................................................. 68 10 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ................................. 69 10.1 10.2 10.3 EEPROM (I2C) INTERFACE ................................................................................................ 69 SYSTEM MANAGEMENT BUS .......................................................................................... 69 EEPROM AUTOLOAD CONFIGURATION ....................................................................... 69 11 HOT PLUG OPERATION .......................................................................................................... 72 12 RESET SCHEME......................................................................................................................... 73 13 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................. 74 13.1 13.2 13.3 13.4 13.5 INSTRUCTION REGISTER .................................................................................................. 74 BYPASS REGISTER ............................................................................................................. 74 DEVICE ID REGISTER ......................................................................................................... 74 BOUNDARY SCAN REGISTER .......................................................................................... 75 JTAG BOUNDARY SCAN REGISTER ORDER ................................................................. 75 14 POWER MANAGEMENT .......................................................................................................... 76 15 POWER SEQUENCING ............................................................................................................. 77 15.1 15.2 16 INITIAL POWER-UP (G3 TO L0) ......................................................................................... 77 POWER-OFF SEQUENCE .................................................................................................... 78 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................ 79 16.1 16.2 16.3 16.4 ABSOLUTE MAXIMUM RATINGS .................................................................................... 79 DC SPECIFICATIONS .......................................................................................................... 79 AC SPECIFICATIONS .......................................................................................................... 80 OPERATING AMBIENT TEMPERATURE ......................................................................... 81 17 PACKAGE INFORMATION ..................................................................................................... 82 18 ORDERING INFORMATION ................................................................................................... 83 PI7C9X111SL Document Number DS40298 Rev 8-2 Page 7 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR TABLE OF FIGURES FIGURE 1-1 PI7C9X111SL TOPOLOGY................................................................................................... 10 FIGURE 4-1 FORWARD BRIDGE MODE ..................................................................................................... 17 FIGURE 4-2 REVERSE BRIDGE MODE ....................................................................................................... 18 FIGURE 15-3 INITIAL POWER-UP .............................................................................................................. 77 FIGURE 16-1 PCI SIGNAL TIMING CONDITIONS ....................................................................................... 80 FIGURE 17-1 PACKAGE OUTLINE DRAWING ............................................................................................ 82 FIGURE 17-2 PART MARKING .................................................................................................................. 82 LIST OF TABLES TABLE 2-1 PIN ASSIGNMENTS.................................................................................................................. 15 TABLE 3-1 MODE SELECTION .................................................................................................................. 16 TABLE 3-2 PIN STRAPPING ....................................................................................................................... 16 TABLE 5-1 TLP FORMAT ......................................................................................................................... 19 TABLE 6-1 CONFIGURATION REGISTER MAP (00H – FFH) ....................................................................... 20 TABLE 6-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H – FFFH) .................................. 23 TABLE 7-1 SM BUS DEVICE ID STRAPPING ............................................................................................. 62 TABLE 9-1 PCIE INTERRUPT MESSAGE TO PCI INTERRUPT MAPPING IN REVERSE BRIDGE MODE .......... 68 TABLE 9-2 PCI INTERRUPT TO PCIE INTERRUPT MESSAGE MAPPING IN FORWARD BRIDGE MODE ........ 68 TABLE 13-1 INSTRUCTION REGISTER CODES ........................................................................................... 74 TABLE 13-2 JTAG DEVICE ID REGISTER ................................................................................................ 74 TABLE 15-1 POWER SEQUENCING AND RESET SIGNAL TIMINGS .............................................................. 78 TABLE 16-1 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 79 TABLE 16-2 DC ELECTRICAL CHARACTERISTICS .................................................................................... 79 TABLE 16-3 PCI BUS TIMING PARAMETERS ............................................................................................ 80 TABLE 16-4 PCIE REFERENCE CLOCK TIMING PARAMETERS .................................................................. 80 TABLE 16-5 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT CHARACTERISTICS80 TABLE 16-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT CHARACTERISTICS ......... 81 TABLE 16-7 OPERATING AMBIENT TEMPERATURE .................................................................................. 81 PI7C9X111SL Document Number DS40298 Rev 8-2 Page 8 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR This page intentionally left blank. PI7C9X111SL Document Number DS40298 Rev 8-2 Page 9 of 83 www.diodes.com January 2021 © Diodes Incorporated PI7C9X111SL PR 1 INTRODUCTION PI7C9X111SL is a PCIe-to-PCI/PCI-X bridge. PI7C9X111SL is compliant with the PCI Express Base Specification, Revision 1.1, the PCI Express Card Electromechanical Specification, Revision 1.1, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X111SL supports transparent mode operation. Also, PI7C9X111SL supports forward and reverse bridging. In forward bridge mode, PI7C9X111SL has an x1 PCI Express upstream port and a 32-bit PCI downstream port. The 32-bit PCI downstream port is 66MHz capable (see figure 1-1). In reverse bridge mode, PI7C9X111SL has a 32-bit PCI upstream port and an x1 PCI Express downstream port. PI7C9X111SL configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X111SL Topology Tx Rx x1 PCI Express Port PI7C9X111SL PCI 32bit / 66MHz Bus PCI Device PCI Device PCI Device PCI Device PI7C9X111SL Page 10 of 83 January 2021 Document Number DS40298 Rev 8-2 www.diodes.com © Diodes Incorporated PI7C9X111SL PR 1.1 PCI EXPRESS FEATURES             1.2 PCI FEATURES           1.3 Compliant with PCI Express Base Specification, Revision 1.1 Compliant with PCI Express Card Electromechanical Specification, Revision 1.1 Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 Physical Layer interface (x1 link with 2.5Gb/s data rate) Lane polarity toggle Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) ASPM support Beacon support CRC (16-bit), LCRC (32-bit) ECRC and advanced error reporting PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing Maximum payload size to 512 bytes Compliant with PCI Local Bus Specification, Revision 3.0 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2 Compliant with PCI Bus PM Interface Specification, Revision 1.1 Compliant with PCI Hot-Plug Specification, Revision 1.1 Compliant with PCI Mobile Design Guide, Version 1.1 3.3V PCI signaling with 5V I/O tolerance Provides two level arbitration support for four PCI Bus masters 16-bit address decode for VGA Subsystem Vendor and Subsystem Device IDs support PCI INT interrupt or MSI Function support GENERAL FEATURES                Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b Compliant with System Management (SM) Bus, Version 2.0 Forward bridging (PCI Express as primary bus, PCI as secondary bus) Reverse bridging (PCI as primary bus, PCI Express as secondary bus) Transparent mode support GPIO support (4 bi-directional pins) Power Management (including ACPI, CLKRUN_L,CLKREQ_L, PCI_PM) EEPROM (I2C) Interface SM Bus Interface Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption less than 0.45 Watt in typical condition Industrial temperature range (-40C ~ +85C) Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain