PI7C9X113SLFDE

PI7C9X113SL PCI Express-to-PCI Bridge Preliminary Datasheet Revision 0.3 3545 North 1ST Street, San Jose, CA 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com 10-0209 PI7C9X113SL PCIe-to-PCI Bridge LIFE SUPPORT POLICY Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) 2) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. Page 2 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge REVISION HISTORY DATE REVISION # 5/27/2009 9/15/2009 0.1 0.2 7/26/2010 0.3 DESCRIPTION Preliminary Datasheet Updated Section 6.3 (I/O Limit Register – Offset 1Ch, Interrupt Line Register – Offset 3Ch, Arbiter Enable Register – Offset 48h, Memory ReadSmart Range Control Register – Offset 58h, Upstream Memory Read/Write Control Register – Offset 68h, XPIP Configuration Register 1 – Offset D0h) Updated Section 12 IEEE 1149.1 Compatible JTAG Controller (Removed TRST_L) Updated Table 14-2 DC Electrical Characteristics (VDDA) Updated Section 2 Pin Definitions (Pin 22 to NC) Updated Section 6.3 PCI Configuration Registers (Offset 40h, 44h, 6Ch, A4h, D0h, D4h) Updated VDDC and VDDA voltage to 1.1V (Section 2.7, Table 14-2) PREFACE The datasheet of PI7C9X113SL will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X113SL (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X113SL. Page 3 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge TABLE OF CONTENTS 1 INTRODUCTION ........................................................................................................................ 11 1.1 1.2 1.3 1.4 2 INDUSTRY SPECIFICATION COMPLIANCE ................................................................... 11 GENERAL FEATURES......................................................................................................... 12 PCI EXPRESS FEATURES ................................................................................................... 12 PCI FEATURES ..................................................................................................................... 12 PIN DEFINITIONS...................................................................................................................... 13 SIGNAL TYPES..................................................................................................................... 13 PCI EXPRESS SIGNALS....................................................................................................... 13 PCI SIGNALS ........................................................................................................................ 13 MODE SELECT AND STRAPPING SIGNALS ................................................................... 15 JTAG BOUNDARY SCAN SIGNALS .................................................................................. 15 MISCELLANEOUS SIGNALS ............................................................................................. 15 POWER AND GROUND PINS ............................................................................................. 15 PIN ASSIGNMENTS ............................................................................................................. 17 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 MODE SELECTION AND PIN STRAPPING.......................................................................... 18 FUNCTIONAL MODE SELECTION.................................................................................... 18 PIN STRAPPING ................................................................................................................... 18 3.1 3.2 4 TRANSPARENT AND FORWARD BRIDGING..................................................................... 19 TRANSPARENT MODE ....................................................................................................... 19 FORWARD BRDIGE............................................................................................................. 19 4.1 4.2 5 PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 21 TLP STRUCTURE ................................................................................................................. 21 VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 21 5.1 5.2 6 CONFIGURATION REGISTER ACCESS............................................................................... 22 CONFIGURATION REGISTER MAP .................................................................................. 22 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 24 PCI CONFIGURATION REGISTERS .................................................................................. 26 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 VENDOR ID – OFFSET 00h ................................................................................................................ 26 DEVICE ID – OFFSET 00h.................................................................................................................. 26 COMMAND REGISTER – OFFSET 04h .............................................................................................. 26 PRIMARY STATUS REGISTER – OFFSET 04h................................................................................... 27 REVISION ID REGISTER – OFFSET 08h ........................................................................................... 28 CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 28 CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................. 28 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 28 HEADER TYPE REGISTER – OFFSET 0Ch........................................................................................ 28 RESERVED REGISTERS – OFFSET 10h TO 17h................................................................................ 29 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 29 Page 4 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 6.3.20 6.3.21 6.3.22 6.3.23 6.3.24 6.3.25 6.3.26 6.3.27 6.3.28 6.3.29 6.3.30 6.3.31 6.3.32 6.3.33 6.3.34 6.3.35 6.3.36 6.3.37 6.3.38 6.3.39 6.3.40 6.3.41 6.3.42 6.3.43 6.3.44 6.3.45 6.3.46 6.3.47 6.3.48 6.3.49 6.3.50 6.3.51 6.3.52 6.3.53 6.3.54 6.3.55 6.3.56 6.3.57 6.3.58 6.3.59 6.3.60 6.3.61 6.3.62 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 29 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 29 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 29 I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 29 I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 29 SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 29 MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 30 MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 30 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 31 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h........................................................ 31 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 31 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch............................................... 31 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h......................................................................... 31 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 31 CAPABILITY POINTER – OFFSET 34h .............................................................................................. 31 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 32 INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................... 32 INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 32 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 32 PCI DATA PREFETCHING CONTROL REGISTER – OFFSET 40h .................................................. 33 CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 35 RESERVED REGISTER – OFFSET 44h............................................................................................... 36 ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 36 ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 36 ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 37 RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 37 MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 38 MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 38 MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 38 MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 38 MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 38 MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 38 UPSTREAM MEMORY READ/WRITE CONTROL REGISTER – OFFSET 68h.................................. 39 PHY TRANSMIT/RECEIVE CONTROL REGISTER – OFFSET 6Ch .................................................. 39 EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 40 RESERVED REGISTER – OFFSET 74h............................................................................................... 42 GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 42 RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 42 PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 42 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 42 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h.................................................................. 42 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.......................................................................... 43 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 44 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 44 POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 44 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 44 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 44 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 45 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 46 SUBTRACTIVE DECODING PCI-TO-PCI BRIDGE ENABLE – OFFSET 98h.................................. 46 RESERVED REGISTERS – OFFSET 9Ch ............................................................................................ 46 Page 5 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.63 6.3.64 6.3.65 6.3.66 6.3.67 6.3.68 6.3.69 6.3.70 6.3.71 6.3.72 6.3.73 6.3.74 6.3.75 6.3.76 6.3.77 6.3.78 6.3.79 6.3.80 6.3.81 6.3.82 6.3.83 6.3.84 6.3.85 6.3.86 6.3.87 6.3.88 6.3.89 6.3.90 6.3.91 6.3.92 6.3.93 6.3.94 6.3.95 6.3.96 6.3.97 6.3.98 6.3.99 6.3.100 6.3.101 6.3.102 6.3.103 6.3.104 6.3.105 6.3.106 6.3.107 6.3.108 6.3.109 6.3.110 6.3.111 6.3.112 6.3.113 CAPABILITY ID REGISTER – OFFSET A0h....................................................................................... 46 NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 46 SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 47 CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 47 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 47 XPIP CONFIGURATION REGISTER 3 – OFFSET A4h ..................................................................... 48 CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 48 NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 48 RESERVED REGISTER – OFFSET A8h .............................................................................................. 48 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 48 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 49 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 49 NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 49 PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................... 49 DEVICE CAPABILITY REGISTER – OFFSET B4h............................................................................. 49 DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 50 DEVICE STATUS REGISTER – OFFSET B8h..................................................................................... 51 LINK CAPABILITY REGISTER – OFFSET BCh ................................................................................. 51 LINK CONTROL REGISTER – OFFSET C0h...................................................................................... 52 LINK STATUS REGISTER – OFFSET C0h.......................................................................................... 53 RESERVED REGISTER – OFFSET C4 – C8h ..................................................................................... 53 XPIP CONFIGURATION REGISTER 0 – OFFSET CCh..................................................................... 53 XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 53 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 54 CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 54 NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 54 VPD REGISTER – OFFSET D8h ......................................................................................................... 54 VPD DATA REGISTER – OFFSET DCh.............................................................................................. 54 EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h............................ 55 EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h................................... 55 RESERVED REGISTERS – OFFSET E8h – ECh ................................................................................. 55 MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h............................................................... 55 NEXT CAPABILITIES POINTER REGISTER – F0h............................................................................ 55 MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 55 MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 56 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h................................................................. 56 MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 56 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 56 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 56 NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 56 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 56 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 57 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................... 57 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h......................................................... 58 CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 58 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h........................ 58 HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 58 HEADER LOG REGISTER 2 – OFFSET 120h..................................................................................... 58 HEADER LOG REGISTER 3 – OFFSET 124h..................................................................................... 59 HEADER LOG REGISTER 4 – OFFSET 128h..................................................................................... 59 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 59 Page 6 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.114 6.3.115 6.3.116 6.3.117 6.3.118 6.3.119 6.3.120 6.3.121 6.3.122 6.3.123 6.3.124 6.3.125 6.3.126 6.3.127 6.3.128 6.3.129 6.3.130 6.3.131 6.3.132 6.3.133 6.3.134 SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 59 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 60 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 61 SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 61 RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 61 VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 61 VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 61 NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 61 PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 61 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 62 PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 62 PORT VC STATUS REGISTER – OFFSET 15Ch................................................................................. 62 VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 62 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 62 VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 62 RESERVED REGISTERS – OFFSET 16Ch – 2FCh ............................................................................. 63 EXTENDED GPIO DATA AND CONTROL REGISTER – OFFSET 300h........................................... 63 EXTENDED GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h .................................... 63 RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 63 REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 63 RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 63 7 GPIO PINS AND SM BUS ADDRESS....................................................................................... 64 8 CLOCK SCHEME ....................................................................................................................... 65 9 INTERRUPTS .............................................................................................................................. 69 10 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS................................. 70 10.1 10.2 10.3 EEPROM (I2C) INTERFACE................................................................................................ 70 SYSTEM MANAGEMENT BUS .......................................................................................... 70 EEPROM AUTOLOAD CONFIGURATION ....................................................................... 70 11 RESET SCHEME......................................................................................................................... 72 12 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................. 73 12.1 12.2 12.3 12.4 12.5 INSTRUCTION REGISTER.................................................................................................. 73 BYPASS REGISTER ............................................................................................................. 73 DEVICE ID REGISTER......................................................................................................... 73 BOUNDARY SCAN REGISTER .......................................................................................... 74 JTAG BOUNDARY SCAN REGISTER ORDER ................................................................. 74 13 POWER MANAGEMENT.......................................................................................................... 75 14 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................ 76 14.1 14.2 14.3 15 ABSOLUTE MAXIMUM RATINGS.................................................................................... 76 DC SPECIFICATIONS .......................................................................................................... 76 AC SPECIFICATIONS .......................................................................................................... 77 PACKAGE INFORMATION ..................................................................................................... 78 Page 7 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 16 ORDERING INFORMATION ................................................................................................... 79 Page 8 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge TABLE OF FIGURES FIGURE 1-1 PI7C9X113SL TOPOLOGY ............................................................................................... 11 FIGURE 4-1 FORWARD BRIDGE MODE ..................................................................................................... 20 FIGURE 8-1 TOPOLOGY OF INTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – INTERNAL FEEDBACK MODE ............................................................................................................................. 66 FIGURE 8-2 TOPOLOGY OF INTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – EXTERNAL FEEDBACK MODE ............................................................................................................................. 66 FIGURE 8-3 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – INTERNAL FEEDBACK MODE ............................................................................................................................. 67 FIGURE 8-4 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – EXTERNAL FEEDBACK MODE ............................................................................................................................. 67 FIGURE 8-5 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND EXTERNAL CLOCK BUFFERING ............... 68 FIGURE 14-1 PCI SIGNAL TIMING CONDITIONS......................................................................................... 77 FIGURE 15-1 PACKAGE OUTLINE DRAWING ............................................................................................. 78 LIST OF TABLES TABLE 2-1 PIN ASSIGNMENTS.................................................................................................................. 17 TABLE 3-1 MODE SELECTION .................................................................................................................. 18 TABLE 3-2 PIN STRAPPING FOR CLOCK POWER MANAGEMENT ............................................................... 18 TABLE 5-1 TLP FORMAT ......................................................................................................................... 21 TABLE 6-1 CONFIGURATION REGISTER MAP (00H – FFH) ....................................................................... 22 TABLE 6-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H – FFFH) .................................. 25 TABLE 7-1 SM BUS DEVICE ID STRAPPING ............................................................................................. 64 TABLE 8-1 FREQUENCY OF PCI CLKOUT WITH INTERNAL CLOCK SOURCE:........................................... 65 TABLE 9-1 PCI INTERRUPT TO PCIE INTERRUPT MESSAGE MAPPING IN FORWARD BRIDGE MODE ............ 69 TABLE 12-1 INSTRUCTION REGISTER CODES ............................................................................................ 73 TABLE 12-2 JTAG DEVICE ID REGISTER.................................................................................................. 73 TABLE 14-1 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 76 TABLE 14-2 DC ELECTRICAL CHARACTERISTICS ..................................................................................... 76 TABLE 14-3 PCI BUS TIMING PARAMETERS.............................................................................................. 77 Page 9 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge This page intentionally left blank. Page 10 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 1 INTRODUCTION PI7C9X113SL is a PCIe-to-PCI/PCI-X bridge. PI7C9X113SL is compliant with the PCI Express Base Specification, Revision 1.1, the PCI Express Card Electromechanical Specification, Revision 1.1, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X113SL supports transparent mode operation and forward bridging. PI7C9X113SL has an x1 PCI Express upstream port and a 32-bit PCI downstream port. The 32-bit PCI downstream port is 66MHz capable (see Figure 1-1). PI7C9X113SL configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X113SL Topology Tx Rx x1 PCI Express Port PI7C9X113L PCI 32bit / 66MHz Bus PCI Device 1.1 PCI Device PCI Device PCI Device INDUSTRY SPECIFICATION COMPLIANCE           Compliant with PCI Express Base Specification, Revision 1.1 Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 Compliant with PCI Express Card Electromechanical Specification, Revision 1.0a Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2 Compliant with PCI Local Bus Specification, Revision 3.0 Compliant with PCI SHPC and Subsystem Specification, Revision 1.0 Compliant with PCI Mobile Design Guide, Version 1.1 Compliant with PCI Bus PM Interface Specification, Revision 1.2 Compliant with System Management (SM) Bus, Version 2.0 Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b Page 11 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 1.2 GENERAL FEATURES               1.3 PCI EXPRESS FEATURES          1.4 Forward bridging (PCI Express as primary bus, PCI as secondary bus) x1 PCI Express interface (2.5Gb/s data rate) 32-bit PCI interface capable of 66MHz GPIO support (4 bi-directional pins). When external arbiter is used, 3 additional GPI (input) and GPO (output) pins Power Management (including ACPI, PCI_PM, CLKRUN_L and CLKREQ_L,) Transparent mode support Subtractive Decoding PCI-to-PCI bridge to support legacy device Masquerade support (user-defined vendor, device, revision, subsystem device, and subsystem vendor ID) EEPROM (I2C) Interface SM Bus Interface 10k byte buffer: 2K byte buffer for downstream memory read, 4K bytes for upstream memory read, and 2K byte buffer for memory write in both directions Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption less than 350 mW in typical condition Extended commercial temperature range (0C to 85C) Physical Layer interface (x1 link with 2.5Gb/s data rate) Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) CRC (16-bit), LCRC (32-bit) ECRC and advanced error reporting Lane polarity toggle ASPM support WAKE_L support Maximum payload size to 512 bytes CLKREQ_L support to disable Refclk at L1 and L2 state PCI FEATURES           Provides two level arbitration support for four PCI Bus masters 3.3V PCI signaling with 5V I/O tolerance PME_L support LOCK support 16-bit address decode for VGA Subsystem Vendor and Subsystem Device IDs support PCI INT interrupt or MSI Function support Adaptive fragmentation support for memory write Internal clock generator for PCI bus CLKRUN_L support to stop the PCI clock Page 12 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 2 PIN DEFINITIONS 2.1 SIGNAL TYPES TYPE OF SIGNAL - DESCRIPTIONS B I IU ID IOD OD O P G Bi-directional Input Input with pull-up Input with pull-down Bi-directional with open drain output Open drain output Output Power Ground “_L” in signal name indicates Active LOW signal 2.2 PCI EXPRESS SIGNALS NAME REFCLKP REFCLKN RP RN TP TN PERST_L PIN ASSIGNMENT 13, 12 TYPE I DESCRIPTION Reference Clock Inputs: Connect to external 100MHz differential clock. 21, 20 I PCI Express Data Inputs: Differential data receiver input signals 17, 16 O PCI Express Data Outputs: Differential data transmitter output signals 29 I PCI Express Fundamental Reset (Active LOW): PI7C9X113SL The device uses this signal reset to initialize the internal state machines. TYPE B DESCRIPTION Address / Data: Multiplexed address and data bus. Address phase is aligned with first clock of FRAME_L assertion. Data phase is aligned with IRDY_L or TRDY_L assertion. Data is transferred on rising edges of CLKOUT[0] when both IRDY_L and TRDY_L are asserted. During bus idle (both FRAME_L and IRDY_L are deasserted), PI7C9X113SL drives AD to a valid logic level when arbiter is parking to PI7C9X113SL on PCI bus. B Command / Byte Enables (Active LOW): Multiplexed command at address phase and byte enable at data phase. During address phase, the initiator drives commands on CBE [3:0] signals to start the transaction. If the command is a write transaction, the initiator will drive the byte enables during data phase. Otherwise, the target will drive the byte enables during data phase. During bus idle, PI7C9X113SL drives CBE [3:0] signals to a valid logic level when arbiter is parking to PI7C9X113SL on PCI bus. Parity Bit: Parity bit is an even parity (i.e. even number of 1’s), which generates based on the values of AD [31:0], CBE [3:0]. If PI7C9X113SL is an initiator with a write transaction, PI7C9X113SL will tri-state PAR. If PI7C9X113SL is a target and a write transaction, PI7C9X113SL will drive PAR one clock after the address or data phase. If PI7C9X113SL is a target and a read transaction, PI7C9X113SL will drive PAR one clock after the address phase and tri-state PAR during data phases. PAR is tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X113SL drives PAR to a valid logic level when arbiter is parking to PI7C9X113SL on PCI bus. FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration an access. The de-assertion of FRAME_L indicates the final data phase signaled by the initiator in burst transfers. Before being tri-stated, it is driven to a de-asserted state for one cycle. 2.3 PCI SIGNALS NAME AD [31:0] CBE_L[3:0] PIN ASSIGNMENT 125, 126, 124, 121, 122, 120, 119, 117, 113, 111, 110, 109, 108, 106, 103, 104, 90, 88, 86, 85, 83, 80, 79, 78, 75, 74, 71, 70, 68, 69, 67, 64 116, 99, 89, 76 PAR 94 B FRAME_L 63 B Page 13 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge NAME IRDY_L PIN ASSIGNMENT 97 TYPE B TRDY_L 100 B DEVSEL_L 98 B STOP_L 96 B LOCK_L 93 B PERR_L 92 B SERR_L 61 IOD REQ_L [3:0] 33, 34, 32, 31 I GNT_L [3:0] 41, 39, 40, 37 O CLKOUT [3:0] 49, 54, 56, 59 B M66EN 102 I RESET_L 46 O INTA_L INTB_L INTC_L INTD_L 36, 43, 57, 60 I DESCRIPTION IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a deasserted state for one cycle. TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a deasserted state for one cycle. Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C9X113SL waits for the assertion of this signal within 5 cycles of FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a deasserted state for one cycle. LOCK (Active LOW): Asserted by the initiator for multiple transactions to complete. PI7C9X113SL does not support any upstream LOCK transaction. Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the PCI bus interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. If SERR control is enabled, PI7C9X113SL will drive this pin on:  Address parity error  Posted write data parity error on target bus  Master abort during posted write transaction  Target abort during posted write transaction  Posted write transaction discarded  Delayed write request discarded  Delayed read request discarded  Delayed transaction master timeout  Errors reported from PCI Express port (advanced error reporting) in transparent mode. This signal is an open drain buffer that requires an external pull-up resistor for proper operation. Request (Active LOW): REQ_L’s are asserted by bus master devices to request for transactions on the PCI bus. The master devices de-assert REQ_Ls for at least 2 PCI clock cycles before asserting them again. If external arbiter is selected, REQ_L [0] will be the bus grant input to PI7C9X113SL. Also, REQ_L [3:1] will become the GPI [2:0]. When powered up, if both REQ_L[2] and REQ_L[3] and pulled low (Active LOW) and stay low in normal operation, the PI7C9X113SL will change the function of CLKOUT[3] to CLKRUN_L and CLKOUT[2] to CLKREQ_L, respectively. Grant (Active LOW): PI7C9X113SL asserts GNT_Ls to release PCI bus control to bus master devices. During idle and all GNT_Ls are de-asserted and arbiter is parking to PI7C9X113SL, PI7C9X113SL will drive AD, CBE, and PAR to valid logic levels. If external arbiter is selected, GNT_L [0] will be the bus request from PI7C9X113SL to external arbiter. Also, GNT_L [3:1] will become the GPO [2:0]. PCI Clock Outputs: PCI clock outputs are derived from the CLKIN and provide clocking signals to external PCI Devices. In external feedback mode, CLKOUT[0] becomes an input for feedback clock and CLKOUT[1:3] remain as clock outputs to provide clock signals to external PCI Devices. Please see Chapter 8 for further information. 66MHz Enable: This input is used to specify if Bridge is capable of running at 66MHz. For 66MHz operation on the PCI bus, this signal should be pulled “HIGH”. For 33MHz operation on the PCI bus, this signal should be pulled LOW. RESET_L (Active LOW): When RESET_L active, all PCI signals should be asynchronously tri-stated. Interrupt: Signals are asserted to request an interrupt. After asserted, it can be cleared by the device driver. INTA_L, INTB_L, INTC_L, INTD_L signals are inputs and asynchronous to the clock in the forward mode. Page 14 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge NAME CLKIN 2.4 PIN ASSIGNMENT 44 TYPE I DESCRIPTION PCI Clock Input: PCI Clock Input Signal connects to an external clock source. The PCI Clock Outputs CLKOUT [3:0] pins are derived from CLKIN Input. MODE SELECT AND STRAPPING SIGNALS NAME TM0 PIN ASSIGNMENT 128 TM1 23 TYPE ID ID DESCRIPTION Mode Select 0: Mode Selection Pin to select EEPROM or SM Bus. TM0=0 for EEPROM (I2C) support and TM0=1 for SM Bus support. TM0 is a strapping pin. See Table 3-1 mode selection and Table 3-2 for strapping control. Mode Select 1: Mode Selection Pin for normal operation. Set TM1=0 for normal operation. TM1=1 is reserved. TM1 is a strapping pin. See Table 3-1 mode selection and Table 3-2 for strapping control. 2.5 JTAG BOUNDARY SCAN SIGNALS 2.6 NAME TCK PIN ASSIGNMENT 26 TYPE IU TMS TDO 24 27 IU O TDI 28 IU DESCRIPTION Test Clock: TCK is the test clock to synchronize the state information and data on the PCI bus side of PI7C9X113SL during boundary scan operation. Test Mode Select: TMS controls the state of the Test Access Port (TAP) controller. Test Data Output: TDO is the test data output and connects to the end of the JTAG scan chain. Test Data Input: TDI is the test data input and connects to the beginning of the JTAG scan chain. It allows the test instructions and data to be serially shifted into the PCI side of PI7C9X113SL. MISCELLANEOUS SIGNALS NAME GPIO [3:0] PIN ASSIGNMENT 47, 48, 51, 52 TYPE B SMBCLK / SCL 3 B SMBDATA / SDA 5 B/IOD PME_L 1 I WAKE_L 4 O REXTP, REXTN NC 8, 9 I 22 - DESCRIPTION General Purpose I/O Data Pins: The 4 general-purpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space. SMBUS / EEPROM Clock Pin: When EEPROM (I2C) interface is selected (TM0=0), this pin is an output of SCL clock and connected to EEPROM clock input. When SMBUS interface is selected (TM0=1), this pin is an input for the clock of SMBUS. SMBUS / EEPROM Data Pin: Data Interface Pin to EERPOM or SMBUS. When EEPROM (I2C) interface is selected (TM0=0), this pin is a bi-directional signal. When SMBUS interface is selected (TM0=1), this pin is an open drain signal. Power Management Event Pin: Power Management Event Signal is asserted to request a change in the device or link power state. Wakeup Signal (Active LOW): This signal is asserted when PME_L pin is asserted and the link is in the L2 state External Precision Resistor: Connect an external resistor (1.43K Ohm +/- 1%) to provide a reference to both the bias currents and impedance calibration circuitry. Not Connected 2.7 POWER AND GROUND PINS NAME VDDA PIN ASSIGNMENT 15, 18 VDDA33 10 VDDC 30, 35, 45, 53, 62, 73, 81, 95, 105, 114, 127 7 VDDCAUX TYPE P P DESCRIPTION Analog Voltage Supply for PCI Express Interface: Connect to the 1.1V Power Supply. High Voltage Supply for PCI Express Interface: Connect to the 3.3V Power Supply. Core Supply Voltage: Connect to the 1.1V Power Supply. P Auxiliary Core Supply Voltage: Connect to the 1.0V Power Supply. Page 15 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge NAME VD33 VAUX VSS PIN ASSIGNMENT 25, 38, 50, 55, 58, 66 72, 77, 82, 87, 91, 101, 107, 112, 118, 123 2 TYPE P 6, 11, 14, 19, 42, 65, 84, 115 P P DESCRIPTION I/O Supply Voltage for PCI Interface: Connect to the 3.3V Power Supply for PCI I/O Buffers. Auxiliary I/O Supply Voltage for PCI interface: Connect to the 3.3V Power Supply. Ground: Connect to Ground. Page 16 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 2.8 PIN ASSIGNMENTS Table 2-1 Pin Assignments PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME PME_L VAUX SMBCLK / SCL WAKE_L SMBDAT / SDA VSS VDDCAUX REXTP REXTN VDDA33 VSS REFCLKN REFCLKP VSS VDDA TN TP VDDA VSS RN RP NC TM1 TMS VD33 TCK TDO TDI PERST_L VDDC REQ_L[0] REQ_L[1] PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME REQ_L[3] REQ_L[2] VDDC INTA_L GNT_L[0] VD33 GNT_L[2] GNT_L[1] GNT_L[3] VSS INTB_L CLKIN VDDC RESET_L GPIO[3] GPIO[2] CLKOUT[3] VD33 GPIO[1] GPIO[0] VDDC CLKOUT[2] VD33 CLKOUT[1] INTC_L VD33 CLKOUT[0] INTD_L SERR_L VDDC FRAME_L AD[0] PIN 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME VSS VD33 AD[1] AD[3] AD[2] AD[4] AD[5] VD33 VDDC AD[6] AD[7] CBE[0] VD33 AD[8] AD[9] AD[10] VDDC VD33 AD[11] VSS AD[12] AD[13] VD33 AD[14] CBE[1] AD[15] VD33 PERR_L LOCK_L PAR VDDC STOP_L PIN 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME IRDY_L DEVSEL_L CBE[2] TRDY_L VD33 M66EN AD[17] AD[16] VDDC AD[18] VD33 AD[19] AD[20] AD[21] AD[22] VD33 AD[23] VDDC VSS CBE[3] AD[24] VD33 AD[25] AD[26] AD[28] AD[27] VD33 AD[29] AD[31] AD[30] VDDC TM0 Page 17 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 3 MODE SELECTION AND PIN STRAPPING 3.1 FUNCTIONAL MODE SELECTION PI7C9X113SL uses TM1 and TM0 pins to select different modes of operations. These input signals are required to be stable during normal operation. One of the four combinations of normal operation can be selected by setting the logic values for the three mode select pins. For example, if the logic values are low for both two (TM1 and TM0) pins, the normal operation will have EEPROM (I2C) support with internal arbiter. The designated operation with respect to the values of the TM1 and TM0 pins are defined on Table 3-1: Table 3-1 Mode Selection TM1 Strapped 0 0 3.2 TM0 Strapped 0 1 Functional Mode EEPROM (I2C) support SM Bus support PIN STRAPPING If TM1 is strapped to low, PI7C9X113SL uses REQ_L[3:2] as the strapping pins at the PCIe PERST_L deassertion to enable Clock Power Management feature. Table 3-2 Pin Strapping for Clock Power Management TM1 Strapped 0 REQ_L[3:2] Strapped 2’b0 Test Functions Clock Power Management is enabled, only two PCI devices supported. CLKOUT[2] is used as CLKREQ_L CLKOUT[3] is used as CLKRUN_L Page 18 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 4 TRANSPARENT AND FORWARD BRIDGING 4.1 TRANSPARENT MODE In transparent bridge mode, base class code of PI7C9X113SL is set to be 06h (bridge device). The sub-class code is set to be 04h (PCI-to-PCI bridge). Programming interface is set to either 00h or 01h. If this interface is set to 00h, subtractive decoding is not supported. If it is set to 01h, legacy support is enabled and subtractive decoding is supported. When Subtractive Decoding PCI-to-PCI bridge is enabled by setting the legacy bit (bit 0 of offset 98h), all cycles (Memory/IO) are forwarded to downstream PCI devices. However, the Type-1 configuration cycle still should be checked for the bus number in order to be forwarded to PCI bus. The PCI-X/PCIe capability is not included in the Capability List and all PCI-X/PCIe capability registers and Extended Configuration registers are treated as reserved registers. As a result, all Write accesses are completed normally but data is discarded, and all Read accesses are returned with data value of 0. When PCI bus Subtractive Decoding Enable bit (bit 1 of 98h) is set, the device performs subtractive decode at PCI bus when the cycle is outside the range (negative decoding is used). PI7C9X113SL has type-1 configuration header. These configuration registers are the same as traditional transparent PCI-to-PCI Bridge. In fact, it is backward compatible to the software that supporting traditional transparent PCI-toPCI bridges. Configuration registers can be accessed from several different ways. For PCI Express access, PCI Express configuration transaction is in forward bridge mode. For I2C access, I2C bus protocol is used with EEPROM selected (TM0=0). For SM bus access, SM bus protocol is used with SM bus selected (TM0=1). 4.2 FORWARD BRDIGE PI7C9X113SL supports forward mode of bridging. In forward bridging mode, its PCI Express interface is connected to a root complex and its PCI bus interface is connected to PCI devices. PCI based systems and peripherals are ubiquitous in the I/O interconnect technology market today. It will be a tremendous effort to convert existing PCI based products to be used in PCI Express systems. PI7C9X113SL provides a solution to bridge existing PCI based products to the latest PCI Express technology. Page 19 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Figure 4-1 Forward Bridge Mode Host Processor System Memory Root Complex x1 link PI7C9X113SL PCI 32bit / 66MHz USB / 1394 Fibre Channel Fast Ethernet SCSI HDD Page 20 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 5 PCI EXPRESS FUNCTIONAL OVERVIEW 5.1 TLP STRUCTURE PCI Express TLP (Transaction Layer Packet) Structure is comprised of format, type, traffic class, attributes, TLP digest, TLP poison, and length of data payload. There are four TLP formats defined in PI7C9X113SL based on the states of FMT [1] and FMT [0] as shown on Table 5-1 . Table 5-1 TLP Format FMT [1] 0 0 1 1 FMT [0] 0 1 0 1 TLP Format 3 double word, without data 4 double word, without data 3 double word, with data 4 double word, with data Data payload of PI7C9X113SL can range from 4 (1DW) to 512 (128DW) bytes. PI7C9X113SL supports three TLP routing mechanisms. They are comprised of Address, ID, and Implicit routings. Address routing is being used for Memory and IO requests. ID based (bus, device, function numbers) routing is being used for configuration requests. Implicit routing is being used for message routing. There are two message groups (baseline and advanced switching). The baseline message group contains INTx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. The other is advanced switching support message group. The advanced switching support message contains data packet and signal packet messages. Advanced switching is beyond the scope of PI7C9X113SL implementation. The r [2:0] values of the "type" field will determine the destination of the message to be routed. All baseline messages must use the default traffic class zero (TC0). 5.2 VIRTUAL ISOCHRONOUS OPERATION This section provides a summary of Virtual Isochronous Operation supported by PI7C9X113SL. Virtual Isochronous support is disabled by default. Virtual Isochronous feature can be turned on with setting bit [26] of offset 40h to one. Control bits are designated for selecting which traffic class (TC1-7) to be used for upstream (PCI -to-PCI Express). PI7C9X113SL accepts only TC0 packets of configuration, IO, and message packets for downstream (PCI Express-to-PCI). If configuration, IO and message packets have traffic class other than TC0, PI7C9X113SL will treat them as malformed packets. PI7C9X113SL maps all downstream memory packets from PCI Express to PCI transactions regardless the virtual Isochronous operation is enabled or not. Page 21 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6 CONFIGURATION REGISTER ACCESS PI7C9X113SL supports Type-0 and Type-1 configuration space headers and Capability ID of 01h (PCI power management) to 10h (PCI Express capability structure). PI7C9X113SL supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of offset 02h). 6.1 CONFIGURATION REGISTER MAP PI7C9X113SL supports capability pointer with PCI power management (ID=01h), PCI bridge sub-system vendor ID (ID=0Dh), PCI Express (ID=10h), and message signaled interrupt (ID=05h). Table 6-1 Configuration Register Map (00h – FFh) Primary Bus Configuration Access or Secondary Bus Configuration Access 01h - 00h 03h – 02h 05h – 04h 07h – 06h 0Bh – 08h 0Ch 0Dh 0Eh 0Fh 17h – 10h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Fh – 1Eh 21h – 20h 23h – 22h 25h – 24h 27h – 26h 2Bh – 28h 2Dh – 2Ch PCI Configuration Register Name (type1) EEPROM (I2C) Access SM Bus Access Vendor ID Device ID Command Register Primary Status Register Class Code and Revision ID Cacheline Size Register Primary Latency Timer Header Type Register Reserved Reserved Primary Bus Number Register Secondary Bus Number Register Subordinate Bus Number Register Secondary Latency Timer I/O Base Register I/O Limit Register Secondary Status Register Memory Base Register Memory Limit Register Prefetchable Memory Base Register Prefetchable Memory Limit Register Prefetchable Memory Base Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Yes1 Yes1 Yes Yes Yes2 Yes2 Yes Yes Yes1 Yes2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Page 22 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Primary Bus Configuration Access or Secondary Bus Configuration Access 2Fh – 2Eh 31h – 30h 33h – 32h 34h 37h – 35h 3Bh – 38h 3Ch 3Dh 3Fh – 3Eh 41h – 40h 43h – 42h 47h – 44h 4Bh – 48h 4Fh – 4Ch 53h – 50h 57h – 54h 5Bh – 58h 5Fh – 5Ch 63h – 60h 67h – 64h 6Ah – 68h 6Bh 6Fh – 6Ch 73h – 70h 77h – 74h 7Bh – 78h 7Ch – 7Ch 83h – 80h 87h – 84h 8Bh – 88h 8Fh – 8Ch 93h – 90h 97h – 94h PCI Configuration Register Name (type1) EEPROM (I2C) Access SM Bus Access Prefetchable Memory Limit Upper 32-bit Register I/O Base Upper 16-bit Register I/O Limit Upper 16-bit Register Capability Pointer Reserved Reserved Interrupt Line Interrupt Pin Bridge Control PCI Data Prefetching Control Chip Control 0 Reserved Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - Yes - - - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Arbiter Mode, Enable, Priority Reserved Memory Readsmart Base Lower 32-Bit Register 1 Memory Readsmart Base Upper 32-Bit Register 1 Memory Readsmart Range Control Register 1 Memory Readsmart Memory Base Lower 32-Bit Register 2 Memory Readsmart Base Upper 32-Bit Register 2 Memory Readsmart Range Size Register 2 Reserved Upstream Memory Read/Write Control PHY TX/RX Control EEPROM (I2C) Control and Status Register Reserved GPIO Data and Control Reserved PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control and Status Page 23 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Primary Bus Configuration Access or Secondary Bus Configuration Access 98h PCI Configuration Register Name (type1) EEPROM (I2C) Access SM Bus Access Subtractive Decoding Yes Yes PCI-to-PCI Bridge Enable 9Bh – 99h Reserved 9Fh – 9Ch Reserved A3h – A0h Slot ID Capability Yes Yes A5h – A4h Secondary Clock and Yes Yes CLKRUN Control A6h XPIP Configuration Register 3 A7h Reserved Yes Yes A9h – A8h Subsystem ID and Yes Yes Subsystem Vendor ID Capability ABh – AAh Reserved AFh – ACh Subsystem ID and Yes Yes Subsystem Vendor ID B3h – B0h PCI Express Capability Yes Yes B7h – B4h Device Capability Yes Yes BBh – B8h Device Control and Yes Yes Status BFh – BCh Link Capability Yes Yes C3h – C0h Link Control and Yes Yes Status CBh – C4h Reserved CFh – CCh XPIP Configuration Yes Yes Register 0 D3h – D0h XPIP Configuration Yes Yes Register 1 D6h – D4h XPIP Configuration Yes Yes Register 2 D7h Reserved DBh – D8h VPD Capability Yes Yes Register DFh – DCh VPD Data Register Yes3 Yes E3h – E0h Extended Config Yes Yes Access Address E7h – E4h Extended Config Yes Yes Access Data EBh – E8h Reserved EFh – ECh Reserved F3h – F0h MSI Capability Yes Yes Register F7h – F4h Message Address Yes Yes FBh – F8h Message Upper Yes Yes Address FFh – FCh Message Data Yes Yes Note 1: When masquerade is enabled, it is pre-loadable. Note 2: Read access only. Note 3: The VPD data is read/write through I2C during VPD operation. 6.2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP PI7C9X113SL also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space. The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting (ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h). Page 24 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge When Subtractive Decoding PCI-to-PCI bridge is enabled, the PCI-X/PCIe capability is not included in the Capability List and all PCI-X/PCIe capability registers and Extended Configuration registers are treated as reserved registers. Table 6-2 PCI Express Extended Capability Register Map (100h – FFFh) Primary Bus Configuration Access or Secondary Bus Configuration Access 103h – 100h 107h – 104h 10Bh – 108h 10Fh – 10Ch 113h – 110h 117h – 114h 11Bh – 118h 12Bh – 11Ch 12Fh – 12Ch 133h – 130h 137h – 134h 13Bh – 138h 14Bh – 13Ch 14Fh – 14Ch 153h – 150h 157h – 154h 15Bh – 158h 15Fh – 15Ch 163h – 160h 167h – 164h 16Bh – 168h 2FFh – 16Ch 303h – 300h 307h – 304h 30Fh – 308h 310h FFFh – 314h Note 5: Read access only. Transparent Mode (type1) EEPROM (I2C) Access SM Bus Access Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask AER Capabilities and Control Header Log Registers Secondary Uncorrectable Error Status Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary AER Capability and Control Secondary Header Log Register Reserved VC Capability Port VC Capability 1 Port VC Capability 2 Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Reserved Extended GPIO Data and Control Extended GPI/GPO Data and Control Reserved Replay and Acknowledge Latency Timer Reserved Yes Yes2 No Yes Yes Yes No No Yes Yes No Yes No Yes No No Yes Yes No Yes No Yes No Yes No Yes No No No No No Yes Yes Yes Yes Yes No Yes No No No No Yes Yes No Yes No Yes No Yes No Yes No No Page 25 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3 PCI CONFIGURATION REGISTERS The following section describes the configuration space when the device is in transparent mode. The descriptions for different register type are listed as follow: Register Type RO ROS RW RWC RWS RWCS 6.3.1 VENDOR ID – OFFSET 00h BIT 15:0 6.3.2 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. Returns 12D8h when read. TYPE RO DESCRIPTION Identifies this device as the PI7C9X113SL. Returns E113 when read. DEVICE ID – OFFSET 00h BIT 31:16 6.3.3 Descriptions Read Only Read Only and Sticky Read/Write Read/Write “1” to clear Read/Write and Sticky Read/Write “1” to clear and Sticky FUNCTION Device ID COMMAND REGISTER – OFFSET 04h BIT 0 FUNCTION I/O Space Enable TYPE RW 1 Memory Space Enable RW 2 Bus Master Enable RW 3 Special Cycle Enable RO 4 Memory Write and Invalidate Enable RO 5 VGA Palette Snoop Enable RO 6 Parity Error Response Enable RW 7 Wait Cycle Control RO DESCRIPTION 0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. Reset to 0 0: PI7C9X113SL does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X113SL does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). Reset to 0 VGA Palette Snoop Enable is not supported. Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait Cycle Control is not supported. Page 26 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.4 BIT FUNCTION TYPE 8 SERR_L Enable Bit RW 9 Fast Back-to-Back Enable RO 10 Interrupt Disable RW 15:11 Reserved RO DESCRIPTION Reset to 0 0: Disable 1: Enable PI7C9X113SL in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Reset to 0 Fast Back-to-back Enable is not supported Reset to 0 0: INTA_L can be asserted on PCI interface 1: Prevent INTA_L from being asserted on PCI interface Reset to 0 Reset to 00000 PRIMARY STATUS REGISTER – OFFSET 04h BIT 19:16 20 FUNCTION Reserved Capability List Capable TYPE RO RO 21 66MHz Capable RO Reset to 1 1: 66MHz capable 22 23 Reserved Fast Back-to-Back Capable RO RO Reset to 0 Reset to 0 1: Enable fast back-to-back transactions 24 Master Data Parity Error Detected RWC DESCRIPTION Reset to 0000 0: PI7C9X113SL does not support the capability list 1: PI7C9X113SL supports the capability list (offset 34h in the pointer to the data structure) Reset to 0 This bit is set if its Parity Error Enable bit is set and either of the conditions occurs on the primary:   RO Receives a completion marked poisoned Poisons a write request Reset to 0 DEVSEL_L Timing is not supported. 26:25 DEVSEL_L Timing (medium decode) 27 Signaled Target Abort RWC Reset to 00 This bit is set when PI7C9X113SL completes a request using completer abort status on the primary 28 Received Target Abort RWC Reset to 0 This bit is set when PI7C9X113SL receives a completion with completer abort completion status on the primary 29 Received Master Abort RWC Reset to 0 This bit is set when PI7C9X113SL receives a completion with Unsupported Request Completion Status on the primary 30 Signaled System Error RWC Reset to 0 This bit is set when PI7C9X113SL sends an ERR_FATAL or ERR_NON_FATAL message on the primary 31 Detected Parity Error RWC Reset to 0 This bit is set when poisoned TLP is detected on the primary Reset to 0 Page 27 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.5 REVISION ID REGISTER – OFFSET 08h BIT 7:0 6.3.6 FUNCTION Revision ID TYPE RO DESCRIPTION Reset to 00000000h CLASS CODE REGISTER – OFFSET 08h BIT 15:8 23:16 FUNCTION Programming Interface Sub-Class Code TYPE RO RO DESCRIPTION 00000000: Subtractive decoding of PCI-PCI bridge is not supported 00000001: Subtractive decoding of PCI-PCI bridge is supported RO as 00000000 when legacy bit (bit 0 of offset 98h) is clear, and 00000001 when legacy bit is set. Sub-Class Code 00000100: PCI-to-PCI bridge 31:24 Base Class Code RO Reset to 00000100 Base class code 00000110: Bridge Device Reset to 00000110 6.3.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch BIT 1:0 FUNCTION Reserved TYPE RO DESCRIPTION Bit [1:0] not supported 2 Cache Line Size RW Reset to 00 1: Cache line size = 4 double words 3 Cache Line Size RW Reset to 0 1: Cache line size = 8 double words 4 Cache Line Size RW Reset to 0 1: Cache line size = 16 double words 5 Cache Line Size RW Reset to 0 1: Cache line size = 32 double words 7:6 Reserved RO Reset to 0 Bit [7:6] not supported Reset to 00 6.3.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch BIT 15:8 FUNCTION Primary Latency Timer TYPE RO DESCRIPTION 8 bits of primary latency timer in PCI bus Reset to 00h 6.3.9 HEADER TYPE REGISTER – OFFSET 0Ch BIT 22:16 FUNCTION PCI-to-PCI Bridge Configuration TYPE RO DESCRIPTION PCI-to-PCI bridge configuration (10 – 3Fh) Page 28 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT FUNCTION TYPE 23 Single Function Device RO 31:24 BIST RO DESCRIPTION Reset to 0000001 0: Indicates single function device 1: Indicates multiple function device Reset to 0 Reset to 00h 6.3.10 RESERVED REGISTERS – OFFSET 10h TO 17h 6.3.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h BIT 7:0 FUNCTION Primary Bus Number TYPE RW DESCRIPTION Reset to 00h 6.3.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h BIT 15:8 FUNCTION Secondary Bus Number TYPE RW DESCRIPTION Reset to 00h 6.3.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h BIT 23:16 FUNCTION Subordinate Bus Number TYPE RW DESCRIPTION Reset to 00h 6.3.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h BIT 31:24 FUNCTION Secondary Latency Timer TYPE RW DESCRIPTION Reset to 40h 6.3.15 I/O BASE REGISTER – OFFSET 1Ch BIT 1:0 FUNCTION 32-bit I/O Addressing Support 3:2 7:4 Reserved I/O Base TYPE RO DESCRIPTION 01: Indicates PI7C9X113SL supports 32-bit I/O addressing Reset to 01 Reset to 00 Indicates the I/O base (0000_0000h) RO RW Reset to 0000 6.3.16 I/O LIMIT REGISTER – OFFSET 1Ch BIT 9:8 FUNCTION 32-bit I/O Addressing Support 11:10 15:12 Reserved I/O Limit TYPE RO RO RW DESCRIPTION 01: Indicates PI7C9X113SL supports 32-bit I/O addressing Reset to 01 Reset to 00 Indicates the I/O Limit (0000_0FFFh) Reset to 0000 6.3.17 SECONDARY STATUS REGISTER – OFFSET 1Ch BIT FUNCTION TYPE DESCRIPTION Page 29 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 20:16 21 FUNCTION Reserved 66MHz Capable TYPE RO RO DESCRIPTION Reset to 00000 Indicates PI7C9X113SL is 66MHz capable Reset to 1 22 23 Reserved Fast Back-to-Back Capable 24 Master Data Parity Error Detected RO RO RWC Reset to 0 1: Indicates PI7C9X113SL supports Fast Back-to-Back Capable Reset to 1 This bit is set if its parity error enable bit is set and either of the conditions occur on the primary:    RO Detected parity error when receiving data or split response for read Observes S_PERR_L asserted when sending data or receiving split response for write Receives a split completion message indicating data parity error occurred for non-posted write Reset to 0 01: medium DEVSEL_L decoding 26:25 DEVSEL_L Timing (medium decoding) 27 Signaled Target Abort RWC Reset to 01 This bit is set when PI7C9X113SL signals target abort on the secondary interface. 28 Received Target Abort RWC Reset to 0 This bit is set when PI7C9X113SL detects target abort on the secondary interface. 29 Received Master Abort RWC Reset to 0 This bit is set when PI7C9X113SL detects master abort on the secondary interface. 30 Received System Error RWC Reset to 0 This bit is set when PI7C9X113SL detects SERR_L assertion on the secondary interface. 31 Detected Parity Error RWC Reset to 0 This bit is set when PI7C9X113SL detects address or data parity error on the secondary interface. Reset to 0 6.3.18 MEMORY BASE REGISTER – OFFSET 20h BIT 3:0 15:4 FUNCTION Reserved Memory Base TYPE RO RW DESCRIPTION Reset to 0000 Memory Base (00000000h) Reset to 000h 6.3.19 MEMORY LIMIT REGISTER – OFFSET 20h BIT 19:16 31:20 FUNCTION Reserved Memory Limit TYPE RO RW DESCRIPTION Reset to 0000 Memory Limit (000FFFFFh) Reset to 000h Page 30 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.20 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h BIT 3:0 FUNCTION 64-bit Addressing Support TYPE RO 15:4 Prefetchable Memory Base RW DESCRIPTION 0001: Indicates PI7C9X113SL supports 64-bit addressing Reset to 0001 Prefetchable Memory Base (00000000h) Reset to 000h 6.3.21 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h BIT 19:16 FUNCTION 64-bit Addressing Support TYPE RO 31:20 Prefetchable Memory Limit RW DESCRIPTION 0001: Indicates PI7C9X113SL supports 64-bit addressing Reset to 0001 Prefetchable Memory Limit (000FFFFFh) Reset to 000h 6.3.22 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h BIT 31:0 FUNCTION Prefetchable Base Upper 32bit TYPE RW DESCRIPTION Bit [63:32] of prefetchable base Reset to 00000000h 6.3.23 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch BIT 31:0 FUNCTION Prefetchable Limit Upper 32-bit TYPE RW DESCRIPTION Bit [63:32] of prefetchable limit Reset to 00000000h 6.3.24 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h BIT 15:0 FUNCTION I/O Base Upper 16-bit TYPE RW DESCRIPTION Bit [31:16] of I/O Base Reset to 0000h 6.3.25 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h BIT 31:16 FUNCTION I/O Limit Upper 16-bit TYPE RW DESCRIPTION Bit [31:16] of I/O Limit Reset to 0000h 6.3.26 CAPABILITY POINTER – OFFSET 34h BIT 7:0 FUNCTION Capability Pointer 31:8 Reserved TYPE RO RO DESCRIPTION Capability pointer Reset to 80h (RO as 90h in Legacy Mode to by pass PCI-X capability) Reset to 0 Page 31 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.27 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h BIT 31:0 FUNCTION Expansion ROM Base Address TYPE RO DESCRIPTION Expansion ROM is not supported. Reset to 00000000h 6.3.28 INTERRUPT LINE REGISTER – OFFSET 3Ch BIT 7:0 FUNCTION Interrupt Line TYPE RW DESCRIPTION For initialization code to program to tell which input of the interrupt controller the PI7C9X113SL’s INTA_L in connected to. Reset to 00h 6.3.29 INTERRUPT PIN REGISTER – OFFSET 3Ch BIT 15:8 FUNCTION Interrupt Pin TYPE RO DESCRIPTION Designates interrupt pin, INTA_L, is used Reset to 01h 6.3.30 BRIDGE CONTROL REGISTER – OFFSET 3Ch BIT 16 FUNCTION Parity Error Response Enable TYPE RW DESCRIPTION 0: Ignore parity errors on the secondary 1: Enable parity error detection on secondary Controls the response to uncorrectable address attribute and data errors on the secondary 17 SERR_L Enable RW 18 ISA Enable RW 19 VGA Enable RW 20 VGA 16-bit Decode RW Reset to 0 0: Disable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL 1: Enable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL Reset to 0 0: Forward downstream all I/O addresses in the address range defined by the I/O Base and Limit registers 1: Forward upstream all I/O addresses in the address range defined by the I/O Base and Limit registers that are in the first 64KB of PCI I/O address space (top 768 bytes of each 1KB block) Reset to 0 0: Do not forward VGA compatible memory and I/O addresses from the primary to secondary, unless they are enabled for forwarding by the defined I/O and memory address ranges 1: Forward VGA compatible memory and I/O addresses from the primary and secondary (if the I/O enable and memory enable bits are set), independent of the ISA enable bit Reset to 0 0: Execute 10-bit address decodes on VGA I/O accesses 1: Execute 16-bit address decode on VGA I/O accesses Reset to 0 Page 32 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 21 FUNCTION Master Abort Mode TYPE RW 22 Secondary Interface Reset RW 23 Fast Back-to-Back Enable RO 24 Primary Master Timeout RW DESCRIPTION 0: Do not report master aborts (return FFFFFFFFh on reads and discards data on write) 1: Report master abort by signaling target abort if possible or by the assertion of SERR_L (if enabled). Reset to 0 0: Do not force the assertion of RESET_L on secondary PCI bus 1: Force the assertion of RESET_L on secondary PCI bus Reset to 0 Fast back-to-back is not supported Reset to 0 0: Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles This bit is ignored by the PI7C9X113SL 25 Secondary Master Timeout RW 26 Master Timeout Status RWC 27 Discard Timer SERR_L Enable RW 31:28 Reserved RO Reset to 0 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles Reset to 0 This bit is set when the discard timer expires and a delayed completion is discarded at the PCI interface Reset to 0 This bit is set to enable to generate ERR_NONFATAL or ERR_FATAL as a result of the expiration of the discard timer on the PCI interface. Reset to 0 Reset to 0000 6.3.31 PCI DATA PREFETCHING CONTROL REGISTER – OFFSET 40h BIT 0 FUNCTION Secondary Internal Arbiter’s PARK Function TYPE RW DESCRIPTION 0: Park to the last master 1: Park to PI7C9X113SL secondary port 1 Memory Read Prefetching Dynamic Control Disable RW Reset to 0 0: Enable memory read prefetching dynamic control for PCI to PCIe read 1: Disable memory read prefetching dynamic control for PCI to PCIe read 2 Completion Data Prediction Control Disable RW Reset to 0 0: Enable completion data prediction for PCI to PCIe read. 1: Disable completion data prediction 3 CFG Type0-to-Type1 Conversion Enable RW Reset to 0 0: CFG Type0-to-Type1 conversion is disabled. 1: CFG Type0-to-Type1 conversion is enabled if the AD[31:28] is all 1s. PI7C9X113SL will ignore the AD[0] and always treats the cfg transaction as type 1, other AD bit (except AD[31:28], AD[0]) must meet the Type 1 format Reset to 0 Page 33 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 5:4 FUNCTION PCI Read Multiple Prefetch Mode TYPE RW DESCRIPTION 00: One cache line prefetch if memory read multiple address is in prefetchable range at the PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface, and the PI7C9X113SL will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X113SL will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X113SL, until the discard time expires 7:6 PCI Read Line Prefetch Mode RW Reset to 10 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X113SL will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X113SL will keep remaining data after the read line is terminated either by an external master or by the PI7C9X113SL, until the discard timer expires 9:8 PCI Read Prefetch Mode RW Reset to 00 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI interface 11: Disconnect on the first DWORD 10 PCI Special Delayed Read Mode Enable RW Reset to 00 0: Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X113SL will complete the memory read transaction and return data back to the master if the address and byte enables are the same. 11 Optional Malformed Packet checking Enable RW Reset to 0 0: Optional Malformed Packet checking is disabled 1: Optional Malformed Packet checking is enabled Reset to 0 Page 34 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 14:12 FUNCTION Maximum Memory Read Byte Count TYPE RW DESCRIPTION Maximum byte count is used by the PI7C9X113SL when generating memory read requests on the PCIe link in response to a memory read initiated on the PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to “full prefetch”. 000: 001: 010: 011: 100: 101: 110: 111: 512 bytes (default) 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes 4096 bytes 512 bytes Reset to 000 6.3.32 CHIP CONTROL 0 REGISTER – OFFSET 40h BIT 15 FUNCTION Flow Control Update Control TYPE RW 16 PCI Retry Counter Status RWC 18:17 PCI Retry Counter Control RW 19 PCI Discard Timer Disable RW DESCRIPTION 0: Flow control is updated for every two credits available 1: Flow control is updated for every on credit available Reset to 0 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 0: Enable the PCI discard timer in conjunction with bit [24] or bit [25] of offset 3Ch (bridge control register) 1: Disable the PCI discard timer in conjunction with bit [24] or bit [25] of offset 3Ch (bridge control register) 20 PCI Discard Timer Short Duration RW Reset to 0 0: Use bit [25] offset 3Ch to indicate how many PCI clocks should be allowed before the PCI discard timer expires 1: 64 PCI clocks allowed before the PCI discard timer expires 22:21 Configuration Request Retry Timer Counter Value Control RW 23 Delayed Transaction Order Control RW 25:24 Completion Timer Counter Value Control RW Reset to 0 00: Timer expires at 25us 01: Timer expires at 0.5ms 10: Timer expires at 5ms 11: Timer expires at 25ms Reset to 01 0: Enable out-of-order capability between delayed transactions 1: Disable out-of-order capability between delayed transactions Reset to 0 00: Timer expires at 50us 01: Timer expires at 10ms 10: Timer expires at 50ms 11: Timer disabled Reset to 01 Page 35 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 26 FUNCTION Isochronous Traffic Support Enable TYPE RW DESCRIPTION 0: All memory transactions from PCI to PCIe will be mapped to TC0 1: All memory transactions from PCI to PCIe will be mapped to Traffic Class defined in bit [29:27] of offset 40h. 29:27 30 31 Traffic Class Used For Isochronous Traffic Power Saving Mode Enable Power Saving Mode Enable at ASPM L0s Reset to 0 Reset to 001 RW RW 0: Disable the power saving mode; 1: Enable the power saving mode. The internal clock for MAC/DLL/TLP and PCI logic is disabled at L1s and L1 state. Reset to 1 0: Disables the power saving mode at ASPM L0s 1: Enables the power saving mode at ASPM L0s RW Reset to 1 6.3.33 RESERVED REGISTER – OFFSET 44h BIT 31:0 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 00000000h 6.3.34 ARBITER ENABLE REGISTER – OFFSET 48h BIT 0 FUNCTION Enable Arbiter 0 TYPE RW DESCRIPTION 0: Disable arbitration for internal PI7C9X113SL request 1: Enable arbitration for internal PI7C9X113SL request 1 Enable Arbiter 1 RW Reset to 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 2 Enable Arbiter 2 RW Reset to 1 0: Disable arbitration for master 2 1: Enable arbitration for master 2 3 Enable Arbiter 3 RW Reset to 1 0: Disable arbitration for master 3 1: Enable arbitration for master 3 4 Enable Arbiter 4 RW Reset to 1 0: Disable arbitration for master 4 1: Enable arbitration for master 4 8:5 Reserved RO Reset to 1 Reset to 0h 6.3.35 ARBITER MODE REGISTER – OFFSET 48h BIT 9 FUNCTION External Arbiter Bit TYPE RW DESCRIPTION 0: Enable internal arbiter 1: Use external arbiter and disable internal arbiter Reset to 0 Page 36 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 10 FUNCTION Broken Master Timeout Enable TYPE RW DESCRIPTION 0: Broken master timeout disable 1: This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME_L to become active when a device’s PCI bus GNT is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT for the device is de-asserted. 11 Broken Master Refresh Enable RW Reset to 0 0: A broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served once 19:12 Arbiter Fairness Counter RW 20 GNT_L Output Toggling Enable RW Reset to 0 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device’s PCI bus GNT active after detecting a PCI bus REQ_L from another device. The counter is reloaded whenever a new PCI bus GNT is asserted. For every new PCI bus GNT, the counter is armed to decrement when it detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device’s PCI bus GNT until the device has deasserted its PCI bus REQ. Reset to 08h 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L 21 Reserved RO Reset to 0 Reset to 0 6.3.36 ARBITER PRIORITY REGISTER – OFFSET 48h BIT 22 FUNCTION Arbiter Priority 0 TYPE RW DESCRIPTION 0: Low priority request to internal PI7C9X113SL 1: High priority request to internal PI7C9X113SL 23 Arbiter Priority 1 RW Reset to 1 0: Low priority request to master 1 1: High priority request to master 1 24 Arbiter Priority 2 RW Reset to 0 0: Low priority request to master 2 1: High priority request to master 2 25 Arbiter Priority 3 RW Reset to 0 0: Low priority request to master 3 1: High priority request to master 3 26 Arbiter Priority 4 RW Reset to 0 0: Low priority request to master 4 1: High priority request to master 4 31:27 Reserved RO Reset to 0 Reset to 00h 6.3.37 RESERVED REGISTERS – OFFSET 4Ch Page 37 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.38 MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h BIT 31:0 FUNCTION Memory Readsmart Base Lower 32-bit Register 1 TYPE RW DESCRIPTION Memory Readsmart Base Address 1 in conjunction with Memory Readsmart Base Lower 32-bit register 1 and Memory Readsmart Range Size register 1, defines address range 1 in which PCI memory read are allowed (or not allowed) to use the Readsmart mode which is controlled by bit [7:4] of 40h. Reset to 00000000h 6.3.39 MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h BIT 31:0 FUNCTION Memory Readsmart Base Upper 32-bit register 1 TYPE RW DESCRIPTION Bit[63:32] of Memory Readsmart Base Address 1 Reset to 00000000h 6.3.40 MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h BIT 0 FUNCTION Memory Readsmart Range Control TYPE RW 31:1 Memory Readsmart Range Address 1 RW DESCRIPTION Memory Readsmart Range Control register 0: any PCI memory read with address falling in the range are not allowed to use Readsmart mode. 1: only PCI memory read with address falling in the range are allowed to use Readsmart mode. Reset to 0 Define the size of the range 1, maximum 4G byte with granuity of 2 bytes Reset to 00000000h 6.3.41 MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch BIT 31:0 FUNCTION Readsmart Memory Base Lower 32-bit Register 2 TYPE RW DESCRIPTION Memory Readsmart Base Address 1 in conjunction with Memory Readsmart Base Lower 32-bit register 2 and Memory Readsmart Range Size register 2, defines address range 1 in which PCI memory read are allowed (or not allowed) to use the Readsmart mode which is controlled by bit [7:4] of 40h. Reset to 00000000h 6.3.42 MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h BIT 31:0 FUNCTION Memory Readsmart Base Upper 32-bit register 2 TYPE RW DESCRIPTION Bit[63:32] of Memory Readsmart Base Address 2 Reset to 00000000h 6.3.43 MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h BIT 31:0 FUNCTION Memory Readsmart Range Size register 2 TYPE RW DESCRIPTION Memory Readsmart Range Address 2 defines the size of the range 2, maximum 4G byte Page 38 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT FUNCTION TYPE DESCRIPTION Reset to 00000000h 6.3.44 UPSTREAM MEMORY READ/WRITE CONTROL REGISTER – OFFSET 68h BIT 26:0 29:27 FUNCTION Reserved Upstream Memory Read Request Transmitting Control TYPE RO RW DESCRIPTION Reset to 0 Control when to transmit a second memory read request to PCIe link before receiving Completion data for the previous request which is from the same read channel. 000: Do not send 2nd request until receiving all completion data for the previous request. 001: Do not send 2nd request until 1 ADQ data left unrecived for the previous request. 010: Do not send 2nd request until 2 ADQ data left unrecived for the previous request. 011: Do not send 2nd request until 4 ADQ data left unrecived for the previous request. 1xx: Do not send 2nd request until 8 ADQ data left unrecived for the previous request. 31:30 Memory Write Fragment Control RW Reset to 7h Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragment at 128-byte boundary Reset to 10 6.3.45 PHY TRANSMIT/RECEIVE CONTROL REGISTER – OFFSET 6Ch BIT 2:0 FUNCTION Timing Threshold TYPE RW DESCRIPTION Timing threshold before sampling receiver detection circuit 000: 001: 010: 011: 100: 101: 110: 111: 1.0us 2.0us 4.0us(default) 5.0us 10.0us 20.0us 40.0us 50.0us Reset to 2h xxx1: Enable stage 0 xx1x: Enable stage 1 x1xx: Enable stage 2 6:3 Receiver Equalization Stage Enable (2.5G) RW 7 Clock and Data Recovery (CDR) Second Order Loop Enable Set CDR Second Order Loop Gain Receiver Signal Detect Level Select Threshold Of Clock Recovery Filter RW Reset to 2h Reset to 0 RW Reset to 2h RW Reset to 1h RW Reset to 3h 9:8 11:10 13:12 Page 39 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 14 15 16 17 22:18 27:23 30:28 31 FUNCTION De-Emphasis Offset Drive Level to the Lane Driver in Transmit Margin Mode Enable De-Emphasis Offset Drive Level to the Lane Driver in Normal Mode Enable Base Offset Drive Level to the Lane Driver in Normal Mode Enable Base Offset Drive Level to the Lane Driver in Transmit Margin Mode Enable De-Emphasis -3.5db of Transmit De-Emphasis Base De-Emphasis -3.5db of Transmit Level Base Transmitter Main Output Voltage Drive Level Reserved TYPE RW DESCRIPTION Reset to 0 RW Reset to 0 RW Reset to 0 RW Reset to 0 RW Reset to 0Dh RW Reset to 13h RW Set Transmitter main output voltage drive levels based on Drive Margin setting: 000 : Nominal 001 : Margin 1 case 010 : Margin 2 case 011 : Margin 3 case 100 : Margin 4 case Other : Reserved RO Reset to 0h Reset to 0 6.3.46 EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h BIT 0 FUNCTION Initiate EEPROM Read or Write Cycle TYPE RW DESCRIPTION This bit will be reset to 0 after the EEPROM operation is finished. 0: EEPROM AUTOLOAD disabled 0 -> 1: Starts the EEPROM Read or Write cycle 1 Control Command for EEPROM RW Reset to 0 0: Read 1: Write 2 EEPROM Error RO Reset to 0 0: EEPROM acknowledge is always received during the EEPROM cycle 1: EEPROM acknowledge is not received during EEPROM cycle 3 EPROM Autoload Complete Status RO Reset to 0 0: EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed 5:4 EEPROM Clock Frequency Control RW Reset to 0 Where PCLK is 256MHz 00: PCLK / 8192 01: PCLK / 4096 10: PCLK / 2048 11: PCLK / 256 6 EEPROM Autoload Control RW Reset to 00 0: Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0 Page 40 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 7 FUNCTION Fast EEPROM Autoload Control TYPE RW 8 EEPROM Autoload Status RO 15:9 EEPROM Word Address RW 31:16 EEPROM Data RW DESCRIPTION =0: normal speed of EEPROM autoload =1: speeds up EEPROM autoload by 8 times Reset to 1 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 EEPROM word address for EEPROM cycle Reset to 0000000 EEPROM data to be written into the EEPROM or received from the EEPROM after read cycle has completed Reset to 0000h Page 41 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.47 RESERVED REGISTER – OFFSET 74h 6.3.48 GPIO DATA AND CONTROL REGISTER – OFFSET 78h BIT 11:0 15:12 19:16 23:20 27:24 31:28 FUNCTION Reserved GPIO Output Write-1-toClear GPIO Output Write-1-to-Set GPIO Output Enable Write1-to-Clear GPIO Output Enable Write1-to-Set GPIO Input Data Register TYPE RO RW DESCRIPTION Reset to 000h Reset to 0h RW RW Reset to 0h Reset to 0h RW Reset to 0h RO Reset to 0h 6.3.49 RESERVED REGISTER – OFFSET 7Ch 6.3.50 PCI-X CAPABILITY ID REGISTER – OFFSET 80h BIT 7:0 FUNCTION PCI-X Capability ID TYPE RO DESCRIPTION PCI-X Capability ID Reset to 07h 6.3.51 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h BIT 15:8 FUNCTION Next Capability Pointer TYPE RO DESCRIPTION Point to power management Reset to 90h 6.3.52 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h BIT 16 FUNCTION 64-bit Device on Secondary Bus Interface TYPE RO 17 133MHz Capable RO Reset to 0 133MHz capable on secondary interface. 18 Split Completion Discarded RO Reset to 0 Split Completion Discarded 19 Unexpected Split Completion 20 21 Split Completion Overrun Split Request Delayed RWC RO RO DESCRIPTION 64-bit is not supported Reset to 0 0: No unexpected split completion has been received. 1: An unexpected split completion has been received with the request ID equaled to the bridge's secondary port number, device number 00h, and function number 0 on the bridge secondary interface. Reset to 0 Reset to 0 0: The bridge has not delayed a split request. 1: The bridge has delayed a split request because the bridge cannot forward a transaction to secondary port due to not enough room within the limit specified in the split transaction commitment limit field in the downstream split transaction control register. Reset to 0 Page 42 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 24:22 FUNCTION Secondary Clock Frequency 31:25 Reserved TYPE RO RO DESCRIPTION 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7.5ns) 011: Reserved 1xx: Reserved Reset to 000 Reset to 0000000 6.3.53 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h BIT 2:0 FUNCTION Function Number TYPE RO 7:3 Device Number RO 15:8 Bus Number RO 16 64-bit Device on Primary Bus Interface RO Reset to 11111111 64-bit device. 17 133MHz Capable RO Reset to 0 133MHz capable on primary interface. 18 19 Split Completion Discarded Unexpected Split Completion RO RWC 20 21 Split Completion Overrun Split Request Delayed RO RWC 31:22 Reserved RO DESCRIPTION Function Number; the function number (AD[10:8] of a type-0 configuration transaction) to which the bridge responds. Reset to 000 Device Number; the device number (AD[15:11] of a type-0 configuration transaction) is assigned to the bridge by the connection of system hardware. Each time the bridge is addressed by a configuration write transaction, the bridge updates this register with the contents of AD[15:11] of the address phase of the configuration transaction, regardless of which register in the bridge is addressed by the transaction. The bridge is addressed by a configuration write transaction if all of the following are true:  The transaction uses a configuration write command.  IDSEL is asserted during the address phase.  AD[1:0] are 00 (type-0 configuration transaction).  AD[10:8] of the configuration address contain the appropriate function number. Reset to 11111 Bus Number; It is an additional address from which the contents of the primary bus number register on type-1 configuration space header is read. The bridge uses the bus number, device number, and function number fields to create the completer ID when responding with a split completion to a read of an internal bridge register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCIX mode. Reset to 0 Reset to 0 0: No unexpected split completion has been received. 1: An unexpected split completion has been received with the request ID equaled to the bridge's primary port number, device number, and function number on the bridge primary interface. Reset to 0 Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X113SL is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 Reset to 0000000000 Page 43 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.54 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h BIT 15:0 FUNCTION Upstream Split Transaction Capability TYPE RO 31:16 Upstream Split Transaction Commitment Limit RW DESCRIPTION Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Upstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X113SL is allowed to forward all split requests of any size regardless of the amount of buffer space available. If the limit is set to 0100h or greater will cause the bridge to forward accepted split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h 6.3.55 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch BIT 15:0 FUNCTION Downstream Split Transaction Capability 31:16 Downstream Split Transaction Commitment Limit TYPE RO RW DESCRIPTION Downstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the primary bus in addressing the completers on the secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X113SL is allowed to forward all split requests of any size regardless of the amount of buffer space available. If the limit is set to 0100h or greater will cause the bridge to forward accepted split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h 6.3.56 POWER MANAGEMENT ID REGISTER – OFFSET 90h BIT 7:0 FUNCTION Power Management ID TYPE RO DESCRIPTION Power Management ID Register Reset to 01h 6.3.57 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h 6.3.58 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h Page 44 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 18:16 FUNCTION Version Number TYPE RO DESCRIPTION Version number that complies with revision 1.2 of the PCI Power Management Interface specification. 19 PME Clock RO 20 21 Reserved Device Specific Initialization (DSI) RO RO 24:22 AUX Current RO 25 D1 Power Management RO Reset to 001 D1 power management is not supported 26 D2 Power Management RO Reset to 0 D2 power management is not supported 31:27 PME_L Support RO Reset to 0 PME_L is supported in D3 cold, D3 hot, and D0 states. Reset to 011 PME clock is not required for PME_L generation Reset to 0 Reset to 0 DSI – no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state Reset to 0 000: 0mA 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset to 11001 6.3.59 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h BIT 1:0 FUNCTION Power State TYPE RW DESCRIPTION Power State is used to determine the current power state of PI7C9X113SL. If a non-implemented state is written to this register, PI7C9X113SL will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset without activating the RESET_L of PCI bus interface 00: D0 state 01: D1 state not implemented 10: D2 state not implemented 11: D3 state 2 3 Reserved No Soft Reset RO RO 7:4 8 Reserved PME Enable RO RWS 12:9 Data Select RO Reset to 00 Reset to 0 0: Internal reset occurs at D3hot->D0 1: No internal reset occurs and configuration registers are preserved at D3hot->D0 Reset to 1 Reset to 0h 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset to 0 Data register is not implemented Reset to 0000 Page 45 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 14:13 FUNCTION Data Scale TYPE RO DESCRIPTION Data register is not implemented 15 PME Status RWCS Reset to 00 PME_L is supported Reset to 0 6.3.60 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h BIT 21:16 22 FUNCTION Reserved B2/B3 Support TYPE RO RO DESCRIPTION Reset to 000000 0: B2 / B3 is not support for D3hot 23 PCI Bus Power/Clock Control Enable RO Reset to 0 0: PCI Bus Power/Clock is disabled 31:24 Data Register RO Reset to 0 Data register is not implemented Reset to 00h 6.3.61 SUBTRACTIVE DECODING PCI-TO-PCI BRIDGE ENABLE – OFFSET 98h BIT 0 FUNCTION Subtractive Decoding PCIto-PCI Bridge Enable TYPE RW 1 PCI Bus Subtractive Decoding Enable RW 31:3 Reserved RO DESCRIPTION 0: 1: PI7C9X113SL’s class code is 060401h, and the bridge forwards all cycles (Memory/IO) to downstream PCI devices. All PCI-X/PCIe Capability registers and Extended Configuration registers are treated as reserved registers: Write access is completed normally but data is discarded. Read accesses is returned with data value of 0. Reset to 0 0: PI7C9X113SL does not perform Subtractive Decoding at PCI Bus 1: PI7C9X113SL performs Subtractive Decoding at PCI Bus Reset to 0 Reset to 0 6.3.62 RESERVED REGISTERS – OFFSET 9Ch 6.3.63 CAPABILITY ID REGISTER – OFFSET A0h BIT 7:0 FUNCTION Capability ID TYPE RO DESCRIPTION Capability ID for Slot Identification. SI is off by default but can be turned on through EEPROM interface Reset to 04h 6.3.64 NEXT POINTER REGISTER – OFFSET A0h BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer – points to PCI Express capabilities register Reset to B0h Page 46 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.65 SLOT NUMBER REGISTER – OFFSET A0h BIT 20:16 FUNCTION Expansion Slot Number TYPE RW DESCRIPTION Expansion slot number 21 First In Chassis RW Reset to 00000 First in chassis 23:22 Reserved RO Reset to 0 Reset to 00 6.3.66 CHASSIS NUMBER REGISTER – OFFSET A0h BIT 31:24 FUNCTION Chassis Number TYPE RW DESCRIPTION Chassis number Reset to 00h 6.3.67 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h BIT 1:0 FUNCTION S_CLKOUT0 Enable TYPE RW DESCRIPTION S_CLKOUT0 should be always enabled in order to feed the internal secondary interface logic, unless there is external clock input feeding to the pin. 00: enable S_CLKOUT0 01: enable S_CLKOUT0 10: enable S_CLKOUT0 11: disable S_CLKOUT0 and driven LOW 3:2 S_CLKOUT1 Enable RW Reset to 00 S_CLKOUT (Slot 1) Enable 00: enable S_CLKOUT1 01: enable S_CLKOUT1 10: enable S_CLKOUT1 11: disable S_CLKOUT1 and driven LOW 5:4 S_CLKOUT2 Enable RW Reset to 00 S_CLKOUT (Slot 2) Enable 00: enable S_CLKOUT2 01: enable S_CLKOUT2 10: enable S_CLKOUT2 11: disable S_CLKOUT2 and driven LOW 7:6 S_CLKOUT3 Enable RW Reset to 00 S_CLKOUT (Slot 3) Enable 00: enable S_CLKOUT3 01: enable S_CLKOUT3 10: enable S_CLKOUT3 11: disable S_CLKOUT3 and driven LOW 12:8 Reserved RO Reset to 00 Reset to 0 Page 47 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 13 FUNCTION Secondary Clock Stop Status TYPE RO DESCRIPTION Secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped 14 15 Secondary Clkrun Protocol Enable Clkrun Mode RO / RW RO / RW Reset to 0 0: disable protocol 1: enable protocol The bit is RO as 0 when Clock Power Management feature is disabled, or it is RW (default 1) when Clock Power Management feature is enabled by strapping REQ_L[3:2] to both low at deassertion of RESET_L 0: Stop the secondary clock only when bridge is at D3hot state 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus The bit is RO when Clock Power Management feature is disabled, or it is RW when Clock Power Management feature is enabled by strapping REQ_L[3:2] to both low at deassertion of RESET_L Reset to 0 6.3.68 XPIP CONFIGURATION REGISTER 3 – OFFSET A4h BIT 16 FUNCTION ASPM L0s Enable Control TYPE RW 18:17 20:19 31:21 Scrambling Control L0 Enter L1 Timer Control Reserved RW RW RO DESCRIPTION 0: bridge may enter ASPM L0s regardless if Receiver is Electrical Idle 1: bridge may enter ASPM L0s only if Receiver is Electrical Idle Reset to 1 Reset to 00 Reset to 01 Reset to 00 6.3.69 CAPABILITY ID REGISTER – OFFSET A8h BIT 7:0 FUNCTION Capability ID TYPE RO DESCRIPTION Capability ID for subsystem ID and subsystem vendor ID Reset to 0Dh 6.3.70 NEXT POINTER REGISTER – OFFSET A8h BIT 15:8 FUNCTION Next Item Pointer TYPE RO DESCRIPTION Next item pointer (point to PCI Express Capability by default but can be programmed to A0h if Slot Identification Capability is enabled) Reset to B0h (RO as F0h in Legacy Mode to bypass PCIe capability) 6.3.71 RESERVED REGISTER – OFFSET A8h BIT 31:16 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 0000h 6.3.72 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh BIT FUNCTION TYPE DESCRIPTION Page 48 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 15:0 FUNCTION Subsystem Vendor ID TYPE RO DESCRIPTION Subsystem vendor ID identifies the particular add-in card or subsystem Reset to 00h 6.3.73 SUBSYSTEM ID REGISTER – OFFSET ACh BIT 31:16 FUNCTION Subsystem ID TYPE RO DESCRIPTION Subsystem ID identifies the particular add-in card or subsystem Reset to 00h 6.3.74 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h BIT 7:0 FUNCTION PCI Express Capability ID TYPE RO DESCRIPTION PCI Express capability ID Reset to 10h 6.3.75 NEXT CAPABILITY POINTER REGISTER – OFFSET B0h BIT 15:8 FUNCTION Next Item Pointer TYPE RO DESCRIPTION Next Capabilities Pointer Register Reset to F0h 6.3.76 PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h BIT 19:16 23:20 FUNCTION Capability Version Device / Port Type 24 29:25 31:30 Slot Implemented Interrupt Message Number Reserved TYPE RO RO RO RO RO DESCRIPTION Reset to 1h 0000: PCI Express endpoint device 0001: Legacy PCI Express endpoint device 0100: Root port of PCI Express root complex 0101: Upstream port of PCI Express switch 0110: Downstream port of PCI Express switch 0111: PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h Reset to 0 Reset to 0h Reset to 0 6.3.77 DEVICE CAPABILITY REGISTER – OFFSET B4h BIT 2:0 FUNCTION Maximum Payload Size 4:3 Phantom Functions TYPE RO RO DESCRIPTION 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 2h Phantom functions is not supported Reset to 00 Page 49 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 5 FUNCTION 8-bit Tag Field 8:6 Endpoint L0’s Latency TYPE RO RO DESCRIPTION 8-bit tag field supported Reset to 1 Endpoint L0’s acceptable latency 000: less than 64 ns 001: 64 – 128 ns 010: 128 – 256 ns 011: 256 – 512 ns 100: 512 ns – 1 us 101: 1 – 2 us 110: 2 – 4 us 111: more than 4 us 11:9 Endpoint L1’s Latency RO Reset to 000 Endpoint L1’s acceptable latency 000: less than 1 us 001: 1 – 2 us 010: 2 – 4 us 011: 4 – 8 us 100: 8 – 16 us 101: 16 – 32 us 110: 32 – 64 us 111: more than 64 us 12 13 14 15 Attention Button Present Attention Indicator Present Power Indicator Present Role-Based Error Reporting RO RO RO RO Reset to 000 Reset to 0 Reset to 0 Reset to 0 1: Role-Based Error Reporting is supported by the bridge. 17:16 25:18 Reserved Captured Slot Power Limit Value RO RO Reset to 1 Reset to 000 These bits are set by the Set_Slot_Power_Limit message 27:26 Captured Slot Power Limit Scale RO Reset to 00h This value is set by the Set_Slot_Power_Limit message 31:28 Reserved RO Reset to 00 Reset to 0h 6.3.78 DEVICE CONTROL REGISTER – OFFSET B8h BIT 0 1 2 3 4 FUNCTION Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Relaxed Ordering Enable TYPE RW DESCRIPTION Reset to 0h RW Reset to 0h RW RW Reset to 0h Reset to 0h RO Relaxed Ordering is not supported Reset to 0h Page 50 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 7:5 FUNCTION Max Payload Size TYPE RW DESCRIPTION This field sets the maximum TLP payload size for the PI7C9X113SL 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved 8 9 Extended Tag Field Enable Phantom Functions Enable RW RO Reset to 000 Reset to 0 Phantom functions is not supported 10 Auxiliary Power PM Enable RO Reset to 0 Auxiliary power PM is not supported 11 No Snoop Enable RO Reset to 0 Bridge never sets the No Snoop attribute in the transaction it initiates 14:12 Maximum Read Request Size RW Reset to 0 This field sets the maximum Read Request Size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved 15 Configuration Retry Enable RW Reset to 2h Reset to 0 6.3.79 DEVICE STATUS REGISTER – OFFSET B8h BIT 16 17 18 19 20 21 FUNCTION Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected AUX Power Detected Transaction Pending 31:22 Reserved TYPE RWC RWC RWC RWC RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1 0: No transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset to 0 Reset to 0000000000 6.3.80 LINK CAPABILITY REGISTER – OFFSET BCh BIT 3:0 FUNCTION Maximum Link Speed TYPE RO DESCRIPTION Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset to 1 Page 51 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 9:4 FUNCTION Maximum Link Width TYPE RO DESCRIPTION Indicates the maximum width of the Express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 11:10 ASPM Support RO Reset to 01/04h This field indicates the level of Active State Power Management Support 00: reserved 01: L0’s entry supported 10: reserved 11: L0’s and L1’s supported Reset to 11 Reset to 3h The bits are RO as 0h when Clock Power Management feature is disabled, or RO as 6h when Clock Power Management feature is enabled by strapping REQ_L[3:2] to both low at deassertion of RESET_L. 14:12 17:15 L0’s Exit Latency L1’s Exit Latency RO RO 18 Clock Power Management Capable RO 19 20 Reserved Data Link Layer Link Active Reporting Capable Reserved Port Number RO RO Reset to 0/1 Reset to 0 Reset to 0 RO RO Reset to 0h Reset to 00h 23:21 31:24 Reset to 0/6h The bit is RO as 0 when Clock Power Management feature is disabled, or RO as 1 when Clock Power Management feature is enabled by strapping REQ_L[3:2] to both low at deassertion of RESET_L. 6.3.81 LINK CONTROL REGISTER – OFFSET C0h BIT 1:0 FUNCTION ASPM Control TYPE RW DESCRIPTION This field controls the level of ASPM supported on the Express link 00: disabled 01: L0’s entry enabled 10: L1’s entry enabled 11: L0’s and L1’s entry enabled 2 3 Reserved Read Completion Boundary (RCB) RO RO Reset to 00 Reset to 0 Read completion boundary is not supported 4 5 6 Link Disable Retrain Link Common Clock Configuration Extended Sync RO RO RW Reset to 0 Reset to 0 Reset to 0 Reset to 0 RW Reset to 0 7 Page 52 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 8 FUNCTION Enable Clock Power Management 15:9 Reserved TYPE RO / RW RO DESCRIPTION The bit is RO when Clock Power Management feature is disabled, or RW when Clock Power Management feature is enabled by strapping REQ_L[3:2] to both low at deassertion of RESET_L Reset to 0 Reset to 00h 6.3.82 LINK STATUS REGISTER – OFFSET C0h BIT 19:16 FUNCTION Link Speed TYPE RO DESCRIPTION This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link 25:20 Negotiated Link Width RO 26 27 28 29 Link Train Error Link Training Slot Clock Configuration Data Link Layer Link Active RO RO RO RO 31:30 Reserved RO Reset to 1h 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 Reset to 0 Reset to 0 Reset to 1 0: Indicates the Data Link Active state 1: Indicates the Data Link Non-Active state Reset to 0 Reset to 0 6.3.83 RESERVED REGISTER – OFFSET C4 – C8h 6.3.84 XPIP CONFIGURATION REGISTER 0 – OFFSET CCh BIT 0 1 2 3 4 7:5 12:8 14:13 15 31:16 FUNCTION Hot Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct to Configuration State when in LTSSM state Internal Selection for Debug Mode Negotiate Lane Number of Times TS1 Number Counter Transmit N_FTS Number Control Compliance Pattern Parity Control LTSSM Enter L1 Timer Default Value TYPE RW RW RW RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 RW Reset to 0 RW Reset to 3h RW RW Reset to 10h Reset to 0h RW Reset to 0 RW Reset to 0400h 6.3.85 XPIP CONFIGURATION REGISTER 1 – OFFSET D0h Page 53 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 15:0 31:16 FUNCTION L0s Lifetime Timer L1 Lifetime Timer TYPE RW RW DESCRIPTION Reset to 0800h Reset to 0400h 6.3.86 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h BIT 7:0 FUNCTION CDR Recovery Time (in the number of FTS order sets) TYPE RW 14:8 15 22:16 23 L0’s Exit to L0 Latency RXP/RXN Polarity Inversion Enable L1 Exit to L0 Latency Power Down Wait Time RW RW 31:24 Reserved RO DESCRIPTION A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. Reset to 54h Reset to 2h Reset to 1 RW RW Reset to 19h Power management always waits a fixed time and then enters power down mode. Reset to 1 Reset to 0h 6.3.87 CAPABILITY ID REGISTER – OFFSET D8h BIT 7:0 FUNCTION Capability ID for VPD Register TYPE RO DESCRIPTION Reset to 03h 6.3.88 NEXT POINTER REGISTER – OFFSET D8h BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (F0h, points to MSI capabilities) Reset to F0h 6.3.89 VPD REGISTER – OFFSET D8h BIT 17:16 23:18 30:24 31 FUNCTION Reserved VPD Address for Read/Write Cycle Reserved VPD Operation TYPE RO RW DESCRIPTION Reset to 0 Reset to 0 RO RW Reset to 0 0: Generate a read cycle from the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at ‘0’ until EEPROM cycle is finished, after which the bit is then set to ‘1’. Data for reads is available at register ECh. 1: Generate a write cycle to the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at ‘1’ until EEPROM cycle is finished, after which it is then cleared to ‘0’. Reset to 0 6.3.90 VPD DATA REGISTER – OFFSET DCh BIT FUNCTION TYPE DESCRIPTION Page 54 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 31:0 FUNCTION VPD Data TYPE RW DESCRIPTION VPD Data (EEPROM data [address + 0x40]) The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0 6.3.91 EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h BIT 7:0 11:8 30:12 FUNCTION Register Number Extended Register Number Reserved TYPE RW RW RO DESCRIPTION Reset to 00h Reset to 0h Reset to 0 6.3.92 EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h BIT 31:0 FUNCTION Extended Configuration Access Data TYPE RW DESCRIPTION Access to this register will access the internal configuration registers indexed by bit [11:0] at offset E0h Reset to 0 6.3.93 RESERVED REGISTERS – OFFSET E8h – ECh 6.3.94 MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h BIT 7:0 FUNCTION Capability ID for MSI Registers TYPE RO DESCRIPTION Reset to 05h 6.3.95 NEXT CAPABILITIES POINTER REGISTER – F0h BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (00h indicates the end of capabilities) Reset to 00h 6.3.96 MESSAGE CONTROL REGISTER – OFFSET F0h BIT 16 FUNCTION MSI Enable 19:17 Multiple Message Capable TYPE RW RO DESCRIPTION 0: Disable MSI and default to INTx for interrupt 1: Enable MSI for interrupt service and ignore INTx interrupt pins Reset to 0 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Page 55 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 22:20 FUNCTION Multiple Message Enable 23 31:24 64-bit Address Capable Reserved TYPE RW RO RO DESCRIPTION 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Reset to 1 Reset to 00h 6.3.97 MESSAGE ADDRESS REGISTER – OFFSET F4h BIT 1:0 31:2 FUNCTION Reserved System Specified Message Address TYPE RO RW DESCRIPTION Reset to 00 Reset to 00000000h 6.3.98 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h BIT 31:0 FUNCTION System Specified Message Upper Address TYPE RW DESCRIPTION Reset to 00000000h 6.3.99 MESSAGE DATA REGISTER – OFFSET FCh BIT 15:0 31:16 FUNCTION System Specified Message Data Reserved TYPE RW RO DESCRIPTION Reset to 0000h Reset to 0000h 6.3.100 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h BIT 15:0 FUNCTION Advance Error Reporting Capability ID TYPE RO DESCRIPTION Reset to 0001h 6.3.101 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h BIT 19:16 FUNCTION Advance Error Reporting Capability Version TYPE RO DESCRIPTION Reset to 1h 6.3.102 NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset (150h points to VC capability) Reset to 150h 6.3.103 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h BIT 0 FUNCTION Training Error Status TYPE RWCS DESCRIPTION Reset to 0 Page 56 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Reserved Data Link Protocol Error Status Reserved Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Reserved TYPE RO RWCS DESCRIPTION Reset to 0 Reset to 0 RO RWCS RWCS Reset to 0 Reset to 0 Reset to 0 RWCS RWCS RWCS Reset to 0 Reset to 0 Reset to 0 RWCS RWCS RWCS RWCS Reset to 0 Reset to 0 Reset to 0 Reset to 0 RO Reset to 0 6.3.104 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Training Error Mast Reserved Data Link Protocol Error Mask Reserved Poisoned TLP Mask Flow Control Protocol Error Mask Completion Timeout Mask Completion Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Unsupported Request Error Mask Reserved TYPE RWS RO RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 RO RWS RWS Reset to 0 Reset to 0 Reset to 0 RWS RWS RWS Reset to 0 Reset to 0 Reset to 0 RWS RWS RWS RWS Reset to 0 Reset to 0 Reset to 0 Reset to 0 RO Reset to 0 6.3.105 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 FUNCTION Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity ECRC Error Severity TYPE RWS RO RWS DESCRIPTION Reset to 1 Reset to 0 Reset to 1 RO RWS RWS Reset to 0 Reset to 0 Reset to 1 RWS Reset to 0 RWS RWS Reset to 0 Reset to 0 RWS RWS RWS Reset to 1 Reset to 1 Reset to 0 Page 57 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 20 31:21 FUNCTION Unsupported Request Error Severity Reserved TYPE RWS RO DESCRIPTION Reset to 0 Reset to 0 6.3.106 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h BIT 0 5:1 6 7 8 11:9 12 13 31:14 FUNCTION Receiver Error Status Reserved Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Advisory Non-Fatal Error Status Reserved TYPE RWCS RO RWCS RWCS RWCS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 RO RWCS Reset to 0 Reset to 0 RWCS Reset to 0 RO Reset to 0 6.3.107 CORRECTABLE ERROR MASK REGISTER – OFFSET 114h BIT 0 5:1 6 7 8 11:9 12 13 31:14 FUNCTION Receiver Error Mask Reserved Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Reserved Replay Timer Timeout Mask Advisory Non-Fatal Error Mask Reserved TYPE RWS RO RWS RWS RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 RO RWS RWS Reset to 0 Reset to 0 This bit is set by default to be compatible with software that does not comprehend Role-Based Error Reporting RO Reset to 1 Reset to 0 6.3.108 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h BIT 4:0 5 6 7 8 31:9 FUNCTION First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved TYPE ROS RO RWS RO RWS RO DESCRIPTION Reset to 0h Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0 6.3.109 HEADER LOG REGISTER 1 – OFFSET 11Ch BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 6.3.110 HEADER LOG REGISTER 2 – OFFSET 120h Page 58 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 6.3.111 HEADER LOG REGISTER 3 – OFFSET 124h BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 6.3.112 HEADER LOG REGISTER 4 – OFFSET 128h BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 6.3.113 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 31:14 FUNCTION Target Abort on Split Completion Status Master Abort on Split Completion Status Received Target Abort Status Received Master Abort Status Reserved Unexpected Split Completion Error Status Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR_L Assertion Detected Status SERR_L Assertion Detected Status Internal Bridge Error Status Reserved TYPE RWCS DESCRIPTION Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RO RWCS Reset to 0 Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS RO Reset to 0 Reset to 0 6.3.114 SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h BIT 0 FUNCTION Target Abort on Split Completion Mask TYPE RWS DESCRIPTION Reset to 0 Page 59 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 1 2 3 4 5 6 7 8 9 10 11 12 13 31:14 FUNCTION Master Abort on Split Completion Mask Received Target Abort Mask Received Master Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask Delayed Transaction Discard Timer Expired Mask PERR_L Assertion Detected Mask SERR_L Assertion Detected Mask Internal Bridge Error Mask Reserved TYPE RWS DESCRIPTION Reset to 0 RWS RWS Reset to 0 Reset to 1 RO RWS Reset to 0 Reset to 1 RWS Reset to 0 RWS Reset to 1 RWS Reset to 1 RWS Reset to 1 RWS Reset to 1 RWS Reset to 0 RWS Reset to 1 RWS RO Reset to 0 Reset to 0 6.3.115 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 31:14 FUNCTION Target Abort on Split Completion Severity Master Abort on Split Completion Severity Received Target Abort Severity Received Master Abort Severity Reserved Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR_L Assertion Detected Severity SERR_L Assertion Detected Severity Internal Bridge Error Severity Reserved TYPE RWS DESCRIPTION Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RO RWS Reset to 0 Reset to 0 RWS Reset to 1 RWS Reset to 0 RWS Reset to 1 RWS Reset to 1 RWS Reset to 0 RWS Reset to 0 RWS Reset to 1 RWS Reset to 0 RO Reset to 0 Page 60 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.116 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h BIT 4:0 31:5 FUNCTION Secondary First Error Pointer Reserved TYPE ROS RO DESCRIPTION Reset to 0 Reset to 0 6.3.117 SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h BIT 35:0 FUNCTION Transaction Attribute TYPE ROS 39:36 Transaction Command Lower ROS 43:40 Transaction Command Upper ROS 63:44 95:64 Reserved Transaction Address ROS ROS 127:96 Transaction Address ROS DESCRIPTION Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase Reset to 0 Transaction command lower, CBE [3:0] during first address phase Reset to 0 Transaction command upper, CBE [3:0] during second address phase of DAC transaction Reset to 0 Reset to 0 Transaction address, AD [31:0] during first address phase Reset to 0 Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0 6.3.118 RESERVED REGISTER – OFFSET 14Ch 6.3.119 VC CAPABILITY ID REGISTER – OFFSET 150h BIT 15:0 FUNCTION VC Capability ID TYPE RO DESCRIPTION Reset to 0002h 6.3.120 VC CAPABILITY VERSION REGISTER – OFFSET 150h BIT 19:16 FUNCTION VC Capability Version TYPE RO DESCRIPTION Reset to 0001 6.3.121 NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset – the end of capabilities Reset to 0 6.3.122 PORT VC CAPABILITY REGISTER 1 – OFFSET 154h BIT 2:0 3 6:4 7 9:8 FUNCTION Extended VC Count Reserved Low Priority Extended VC Count Reserved Reference Clock TYPE RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Page 61 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge BIT 11:10 31:12 FUNCTION Port Arbitration Table Entry Size Reserved TYPE RO RO DESCRIPTION Reset to 0 Reset to 0 6.3.123 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h BIT 7:0 23:8 31:24 FUNCTION VC Arbitration Capability Reserved VC Arbitration Table Offset TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 6.3.124 PORT VC CONTROL REGISTER – OFFSET 15Ch BIT 0 3:1 15:4 FUNCTION Load VC Arbitration Table VC Arbitration Select Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 6.3.125 PORT VC STATUS REGISTER – OFFSET 15Ch BIT 16 31:17 FUNCTION VC Arbitration Table Status Reserved TYPE RO RO DESCRIPTION Reset to 0 Reset to 0 6.3.126 VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h BIT 7:0 13:8 14 15 22:16 23 31:24 FUNCTION Port Arbitration Capability Reserved Advanced Packet Switching Reject Snoop Transactions Maximum Time Slots Reserved Port Arbitration Table Offset TYPE RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to0 Reset to 0 Reset to 0 Reset to 0 6.3.127 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h BIT 0 FUNCTION TC / VC Map TYPE RO 7:1 TC / VC Map RW 15:8 16 19:17 23:20 26:24 30:27 31 Reserved Load Port Arbitration Table Port Arbitration Select Reserved VC ID Reserved VC Enable RO RO RO RO RO RO RO DESCRIPTION For TC0 Reset to 1 For TC7 to TC1 Reset to 7Fh Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1 6.3.128 VC0 RESOURCE STATUS REGISTER – OFFSET 168h BIT 0 1 31:2 FUNCTION Port Arbitration Table 1 VC0 Negotiation Pending Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Page 62 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 6.3.129 RESERVED REGISTERS – OFFSET 16Ch – 2FCh 6.3.130 EXTENDED GPIO DATA AND CONTROL REGISTER – OFFSET 300h BIT 2:0 5:3 8:6 11:9 14:12 31:15 FUNCTION Extended GPIO Output Write-1-to-Clear Extended GPIO Output Write-1-to-Set Extended GPIO Output Enable Write-1-to-Clear Extended GPIO Output Enable Write-1-to-Set Extended GPIO Input Data Register Reserved TYPE RW DESCRIPTION Reset to 0 RW Reset to 0 RW Reset to 0 RW Reset to 0 RO Reset to 0 RO Reset to 0 6.3.131 EXTENDED GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h BIT 2:0 FUNCTION Extended GPO Output Write-1-to-Clear 5:3 Extended GPO Output Write-1-to-Set Reserved Extended GPO Output Enable Write-1-to-Clear Extended GPO Output Enable Write-1-to-Set Reserved Extended GPI Input Data Register Reserved 7:6 10:8 13:11 15:14 18:16 31:19 TYPE RW DESCRIPTION GPI/GPO Data and Control Register is only valid when external arbiter is used. RW Reset to 0 Reset to 0 RO RW Reset to 0 Reset to 0 RW Reset to 0 RO RO Reset to 0 Reset to 0 RO Reset to 0 6.3.132 RESERVED REGISTERS – OFFSET 308h – 30Ch 6.3.133 REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h BIT 11:0 FUNCTION Replay Timer 12 Replay Timer Enable RW 15:13 29:16 Reserved Acknowledge Latency Timer RO RW 30 Acknowledge Latency Timer Enable Reserved RW 31 TYPE RW RO DESCRIPTION Replay Timer Reset to 115h Replay Timer Enable Reset to 0 Reset to 0 Acknowledge Latency Timer Reset to CDh Acknowledge Latency Timer Enable Reset to 0 Reset to 0 6.3.134 RESERVED REGISTERS – OFFSET 314h – FFCh Page 63 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 7 GPIO PINS AND SM BUS ADDRESS GPIO[3:0] are defined for SMBUS device ID if TM0=1. GPIO[3:0] can be further defined to serve other functions in the further generations. With 128QFP package, additional three GPI and three GPO pins can be used when external arbiter is selected, and REQ_L[3:1] and GNT_L[3:1] will be mapped to GPI[2:0] and GPO[2:0] respectively. The address-strapping table of SMBUS with GPIO [3:0] pins is defined in the following table: Table 7-1 SM Bus Device ID Strapping SM Bus Address Bit Address bit [7] Address bit [6] Address bit [5] Address bit [4] Address bit [3] Address bit [2] Address bit [1] SM Bus device ID =1 =1 =0 = GPIO [3] = GPIO [2] = GPIO [1] = GPIO [0] Page 64 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 8 CLOCK SCHEME PCI Express Interface: PI7C9X113SL requires 100MHz differential clock inputs through the pins of REFCLKP and REFCLKN. PCI Interface: PI7C9X113SL generates four clock outputs, from either external clock input (1MHz to 66MHz) at CLKIN or internal clock generator: PI7C9X113SL can use configuration control to enable or disable the secondary clock output: CLKOUT[3:0]. PI7C9X113SL used either internally feedbacked clock from CLKOUT[0] or external clock input applied at CLKOUT[0], for internal secondary interface logic. For using internal clock source, the internal clock generator needs to be enabled with CLKIN driven high or low. CLKIN and M66EN signals become the selection for PCI Frequency at 50MHz/25MHz or 66MHz/33MHz. Table 8-1 Frequency of PCI CLKOUT with internal clock source: CLKIN 0 0 1 1 M66EN 0 1 0 1 PCI Clock 33MHz 66MHz 25MHz 50MHz The PI7C9X113SL PCI Clock Outputs, CLKOUT [3:0], can be enabled or disabled through the configuration register. PI7C9X113SL supports three different implementations of PCI clock.  Internal clock generator, and internal clock buffering. o Internal feedback o External feedback  External clock source, and internal clock buffering. o Internal feedback o External feedback  External clock source, and external clock buffering. Page 65 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Figure 8-1 Topology of internal clock generator and internal clock buffering – internal feedback mode Figure 8-2 Topology of internal clock generator and internal clock buffering – external feedback mode Page 66 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Figure 8-3 Topology of external clock generator and internal clock buffering – internal feedback mode PI7C9X113SL CLKOUT[0] CLKOUT[1] Clock Source Clock Generator CLKIN CLKOUT[2] CLKOUT[3] PCI Device PCI Device PCI Device PCI Device Figure 8-4 Topology of external clock generator and internal clock buffering – external feedback mode PI7C9X113SL CLKOUT[0] Note: Feedback source could be from any CLKOUT CLKOUT[1] Clock Generator Clock Source CLKIN CLKOUT[2] CLKOUT[3] PCI Device PCI Device In this configuration, user simply connects the external clock source to CLKIN pin. And user needs to make sure the clock is preset (toggling) before the fundamental reset de-asserted (e.g. PERST_L). In this mode, the frequency is the same as the input clock source. Page 67 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge Figure 8-5 Topology of external clock generator and external clock buffering In this configuration, user simply connects the external clock from the clock buffers to CLKOUT0. And user needs to make sure the clock is preset (toggling) before the fundamental reset de-asserted (e.g. PERST_L deassertion). Page 68 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 9 INTERRUPTS PI7C9X113SL supports interrupt message packets on PCIe side. PI7C9X113SL supports PCI interrupt (INTA, B, C, D) pins or MSI (Message Signaled Interrupts) on PCI side. PCI interrupts and MSI are mutually exclusive. In order words, if MSI is enabled, PCI interrupts will be disabled. PI7C9X113SL support 64-bit addressing MSI. PI7C9X113SL maps the PCI interrupts pins or MSI if enable on PCI side to interrupt message packets on PCIe side. There are eight interrupt message packets. They are Assert_INTA, Assert_INTB, Assert_INTC, Assert_INTD, Deassert_INTA, Deassert_INTB, Deassert_INTC, and Deassert_INTD. PI7C9X113SL tracks the PCI interrupt (INTA, INTB, INTC, and INTD) pins and maps them to the eight interrupt messages. See Table 9-1 for interrupt mapping information. Table 9-1 PCI interrupt to PCIe interrupt message mapping in forward bridge mode PCI Interrupts (from sources of interrupts) INTA INTB INTC INTD PCIe Interrupt message packets (to host controller) INTA message INTB message INTC message INTD message Page 69 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 10 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS 10.1 EEPROM (I2C) INTERFACE PI7C9X113SL supports EEPROM interface through I2C bus. In EEPROM interface, pin 4 is the EEPROM clock (SCL) and pin 6 is the EEPROM data (SDL). TM1 and TM0 are strapped accordingly to select EEPROM interface or System Management Bus. EEPROM (I2C) interface is enabled with TM1=0 and TM0=0. When EEPROM interface is selected , SCL is an output. SCL is the I2C bus clock to the I2C device. In addition, SDL is a bidirectional signal for sending and receiving data. 10.2 SYSTEM MANAGEMENT BUS PI7C9X113SL supports SM bus protocol if TM1=0 and TM0=1. In addition, SMBCLK (pin 4) and SMBDAT (pin 6) are utilized as the clock and data pins respectively for the SM bus. When SM bus interface is selected, SMBCLK pin is an input for the clock of SM bus and SMBDAT pin is an open drain buffer that requires external pull-up resistor for proper operation. 10.3 EEPROM AUTOLOAD CONFIGURATION EEPROM Byte Addresses 00-01h Cfg Offset Description 00-01h 02-03h 08h 09h 0A-0Bh 34h 40-41h 42-43h 48-4Bh 68-6Bh 81-82h 108h 91-93h A1-A3h A4-A7h A8-ABh EEPROM signature: Autoload will only proceed if it reads a value of 1516h on the first word loaded. Region Enable: Enables or disables certain regions of PCI configuration space from being loaded from the EEPROM. bit 0: reserved bit 4-1: 0000=stop autoload at offset 0Bh: Group 1 0001=stop autoload at offset 67h: Group 2 0011=stop autoload at offset AFh: Group 3 0111=stop autoload at offset D7h: Group 4 other combinations are undefined bit 7-5: reserved Enable Miscellaneous functions: (for transparent mode only) bit 0: ISA Enable control bit write protect: when this bit is set, 9x111 will change the bit 2 of 3Eh into RO, and ISA enable feature will not be available. Vendor ID Device ID Revision ID Class Code: low bytes of Class Code register Class Code higher bytes: upper bytes of Class Code register Capability Pointer PCI data prefetching control Chip control 0 Arbiter Mode/Enable/Priority PCIE Transmitter/Receiver control PCIX Capability Uncorrectable Error Mask register Power Management Capability SI Capability Secondary Clock and Clkrun Control SSID/SSVID Capability 02h 03h 04-05h 06-07h 08h 09h 0A-0Bh 0Ch 0D-0Eh 0F-10h 11-14h 15-18h 19-1Ah 1Bh 1C-1Eh 1F-21h 22-25h 26-29h Page 70 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge EEPROM Byte Addresses 2A-2Dh 2E-30h 31-34h 35-38h 39-3Ch 3D-40h 41-44h 45-48h 49-4Ah 4B-4Ch 4Dh 4E-4Fh 50-51h 52-55h 56-57h 58-5Bh 5C-5Dh 5E-61h 62-63h 64-67h 68-77h 79-7Bh 7C-7Dh 7Eh 7F-82h 83-86h 87-8Ah 8B-8Eh 8F-91h 92h 93h 94h 95-96h 97-98h 99-9Ah 9B-9Eh 9F-A2h A3-A6h A7-A8h A9h AA-ABh AC-ADh AE-AFh B0-B3h B4-B6h B7h B8-BBh BC-BFh C0-C3h C4-C7h C8-CBh CC-CFh D0-D3h D4-D5h D6-D7h D8-FFh Cfg Offset Description AC-AFh B1-B3h B4-B7h BC-BFh C4-C7h CC-CFh D0-D3h D4-D7h D9-DAh F1-F2h 100h 109-10Ah E0-E1h E4-E7h E0-E1h E4-E7h E0_E1h E4-E7h E0_E1h E4-E7h SSID/SSVID PCI Express Capabilities Device Capabilities Link Capabilities Slot Capabilities XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 VPD Capability MSI Capability Advance Error Reporting Capability Uncorrectable Error Mask register Extended Cfg Access Address Extended Cfg Access Data Extended Cfg Access Address Extended Cfg Access Data Extended Cfg Access Address Extended Cfg Access Data Extended Cfg Access Address Extended Cfg Access Data Reserved GPIO Data and Control Reserved PCIX Bridge status Upstream Split Transaction Downstream Split Transaction PM Control and Status Device Capabilities Device Control/Status Reserved Link Control/Status Reserved Link Control/Status Slot Control/Status Interrupt Control VPD data Message Address Message Upper Address Message Data Reserved Sec Interrupt Control Replay Timer Ack Latency Timer Command/Status Cacheline/Primary Latency Timer/Header Type Reserved Bus Number/Secondary Latency Timer I/O Base/Limit / Secondary Status Memory Base/Limit Prefetch Memory Base/Limit Prefetch Upper 32 Base Prefetch Upper 32 Limit I/O Upper 16 Base/Limit Reserved Bridge Control Reserved 79-7Bh 86h 88-8Bh 8C-8Fh 94-97h B4-B7h B8-BAh C0h C2-C3h C8-C9h 3C-3Dh DC-DFh F4-F7h F8-FBh FC-FDh 7C-7Dh 310-311h 312-313h 04-07h 0C-0Eh 18-1Bh 1C-1Fh 20-23h 24-27h 28-2Bh 2C-2Fh 30-33h 3E-3Fh Page 71 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 11 RESET SCHEME PI7C9X113SL requires the fundamental reset (PERST_L) input for internal logic. Also, PI7C9X113SL has a power-on-reset (POR) circuit to detect VDDCAUX power supply for auxiliary logic control.  Cold Reset: A cold reset is a fundamental or power-on reset that occurs right after the power is applied to PI7C9X113SL (during initial power up). See section 7.1.1 of PCI Express to PCI Bridge Specification, Revision 1.0 for details.  Warm Reset: A warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to PI7C9X113SL.  Hot Reset: A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to PI7C9X113SL. PI7C9X113SL will enter to training control reset when it receives two consecutive TS1 or TS2 order-sets with reset bit set.  DL_DOWN Reset: If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status. PI7C9X113SL discards all transactions and returns all logic and registers to initial state except the sticky registers. Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X113SL will generate PCI reset (RESET_L) to the downstream devices on the PCI bus in forward bridge mode. The PCI reset de-assertion follows the de-assertion of the reset received from PCIe interface. The reset bit of Bridge Control Register may be set depending on the application. PI7C9X113SL will tolerant to receive and process SKIP order-sets at an average interval between 1180 to 1538 Symbol Times. PI7C9X113SL does not keep PCI reset active when VD33 power is off even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down resistor on its application board to ensure PCI reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management Specification Revision 1.1). PI7C9X113SL transmits one Electrical Idle order-set and enters to Electrical Idle. Page 72 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 12 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C9X113SL for board-level continuity test and diagnostics. The supported TAP pins are TCK, TDI, TDO and TMS. All digital input, output, input/output pins are tested except TAP pins. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. 12.1 INSTRUCTION REGISTER PI7C9X113SL implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in Table 14-1. Those bit combinations that are not listed are equivalent to the BYPASS (11111) instruction: Table 12-1 Instruction register codes Instruction EXTEST SAMPLE HIGHZ CLAMP Operation Code (binary) 00000 00001 00101 00100 Register Selected Boundary Scan Boundary Scan Bypass Bypass IDCODE 01100 Device ID BYPASS INT_SCAN MEM_BIST 11111 00010 01010 Bypass Internal Scan Memory BIST Operation Drives / receives off-chip test data Samples inputs / pre-loads outputs Tri-states output and I/O pins except TDO pin Drives pins from boundary-scan register and selects Bypass register for shifts Accesses the Device ID register, to read manufacturer ID, part number, and version number Selected Bypass Register Scan test Memory BIST test 12.2 BYPASS REGISTER The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C9X113SL. 12.3 DEVICE ID REGISTER This register identifies Pericom as the manufacturer of the device and details the part number and revision number for the device. Table 12-2 JTAG device ID register Bit 31:28 27:12 11:1 0 Type RO RO RO RO Value 01h E110h 23Fh 1b Description Version number Last 4 digits (hex) of the die part number Pericom identifier assigned by JEDEC Fixed bit equal to 1’b1 Page 73 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 12.4 BOUNDARY SCAN REGISTER The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X113SL package pins. The VDD, VSS, and JTAG pins are not in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin. The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK. 12.5 JTAG BOUNDARY SCAN REGISTER ORDER TBD Page 74 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 13 POWER MANAGEMENT PI7C9X113SL supports D0, D3-hot, D3-cold Power States. D1 and D2 states are not supported. The PCI Express Physical Link Layer of the PI7C9X113SL device supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3 ready and L3 Power States. For the PCI Port of PI7C9X113SL, it supports the standard PCI Power Management States with B0, B1, B2 and B3. During D3-hot state, the main power supplies of VDDP, VDDC, and VD33 can be turned off to save power while keeping the VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary information to be restored to the full power D0 state. PI7C9X113SL has been designed to have sticky registers that are powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state changes. Along with the operating system and application software, PCI devices can achieve optimum power saving by using PME_L. PI7C9X113SL converts PME_L signal information to power management messages to the upstream switches or root complex. PI7C9X113SL also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X113SL supports WAKE_L signal but does not support beacon generation during power management. Page 75 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 14 ELECTRICAL AND TIMING SPECIFICATIONS 14.1 ABSOLUTE MAXIMUM RATINGS Table 14-1 Absolute maximum ratings (Above which the useful life may be impaired. For user guidelines, not tested.) -65oC to 150oC -40oC to 85oC -0.3v to 3.0v Storage Temperature Ambient Temperature with power applied PCI Express supply voltage to ground potential (VDDA, VDDC, and VDDCAUX) PCI supply voltage to ground potential (VD33 and VAUX) DC input voltage for PCI Express signals DC input voltage for PCI signals -0.3v to 3.6v -0.3v to 3.0v -0.5v to 5.75v Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 14.2 DC SPECIFICATIONS Table 14-2 DC electrical characteristics Power Pins VDDA VDDA33 VDDC VDDCAUX VD33 VAUX Min. 1.05v 3.0v 1.05v 0.9v 3.0v 3.0v Typ. 1.1v 3.3v 1.1v 1.0v 3.3v 3.3v Max. 1.15v 3.6v 1.15v 1.15v 3.6v 3.6v VDDA: analog power supply for PCI Express Interface VDDA33: high power supply for PCI Express Interface VDDC: digital power supply for the core VDDCAUX: digital auxiliary power supply for the core VD33: digital power supply for PCI interface VAUX: digital auxiliary power supply for PCI interface In order to support auxiliary power management fully, it is recommended to have VD33/VDDC and VAUX/VDDCAUX separated. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X113SL is less than 350 mW. PI7C9X113SL is capable of sustaining 1500V human body model for the ESD protection without any damages. Page 76 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 14.3 AC SPECIFICATIONS Table 14-3 PCI bus timing parameters Symbol Tsu Tsu (ptp) Th Tval Tval (ptp) Ton Toff 1. 2. 3. 4. Parameter Input setup time to CLK – bused signals 1,2,3 Input setup time to CLK – point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay – bused signals 1,2,3 CLK to signal valid delay – point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2 MIN 3 5 0 2 2 2 - 66 MHz MAX 6 6 14 33 MHz MIN MAX 7 10, 124 0 2 11 2 12 2 28 Units ns See Figure 16 –1 PCI Signal Timing Measurement Conditions. All PCI interface signals are synchronized to CLKOUT0. Point-to-point signals are REQ_L [7:0], GNT_L [7:0], LOO, and ENUM_L. Bused signals are AD, CBE, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, LOCK_L, STOP_L and IDSEL. REQ_L signals have a setup of 10ns and GNT_L signals have a setup of 12ns. Figure 14-1 PCI signal timing conditions Page 77 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 15 PACKAGE INFORMATION The package of PI7C9X113SL comes in 14mm x 14mm LQFP (128 Pin) package. The pin pitch is 0.4mm. This package also includes an exposed ground on the bottom surface of the package. Pericom highly recommends implementing this exposed ground pad on any customer boards. The following are the package information and mechanical dimension: Figure 15-1 Package outline drawing Page 78 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3 PI7C9X113SL PCIe-to-PCI Bridge 16 ORDERING INFORMATION PART NUMBER PIN – PACKAGE PB-FREE & GREEN TEMPERATURE RANGE PI7C9X113SLFDE 128 – LQFP (Exposed ground pad) YES 0C TO +85C Page 79 of 79 Pericom Semiconductor 10-0209 July 2010, Revision 0.3