PI7C9X20303SLCFDE

Not Recommended for New Design PI7C9X20303SL PCI EXPRESS® PACKET SWITCH DATASHEET REVISION 1.2 December 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet DISCLAIMER The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this document may be copied or reproduced in any form or by any means without prior written consent of PSC. The information in this document is subjected to change without notice. PSC retains the right to make changes to this document at any time without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any use of the information contained in this document. LIFE SUPPORT POLICY Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) 2) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. Page 2 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet REVISION HISTORY Date 9/13/07 10/04/07 Revision Number 0.1 0.2 10/31/07 0.3 2/20/08 0.4 Description Drafted Preliminary Datasheet Corrected Chapter 3 Pin Description (DTX’s and DEQ’s default values) Updated Chapter 3.5 JTAG Signals description Updated Chapter 7.2.53 bit Remove VDDP, VDDAUX from Chapter 10 Power Management and Chapter 11.1 Absolute Maximum Ratings Revised Chapter 10 Power Management Corrected Chapter 3 Pin Description (PERP/PERN, PETP/PETN, WAKEUP_L, SLOT_IMP, SLOTCLK, EEPD, SMBDATA, SCAN_EN, PORTACT to PORTERR, DTX, DEQ) Updated 5.1 Physical Layer Circuit and Chapter 5.6 Queue Updated Disclaimer Corrected Chapter 2 General Description Updated Chapter 13 Ordering Information Corrected Chapter 3 Pin Description (DWNRST_L, SLOT_IMP, PORTERR, NC) Corrected Chapter 4 Pin Assignment (DWNRST_L[3], SLOT_IMP[3], PORTERR[3]) Removed Virtual Channel 1 related information in Chapter 2 General Description and Chapter 5 (5.5 TC/VC Mapping, 5.6 Queue, 5.7 Transaction Ordering, 5.9 VC Arbitration) Updated Footer Updated Chapter 5.8 Port Arbitration Updated Chapter 6.1.3 EEPROM Space Address Map Added Chapter 6.2 SMBus Fixed Chapter 6.1.4 Mapping EEPROM table format Updated Chapter 7 Registers (Offset 08h, 100h, 140h to 1BCh, B0h bit 31) Updated Chapter 6 EEPROM (50h, 52h, 54h Reserved) Updated 7.2.91 [7:0] (Removed VC1 description) Corrected Chapter 5 Functional Description (multiple virtual channels) Updated Chapter 6 EEPROM (0Ch) Modified Chapter 7 Registers (7.2.2 Device ID Register, 7.2.50 Bit[13:15] Replay Time-Out Counter, 7.2.52 Bit[14:15] Switch Operation Mode, 7.2.64 PCI Express Capability Bit[24], 7.2.70 Link Status Bit[28], 7.2.99 Power Budgeting Data, 7.2.100 Power Budget Capability) Updated 9.5 JTAG Boundary Scan Register Order Updated Chapter 3.5 Power Pins (VDDC, VDDA, VDDAUX, VTT) Updated Chapter 6 EEPROM (A0h, A2h, A4h) Updated Chapter 1 Features (Power Dissipation) Updated Chapter 11.1 AC Specification (VDDAUX) Updated Chapter 11.2 DC Specification (Power Consumption, VDDAUX) Updated Chapter 10 Power Management (VDDAUX) Page 3 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet Date 5/28/08 Revision Number 0.5 7/10/08 0.6 9/5/08 0.7 10/3/08 0.8 11/24/08 1.0 7/20/09 1.1 12/21/09 1.2 Description Updated 1 Features (typical latency, removed peer-to-peer switching, power consumption) Updated Chapter 3.1 PCI Express Interface Signals (REFCLKP, REFCLKN, PRSNT) Updated Chapter 4.1 PIN List of 128-PIN LQFP (PRSNT) Modified 5.1 Physical Layer Circuit Updated Chapter 6.1.3 EEPROM Space Address Map (10h to 14h, 50h to 54h) Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers (0Ch: Ordering Frozen, TX SOF Latency, Surprise Down Capability Enable, Power Management Data Select, 20h, 22h, 24h: Removed LPVC, Added PMCSR, 51h, 52h, 53h, 54h, 55h, 56h) Updated Chapter 7.2 Transparent Mode Configuration Registers (A4h, B4h, B8, BCh, C0h, C4h) Updated 7.2.5 Revision ID Register, 7.2.27 Interrupt Pin Register, 7.2.32 Power Management Data Register Bit[3], 7.2.46 Next Item Pointer Register, 7.2.50 Replay Time-Out Counter, 7.2.51 Acknowledge Latency Timer, 7.5.52 Switch Operation Mode, 7.2.53 Switch Operation Mode (Downstream Port) Bit[16:31], 7.2.54 XPIP CSR2, 7.2.55 SSID/SSVID Capability ID Register, 7.2.56 Next Item Pointer Register, 7.2.57 Subsystem Vendor ID Register, 7.2.58 Subsystem ID Register, 7.2.65 PCI Express Capabilities Register Bit[19:16], 7.2.69 Link Capabilities Register Bit 19, 7.2.86 Capability Version Bit[19:16], 7.2.93 VC Resource Control Register Bit [26:24], 7.2.97 Capability Version Bit[19:16] Modified 1. Features Modified 3.3 Miscellaneous Signals (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS, LODRV to P2_CTCDIS, DTX[3] to TEST7) Modified 4.1 Pin List (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS, LODRV to P2_CTCDIS[2], DTX[3] to TEST7) Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers (0Ch, 10h, 12h, 14h) Corrected 7.2.27 Interrupt Pin Register Added 7.2.55 TL CSR Modified 11.2 Power Consumption Updated Chapter 1 Features (updated Industrial Temperature Range) Updated Section 11.1 Absolute Maximum Ratings: Ambient Temperature with power applied Updated Figure 12-1 Package outline drawing Updated Chapter 1 Features (power dissipation) Modified 11.2 Power Consumption Corrected Chapter 7.2 (8Ch - Next Item Pointer) Updated Figure 12-1 Package outline drawing Updated Chapter 13 Ordering Information Removed “Preliminary” and “Confidential” references Updated Chapter 3.2 Port Configuration Signals (PRSNT, SLOTCLK) Updated Chapter 3.3 Miscellaneous Signals (updated PWR_SAV pin, SMBCLK, SMBDATA, PWR_SAV, CTCDIS, EEPD) Updated Chapter 3.4 JTAG Boundary Scan Signals (TMS, TDI, TRST_L) Updated Chapter 7.2.52 Switch Operation Mode (Bit[31:16]) Updated Chapter 13 Ordering Information Updated Section 7 Register Description (7.2.52 Switch Operation Mode (Upstream Port) Bit[27:26] and Bit[29:28], 7.2.53 Switch Operation Mode (Downstream Port) Bit[27:26] and Bit[29:28]) Page 4 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet TABLE OF CONTENTS 1 FEATURES ......................................................................................................................................................... 10 2 GENERAL DESCRIPTION .............................................................................................................................. 11 3 PIN DESCRIPTION........................................................................................................................................... 12 3.1 3.2 3.3 3.4 3.5 4 PIN ASSIGNMENTS ......................................................................................................................................... 15 4.1 5 PCI EXPRESS INTERFACE SIGNALS .................................................................................................... 12 PORT CONFIGURATION SIGNALS ....................................................................................................... 12 MISCELLANEOUS SIGNALS.................................................................................................................. 12 JTAG BOUNDARY SCAN SIGNALS ...................................................................................................... 13 POWER PINS ............................................................................................................................................. 14 PIN LIST OF 128-PIN LQFP ....................................................................................................................... 15 FUNCTIONAL DESCRIPTION ....................................................................................................................... 16 5.1 PHYSICAL LAYER CIRCUIT .................................................................................................................. 16 5.2 DATA LINK LAYER (DLL) ...................................................................................................................... 18 5.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) .............................................. 18 5.4 ROUTING .................................................................................................................................................. 18 5.5 TC/VC MAPPING ...................................................................................................................................... 19 5.6 QUEUE ....................................................................................................................................................... 19 5.6.1 PH ....................................................................................................................................................... 19 5.6.2 PD ....................................................................................................................................................... 19 5.6.3 NPHD ................................................................................................................................................. 19 5.6.4 CPLH .................................................................................................................................................. 19 5.6.5 CPLD .................................................................................................................................................. 19 5.7 TRANSACTION ORDERING ................................................................................................................... 20 5.8 PORT ARBITRATION .............................................................................................................................. 20 5.9 FLOW CONTROL ..................................................................................................................................... 21 5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................. 21 6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS.................................................................. 22 6.1 EEPROM INTERFACE.............................................................................................................................. 22 6.1.1 AUTO MODE EERPOM ACCESS...................................................................................................... 22 6.1.2 EEPROM MODE AT RESET .............................................................................................................. 22 6.1.3 EEPROM SPACE ADDRESS MAP .................................................................................................... 22 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS .......................................... 24 6.2 SMBUS INTERFACE ................................................................................................................................. 29 7 REGISTER DESCRIPTION ............................................................................................................................. 30 7.1 REGISTER TYPES .................................................................................................................................... 30 7.2 TRANSPARENT MODE CONFIGURATION REGISTERS .................................................................... 30 7.2.1 VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 32 7.2.2 DEVICE ID REGISTER – OFFSET 00h ............................................................................................. 32 7.2.3 COMMAND REGISTER – OFFSET 04h ............................................................................................ 32 7.2.4 PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................. 33 7.2.5 REVISION ID REGISTER – OFFSET 08h ......................................................................................... 33 7.2.6 CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 33 7.2.7 CACHE LINE REGISTER – OFFSET 0Ch ......................................................................................... 34 Page 5 of 76 December 2009 – Revision 1.2 Pericom Semiconductor 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 7.2.43 7.2.44 7.2.45 7.2.46 7.2.47 7.2.48 7.2.49 7.2.50 7.2.51 7.2.52 7.2.53 7.2.54 7.2.55 7.2.56 7.2.57 7.2.58 7.2.59 7.2.60 PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 34 HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................................... 34 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 34 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 34 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 34 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 35 I/O BASE ADDRESS REGISTER – OFFSET 1Ch .............................................................................. 35 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ............................................................................. 35 SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 35 MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 36 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 36 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 36 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h .................................... 36 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 37 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 37 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ................................................... 37 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 37 CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 37 INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................. 38 INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 38 BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 38 POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 39 NEXT ITEM POINTER REGISTER – OFFSET 80h ........................................................................... 39 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................................. 39 POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 39 PPB SUPPORT EXTENSIONS – OFFSET 84h .................................................................................. 40 DATA REGISTER – OFFSET 84h ...................................................................................................... 40 MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) .................................... 40 NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) ................................. 41 MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) .................................. 41 MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) .................................... 41 MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ...................... 41 MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ........................................... 41 VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only) ........................................ 41 NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) ...................................... 42 VPD REGISTER – OFFSET 9Ch (Upstream Port Only) .................................................................... 42 VPD DATA REGISTER – OFFSET A0h (Upstream Port Only) ......................................................... 42 VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .................................................. 42 NEXT ITEM POINTER REGISTER – OFFSET A4h .......................................................................... 43 LENGTH REGISTER – OFFSET A4h ................................................................................................ 43 XPIP CSR0 – OFFSET A8h (Test Purpose Only) ............................................................................... 43 XPIP CSR1 – OFFSET ACh (Test Purpose Only) .............................................................................. 43 REPLAY TIME-OUT COUNTER – OFFSET B0h (Upstream Port)................................................... 43 ACKNOWLEDGE LATENCY TIMER – OFFSET B0h ....................................................................... 44 SWITCH OPERATION MODE – OFFSET B4h (Upstream Port) ...................................................... 44 SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) ................................................. 45 XPIP CSR2 – OFFSET B8h (Test Purpose Only) ............................................................................... 46 TL CSR – OFFSET BCh ..................................................................................................................... 46 SSID/SSVID CAPABILITY ID REGISTER – OFFSET C0h ................................................................ 47 NEXT ITEM POINTER REGISTER – OFFSET C0h .......................................................................... 47 SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h .................................................................... 47 SUBSYSTEM ID REGISTER – OFFSET C4h ..................................................................................... 47 GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only) ............................................... 47 Page 6 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.61 EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only) ........................................ 48 7.2.62 EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only) ......................................... 49 7.2.63 EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only) ................................................ 49 7.2.64 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................ 49 7.2.65 NEXT ITEM POINTER REGISTER – OFFSET E0h .......................................................................... 50 7.2.66 PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .............................................................. 50 7.2.67 DEVICE CAPABILITIES REGISTER – OFFSET E4h ....................................................................... 50 7.2.68 DEVICE CONTROL REGISTER – OFFSET E8h............................................................................... 51 7.2.69 DEVICE STATUS REGISTER – OFFSET E8h ................................................................................... 52 7.2.70 LINK CAPABILITIES REGISTER – OFFSET ECh ............................................................................ 52 7.2.71 LINK CONTROL REGISTER – OFFSET F0h .................................................................................... 53 7.2.72 LINK STATUS REGISTER – OFFSET F0h ........................................................................................ 54 7.2.73 SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h ................................... 54 7.2.74 SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h ........................................... 55 7.2.75 SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h ............................................... 56 7.2.76 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h . 57 7.2.77 CAPABILITY VERSION – OFFSET 100h .......................................................................................... 57 7.2.78 NEXT ITEM POINTER REGISTER – OFFSET 100h ......................................................................... 57 7.2.79 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 57 7.2.80 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 58 7.2.81 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................. 59 7.2.82 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ...................................................... 60 7.2.83 CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ......................................................... 60 7.2.84 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ......................... 61 7.2.85 HEADER LOG REGISTER – OFFSET From 11Ch to 128h .............................................................. 61 7.2.86 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h (Upstream Only) 61 7.2.87 CAPABILITY VERSION – OFFSET 140h (Upstream Only) .............................................................. 61 7.2.88 NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only) ............................................. 62 7.2.89 PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only) ........................................ 62 7.2.90 PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only) ........................................ 62 7.2.91 PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)............................................... 62 7.2.92 PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only) ................................................... 63 7.2.93 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream Only) ............................ 63 7.2.94 VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream Only) .............................. 63 7.2.95 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only) .................................... 64 7.2.96 PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh (Upstream Only) .................. 64 7.2.97 PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch .................... 65 7.2.98 CAPABILITY VERSION – OFFSET 20Ch .......................................................................................... 65 7.2.99 NEXT ITEM POINTER REGISTER – OFFSET 20Ch ........................................................................ 65 7.2.100 DATA SELECT REGISTER – OFFSET 210h ................................................................................. 65 7.2.101 POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 65 7.2.102 POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 66 8 CLOCK SCHEME ............................................................................................................................................. 67 9 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................................... 68 9.1 9.2 9.3 9.4 9.5 INSTRUCTION REGISTER ...................................................................................................................... 68 BYPASS REGISTER ................................................................................................................................. 68 DEVICE ID REGISTER ............................................................................................................................. 68 BOUNDARY SCAN REGISTER ............................................................................................................... 69 JTAG BOUNDARY SCAN REGISTER ORDER ...................................................................................... 69 10 POWER MANAGEMENT ................................................................................................................................ 71 Page 7 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 11 ELECTRICAL AND TIMING SPECIFICATIONS ....................................................................................... 72 11.1 11.2 11.3 11.4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 72 POWER CONSUMPTION ......................................................................................................................... 72 DC SPECIFICATIONS .............................................................................................................................. 72 AC SPECIFICATIONS .............................................................................................................................. 73 12 PACKAGE INFORMATION............................................................................................................................ 75 13 ORDERING INFORMATION.......................................................................................................................... 76 Page 8 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet TABLE OF FIGURES FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X20303SL ............................................................ 29 FIGURE 12-1 PACKAGE OUTLINE DRAWING ................................................................................................................. 75 LIST OF TABLES TABLE 5-1 NOMINAL DRIVER CURRENT VALUES (INOM)............................................................................................ 16 TABLE 5-2 RATIO OF ACTUAL CURRENT AND NOMINAL CURRENT ............................................................................. 16 TABLE 5-3 DE-EMPHASIS LEVEL VERSUS DEQ [3:0] ................................................................................................... 17 TABLE 5-4 SUMMARY OF PCI EXPRESS ORDERING RULES .......................................................................................... 20 TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION .................................................................................................... 29 TABLE 7-1 TABLE ENTRY SIZE IN 4 BITS ..................................................................................................................... 64 TABLE 8-1 INPUT CLOCK REQUIREMENTS ................................................................................................................... 67 TABLE 9-1 INSTRUCTION REGISTER CODES .................................................................................................................. 68 TABLE 9-2 JTAG DEVICE ID REGISTER ....................................................................................................................... 68 TABLE 9-3 JTAG BOUNDARY SCAN REGISTER DEFINITION .......................................................................................... 69 TABLE 11-1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 72 TABLE 11-2 PI7C9X303SL POWER DISSIPATION ......................................................................................................... 72 TABLE 11-3 DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 72 TABLE 11-4 TRANSMITTER CHARACTERISTICS............................................................................................................ 73 TABLE 11-5 RECEIVER CHARACTERISTICS .................................................................................................................. 74 Page 9 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 1 Features                      3-lane PCI Express Switch with 3 PCI Express ports Non-blocking full-wired switching capability at 12 Gbps when all 3 ports are enabled Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching 150 ns typical latency for packet routed through Switch without blocking Strapped pins configurable with optional EEPROM or SMBus SMBus interface support Compliant with System Management (SM) Bus, Version 1.0 Compliant with PCI Express Base Specification Revision 1.1 Compliant with PCI Express CEM Specification Revision 1.1 Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Compliant with Advanced Configuration Power Interface (ACPI) Specification Reliability, Availability and Serviceability - Supports Data Poisoning and End-to-End CRC - Advanced Error Reporting and Logging - IEEE 1149.6 JTAG interface support Advanced Power Saving - Empty downstream ports are set to idle state to minimize power consumption Link Power Management - Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states - Active state power management for L0s and L1 states - Beacon or Wake# support in L2 state Device State Power Management - Supports D0, D3Hot and D3Cold device power states - 3.3V Aux Power support in D3Cold power state Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Supports up to 256-byte maximum payload size Programmable driver current and de-emphasis level at each individual port Low Power Dissipation at 360 mW typical in L0 normal mode, 210 mW typical in L1 standby mode Industrial Temperature Range -40o to 85oC 128-pin LQFP 14mm x 14mm package Page 10 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 2 GENERAL DESCRIPTION Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect architecture. The 3-lane PCIE Switch can be configured as 3-port type combinations. It provides users the flexibility to expand or fan-out the PCI Express lanes based on their application needs. For some systems that do not need all the 3 lanes, the unused lanes can be disabled to reduce power consumption. In the PCI Express Architecture, the PCIE Switch forwards posted and non-posted requests and completion packets in either downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port. By visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge during enumeration, each port is given a unique bus number, device number, and function number by the initiating software. The bus number, device number, and function number are combined to form a destination ID for each specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the packets to multiple small packets or merge the received packets into a large transmit packet. Also, the IDs of the requesters and completers are kept unchanged along the path between ingress and egress port. The Switch employs the architecture of Combined Input and Output Queue (CIOQ) in implementation. The main reason for choosing CIOQ is that the required memory bandwidth of input queue equals to the bandwidth of ingress port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at each ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port based on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass over each other in case that the addressed egress port is available to accept them. As to the packets required to follow the ordering rule, the Head-Of-Line (HOL) issue becomes unavoidable for packets destined to different egress ports since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it out. This can assure the maximum throughput being achieved and therefore the Switch works efficiently. Another advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified and streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port maintains the credits independently without checking other ports' credit availability, which is otherwise required by pure output queue architecture. Page 11 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 3 PIN DESCRIPTION 3.1 PCI EXPRESS INTERFACE SIGNALS NAME REFCLKP REFCLKN 3.2 3.3 PIN 91 93 TYPE I DESCRIPTION Reference Clock Input Pairs: Connect to external 100MHz differential clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. It is recommended that a 0.1uF be used in the AC-coupling. PCI Express Data Serial Input Pairs: Differential data receive signals in three ports. PERP [2:0] 104, 87, 70 I PERN [2:0] 103, 88, 69 I PETP [2:0] 107, 84, 73 O PCI Express Data Serial Output Pairs: Differential data transmit signals in three ports. PETN [2:0] 108, 83, 74 O WAKEUP_L 6 I PERST_L 43 I DWNRST_L [2:1] 97, 96 O Port 0 (Upstream Port) is PETP[0] and PETN[0] Port 1 (Downstream Port) is PETP[1] and PETN[1] Port 2 (Downstream Port) is PETP[2] and PETN[2] Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the upstream port has to generate a Beacon that is propagated to the Root Complex/Power Management Controller. Pin has an internal pull-up. System Reset (Active LOW): When PERST_L is asserted, the internal states of whole chip except sticky logics are initialized. Downstream Device Reset (Active LOW): It provides a reset signal to the devices connected to the downstream ports of Switch. The signal is active when either PERST_L is asserted or the device is just plugged into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2. Port 0 (Upstream Port) is PERP[0] and PERN[0] Port 1 (Downstream Port) is PERP[1] and PERN[1] Port 2 (Downstream Port) is PERP[2] and PERN[2] PORT CONFIGURATION SIGNALS NAME PRSNT [2:1] PIN 7, 128 SLOTCLK 127 TYPE I I DESCRIPTION Present: When asserted low, it represents the device is present in the slot of downstream ports. Otherwise, it represents the absence of the device. PRSNT [x] is correspondent to Port x, where x=1,2. The pins have internal pull-down. Slot Clock Configuration: It determines if the downstream component uses the same physical reference clock that the platform provides on the connector. When SLOTCLK is high, the platform reference clock is employed. By default, all downstream ports use the same physical reference clock provided by platform. The pin has internal pull-down. MISCELLANEOUS SIGNALS NAME EECLK EEPD 40 41 PIN TYPE O I/O SMBCLK 13 I SMBDATA 16 I/O DESCRIPTION EEPROM Clock: Clock signal to the EEPROM interface. EEPROM Data: Bi-directional serial data interface to and from the EEPROM. The pin has internal pull-up. SMBus Clock: System management Bus Clock. The pin has internal pull-up. SMBus Data: Bi-directional System Management Bus Data. The pin has internal pull-up. Page 12 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 3.4 NAME SCAN_EN 56 PIN TYPE I/O PORTERR [2:0] 51, 47, 45 O GPIO [7:0] 28, 27, 26, 25, 24, 23, 22, 21 I/O PWR_SAV 17 I P0_CTCDIS P1_CTCDIS P2_CTCDIS TEST1/3/4/5/6/7 18 32 33 31, 12, 11, 10, 126, 38 I TEST2 66 I NC 9, 54, 98, 116, 117, 120, 121 DESCRIPTION Full-Scan Enable Control: For normal operation, SCAN_EN is an output with a value of “0”. SCAN_EN becomes an input during manufacturing testing. Port PHY Error Status: These pins are used to display the PHY Error status of the ports. When PORTERR is flashing (alternating high and low signals), it indicates that a PHY error is detected. When it is low, no PHY error is detected. PORTERR [x] is correspondent to Port x, where x=0,1,2. General Purpose Input and Output: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. When SMBus is implemented, GPIO[7:5] act as the SMBus address pins, which set Bit 2 to 0 of the SMBus address. Power Saving Mode: PWR_SAV is a strapping pin. When this pin is pulled high when system is reset, the Power Saving Mode is enabled. When this pin is pulled low when system is reset, the Power Saving Mode is disabled. When this pin is pulled low, it should be tied to ground through a pull-down resistor. When this pin is pulled high, a pull-up resistor should be used. The suggested value for the pull-up and pull-down resistor is 5.1K. Pin has an internal pull-down. P0/P1/P2 CTC Disable: These pins should be tied to ground through a pull-down resistor. The suggested value for the pull-down resistor is 5.1K. The pins have internal pull-down. Test1/3/4/5/6/7: These pins are for internal test purpose. Test1/3/4/5/6/7 should be tied to ground through a pull-down resistor. The suggested value for the pull-down resistor is 5.1K. Test2: This pin is for internal test purpose. Test2 should be tied to 3.3V through a pull-up resistor. The suggested value for the pull-up resistor is 5.1K. Not Connected: These pins can be left floating. JTAG BOUNDARY SCAN SIGNALS NAME TCK 59 PIN TYPE I TMS 63 I TDO 58 O TDI 64 I TRST_L 65 I DESCRIPTION Test Clock: Used to clock state information and data into and out of the chip during boundary scan. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Mode Select: Used to control the state of the Test Access Port controller. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 5.1K pull-down resistor. Test Data Output: When SCAN_EN is high, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Data Input: When SCAN_EN is high, it is used (in conjunction with TCK) to shift data and instructions into the TAP in a serial bit stream. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Reset (Active LOW): Active LOW signal to reset the TAP controller into an initialized state. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 5.1K pull-down resistor. Page 13 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 3.5 POWER PINS NAME VDDC VDDR VDDA VDDAUX VAUX VTT VSS PIN 1, 15, 29, 37, 42, 46, 49, 52, 61, 72, 85, 101, 106, 118, 123 8, 20, 35, 39, 48, 55, 99, 124 78, 79, 80, 92, 112, 113 4, 76, 110 5 75, 82, 109, 115 TYPE P DESCRIPTION VDDC Supply (1.0V): Used as digital core power pins. P VDDR Supply (3.3V): Used as digital I/O power pins. P VDDA Supply (1.0V): Used as analog power pins. P P P 2, 3, 14, 19, 30, 34, 36, 44, 50, 53, 57, 60, 62, 67, 68, 71, 77, 81, 86, 89, 90, 94, 95, 100, 102, 105, 111, 114, 119, 122, 125 P VDDAUX Supply (1.0V): Used as auxiliary core power pins. VAUX Supply (3.3V): Used as auxiliary I/O power pins. Transmit Termination Voltage (1.5V): Provides driver termination voltage at transmitter. Should be given the same consideration as VDDAUX. VSS Ground: Used as ground pins. Page 14 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 4 PIN ASSIGNMENTS 4.1 PIN LIST of 128-PIN LQFP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME VDDC VSS VSS VDDAUX VAUX WAKEUP_L PRSNT[2] VDDR NC TEST5 TEST4 TEST3 SMBCLK VSS VDDC SMBDATA PWR_SAV P0_CTCDIS VSS VDDR GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] VDDC VSS TEST1 P1_CTCDIS PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME P2_CTCDIS VSS VDDR VSS VDDC TEST7 VDDR EECLK EEPD VDDC PERST_L VSS PORTERR[0] VDDC PORTERR[1] VDDR VDDC VSS PORTERR[2] VDDC VSS NC VDDR SCAN_EN VSS TDO TCK VSS VDDC VSS TMS TDI PIN 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Page 15 of 76 December 2009 – Revision 1.2 Pericom Semiconductor NAME TRST_L TEST2 VSS VSS PERN[0] PERP[0] VSS VDDC PETP[0] PETN[0] VTT VDDAUX VSS VDDA VDDA VDDA VSS VTT PETN[1] PETP[1] VDDC VSS PERP[1] PERN[1] VSS VSS REFCLKP VDDA REFCLKN VSS VSS DWNRST_L[1] PIN 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME DWNRST_L[2] NC VDDR VSS VDDC VSS PERN[2] PERP[2] VSS VDDC PETP[2] PETN[2] VTT VDDAUX VSS VDDA VDDA VSS VTT NC NC VDDC VSS NC NC VSS VDDC VDDR VSS TEST6 SLOTCLK PRSNT[1] PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 5 FUNCTIONAL DESCRIPTION Multiple virtual PCI-to-PCI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB contains the complete PCIe architecture layers that consist of the physical, data link, and transaction layer. The packets entering the Switch via one of VPPBs are first converted from serial bit-stream into parallel bus signals in physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to extract out the transaction header. According to the address or ID embedded in the transaction header, the entire transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the transmit circuits in the data link layer and physical layer. The following sections describe these function elements for processing PCIe packets within the Switch. 5.1 PHYSICAL LAYER CIRCUIT The physical layer circuit design is based on the PHY Interface for PCI Express Architecture (PIPE). It contains Physical Media Attachment (PMA) and Physical Coding Sub-layer (PCS) blocks. PMA includes Serializer/ Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, beacon transmitter, electrical idle detector, and input/output buffers. PCS consists of framer, 8B/10B encoder/decoder, receiver elastic buffer, and PIPE PHY control/status circuitries. To provide the flexibility for port configuration, each lane has its own control and status signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for PHY built-in self test. The main functions of physical layer circuits include the conversion between serial-link and parallel bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of physical layer errors. In order to meet the different application needs, the driving current and equalization of each transmitting channels can be adjusted using EEPROM individually. The driver current of each channel is set to 20mA in default mode. To change the current value, the user can program the EEPROM for nominal value (HIDRV, LODRV) or actual value (DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current values the chip provides. Table 5-1 Nominal Driver Current Values (Inom) HIDRV 0 0 1 1 LODRV 0 1 0 1 NOMINAL DRIVER CURENT 20 mA 10 mA 28 mA Reserved Table 5-2 Ratio of Actual Current and Nominal Current DTX [3:0] 0000 0001 0010 0011 0100 0101 0110 1 ACTUAL CURRENT / NOMINAL CURRENT 1.00 1.05 1.10 1.15 1.20 1.25 1.30 Multiple lanes could share the PLL. Page 16 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet ACTUAL CURRENT / NOMINAL CURRENT 1.35 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 DTX [3:0] 0111 1000 1001 1010 1011 1100 1101 1110 1111 The equalization function of transmitting channels can optimize the driver current for different back-plane lengths and materials. The table shown below lists the combinations of de-emphasized driver current (ITX –IEQ) to non-deemphasized driver current (ITX) for different values of DEQ [3:0]. Table 5-3 De-emphasis Level versus DEQ [3:0] (ITX –IEQ) / ITX 1.00 0.96 0.92 0.88 0.84 0.80 0.76 0.72 0.68 0.64 0.60 0.56 0.52 0.48 0.44 0.40 DEQ [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 De-emphasis (dB) 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96 By default, the DEQ is set to “1000” to conform to the PCI Express specification, which calls for a de-emphasis level of between –3 dB and –4 dB. In order to improve the data stream integrity across the channels, the receiver of each port of the Switch includes a reception equalizer to mitigate the effects of ISI. The reception equalizer is implemented as a selectable high-pass filter at the input node, and it is capable of removing as much as 0.4UI of ISI related jitter. The following table shows a simple guideline for selecting the appropriate value to adapt with different lengths or connector numbers in various applications. Table 5-4 Rx Equalizer Settings (RXEQCTL) RXEQCTL [1] 0 RXEQCTL [0] 0 Rx Eq Setting Max Rx Eq Input Jitter > 0.25 UI 0 1 Min Rx Eq 1 X Between 0.1 UI and 0.25 UI < 0.1 UI Page 17 of 76 December 2009 – Revision 1.2 Pericom Semiconductor Channel Length > 20" and two or more connectors Between 8'' and 20" and up to two connectors 8" or less, up to one connector PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 5.2 DATA LINK LAYER (DLL) The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be sent out to acknowledge on reception of a good TLP. In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted after that packet. Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit. All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded by 16-bit CRC to detect if data corruption occurs. In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew, scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is implemented to interface physical layer with data link layer. 5.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) The receiving end of the transaction layer performs header information retrieval and TC/VC mapping (see section 5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain illegal header or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the TLP at the receiver if the digest bit is set in header. 5.4 ROUTING The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing. For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are routed by their destination ID constituted of bus number, device number, and function number. Address routing is employed to forward I/O or memory transactions to the destination port, which is located within the address range indicated by the address field carried in the packet header. The packet header indicates the packet types including memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message. Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power management, and so on. The message type embedded in the packet header determines the routing mechanism. If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI protocol. Page 18 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 5.5 TC/VC MAPPING The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the differential service, a TC/VC mapping table at destination port that is pre-programmed by system software or EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that all the traffic classes are mapped to VC0, since only VC0 is available on the Switch. After the TC/VC mapping, the receive block dispatches the incoming request, completion, or data into the VC0 queues. 5.6 QUEUE In PCI Express, it defines six different packet types to represent request, completion, and data. They are respectively Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted Data Payload (NPD), Completion Header (CPLH) and Completion Data payload (CPLD). Each packet with different type would be put into a separate queue in order to facilitate the following ordering processor. Since NPD usually contains one DW, it can be merged with the corresponding NPH into a common queue named NPHD. 5.6.1 PH PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header space occupies sixteen bytes to accommodate 3 DW or 4 DW headers. 5.6.2 PD PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined to have payload coming with the header, the payload data would be put into PD queue. 5.6.3 NPHD NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data. 5.6.4 CPLH CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to accommodate a 3-DW header. Please note that there is no 4-DW completion headers. 5.6.5 CPLD CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to have payload coming with the header, the payload data would be put into CPLD queue. Page 19 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 5.7 TRANSACTION ORDERING Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering requirement among transactions within different TC labels. Table 5-4 Summary of PCI Express Ordering Rules Row Pass Column Posted Request Read Request Non-posted Write Request Read Completion Non-Posted Write Completion Posted Request Yes/No1 No2 No2 Yes/No3 Yes4 Read Request Yes5 Yes Yes Yes Yes Non-posted Write Request Yes5 Yes Yes Yes Yes Read Completion Yes5 Yes Yes Yes Yes Non-posted Write Completion Yes5 Yes Yes Yes Yes 1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and message request must complete on the egress bus of VPPB in the order in which they are received on the ingress bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted Requests occurring before it. 2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data. Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data. 3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ‘‘pull’’ ahead of previously queued posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory Write or Message Request. 4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction. Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship. 5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write queue and the Non-posted transaction queue. 5.8 PORT ARBITRATION Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC channel. Each port has port arbitration circuitries for traffic handling in VC0. At upstream port, in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the arbitration loop to get the service in Virtual Channel 0. Page 20 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 5.9 FLOW CONTROL PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient. The transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free buffer space to an opposite transmitter to avoid packet stale. In this switch, each port has separate queues for different traffic types and the credits are on the fly sent to data link layer, which compares the current available credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other ingress ports for gating the packet transmission. 5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) The transmit portion of transaction layer performs the following functions. They are to construct the all types of forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e. configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an upstream port. Page 21 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bidirectional serial data). The Switch may control an ISSI IS24C04 or compatible parts using into 512x8 bits. The EEPROM is used to initialize a number of registers before enumeration. This is accomplished after PRST# is deasserted, at which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address input. It can only access the EEPROM with address input set to 0. The System Management Bus interface consists of two pins: SMBCLK (System Management Bus Clock input) and SMBDATA (System Management Bus Data input/ output). 6.1 EEPROM INTERFACE 6.1.1 AUTO MODE EERPOM ACCESS The Switch may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer. The EEPROM start-control, address, and read/write commands can be accessed through the configuration register. Before each access, the software should check the Autoload Status bit before issuing the next start. 6.1.2 EEPROM MODE AT RESET During a reset, the Switch will automatically load the information/data from the EEPROM if the automatic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload initiates right after the reset. During the autoload, the Bridge will read sequential words from the EEPROM and write to the appropriate registers. Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading bit [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0' which indicates that the autoload initialization sequence is complete. 6.1.3 EEPROM SPACE ADDRESS MAP 15 – 8 7–0 EEPROM Signature (1516h) Vendor ID Device ID Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port 1 ~ 2 Subsystem Vender ID Subsystem ID Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm Difference Reserved Revision ID NFTS / Scramble for Port0 NFTS / Scramble for Port1 NFTS / Scramble for Port2 Reserved Reserved Reserved Reserved Page 22 of 76 December 2009 – Revision 1.2 Pericom Semiconductor BYTE OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 15 – 8 7–0 Reserved TC/VC Map for Port 0 (VC0) Slot Clock / LPVC Count / Port Num, Port 0 TC/VC Map for Port 1(VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 1 TC/VC Map for Port 2 (VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 2 Reserved Reserved Reserved Reserved Reserved Reserved Slot Capability 0 for Port 1 Slot Capability 0 for Port 2 Reserved Reserved Reserved Reserved Reserved Reserved Slot Capability 1 for Port 1 Slot Capability 1 for Port 2 Reserved Reserved Reserved Reserved Reserved PM Data for Port 0 PM Capability for Port 0 PM Data for Port 1 PM Capability for Port 1 PM Data for Port 2 PM Capability for Port 2 Reserved Reserved Reserved Reserved Reserved Power Budgeting Capability Register for Port 0 Power Budgeting Capability Register for Port 1 Power Budgeting Capability Register for Port 2 Reserved Reserved Reserved Reserved Reserved Replay Time-out Counter for Port 0 Replay Time-out Counter for Port 1 Replay Time-out Counter for Port 2 Reserved Reserved Reserved Reserved Reserved Acknowledge Latency Timer for Port 0 Acknowledge Latency Timer for Port 1 Acknowledge Latency Timer for Port 2 Reserved Reserved Reserved Reserved Reserved PHY Parameter for Port 0 PHY Parameter for Port 1 PHY Parameter for Port 2 Page 23 of 76 December 2009 – Revision 1.2 Pericom Semiconductor BYTE OFFSET 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 15 – 8 7–0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PM Control Para/Rx Polarity for Port 0 PM Control Para/Rx Polarity for Port 1 PM Control Para/Rx Polarity for Port 2 Reserved BYTE OFFSET 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ADDRESS 00h 02h 04h 06h 08h 0Ah 0Ch PCI CFG OFFSET 00h ~ 01h 02h ~ 03h 144h (Port 0~2) 144h: Bit [0] DESCRIPTION EEPROM signature – 1516h Vendor ID Device ID Extended VC Count for Port 0 ~ 2  Bit [0]: It represents the supported VC count other than the default VC ECh (Port 0~2) ECh: Bit [14:12] ECh: Bit [17:15] Link Capability for Port 0 ~ 2  Bit [3:1]: It represents L0s Exit Latency for all ports  Bit [6:4]: It represents L1 Exit Latency for all ports B4h (Port 0~2) B4h:Bit [5] Bit [6] Bit [0] Bit [2:1] Bit [3] Bit [4] Switch Mode Operation for Port 0  Bit [8]: no ordering on packets for different egress port mode  Bit [9]: no ordering on different tag of completion mode  Bit [10]: Store and Forward  Bit [12:11]: Cut-through Threshold  Bit [13] : Port arbitrator Mode  Bit [14]: Credit Update Mode 3Ch (Port 1~2) 3Ch: Bit [8]] C4h: Bit [15:0] C4h: Bit [31:16] E4h(Port 0~2) E4h: Bit 0 Interrupt pin for Port 1 ~ 2  Bit [15]: Set when INTA is requested for interrupt resource Subsystem Vender ID Subsystem ID Max_Payload_Size Support for Port 0 ~ 2  Bit [0]: Indicated the maximum payload size that the device can support for the TLP ECh(Port 0~2) ECh: Bit[11:10] ASPM Support for Port 0 ~ 2  Bit [2:1] : Indicate the level of ASPM supported on the PCIe link E4h(Port 0~2) E4h: Bit[15] Role_Base Error Reporting for Port 0 ~ 2  Bit [3] : Indicate implement the role-base error reporting B0h(port 0~2) B0h : Bit [14] MSI Capability Disable for Port 0~2  Bit [4] : Disable MSI capability B0h(port 0~2) B0h : Bit [15] AER Capability Disable for Port 0~2  Bit [5] : Disable AER capability B4h(port 0~2) B4h : Bit [15] Compliance Pattern Parity Control Disable for Port 0~2  Bit [6] : Disable compliance pattern parity B0h(port 0~2) B0h : Bit [13] Power Management Capability Disable for Port 0~2  Bit [7] : Disable Power Management Capability B4h(Port 0~2) B4h: Bit [7] Ordering Frozen for Port 0~2  Bit [10]: Freeze the ordering feature BCh(Port 0~2) TX SOF Latency Mode for Port 0~2 Page 24 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet ADDRESS 0Eh 10h 12h 14h 20h PCI CFG OFFSET BCh: Bit[0] DESCRIPTION  Bit [11]: Set to zero to shorten latency ECh(port0~2) ECh : Bit [19] Surprise Down Capability Enable for for Port 0~2  Bit [12]: Enable Surprise Down Capability BCh(Port 0~2) BCh: Bit[1] Power Management’s Data Select Register R/W Capability for Port 0~2  Bit [13]: Enable Data Select Register R/W BCh(Port 0~2) BCh: Bit[2] Flow Control Update Type for Port 0~2  Bit [14]: Select Flow Control Update Type BCh(Port 0~2) BCh: Bit[3] 08h: Bit[7:0] 4KB Boundary Check Enable Bit [15]: Enable 4KB Boundary Check Revision ID  Bit [7:0]: Indicates the Revision ID of chip. FTS Number for Port 0  Bit [7:0]: FTS number at receiver side B8h (port 0) B8h : Bit[7:0] A8h(Port 0) A8h: Bit [14:13] RefClk ppm Difference for Port 0  Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm B8h (port0) B8h : Bit[11:10] B8h : Bit[12] B8h (port 1) B8h : Bit[7:0] Scrambler Control for Port 0  Bit [11:10]: scrambler control  Bit [12]: L0s FTS Number for Port 1  Bit [7:0]: FTS number at receiver side A8h(Port 1) A8h: Bit [14:13] RefClk ppm Difference for Port 1  Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm B8h (port1) B8h : Bit[11:10] B8h : Bit[12] B8h (port 2) B8h : Bit[7:0] Scrambler Control for Port 1  Bit [11:10]: scrambler control  Bit [12]: L0s FTS Number for Port 2  Bit [7:0]: FTS number at receiver side A8h(Port 2) A8h: Bit [14:13] RefClk ppm Difference for Port 2  Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm B8h (port2) B8h : Bit[11:10] B8h : Bit[12] F0h (Port 0) F0h: Bit [28] Scrambler Control for Port 2  Bit [11:10]: scrambler control  Bit [12]: L0s Slot Clock Configuration for Port 0  Bit [1]: When set, the component uses the clock provided on the connector 80h (Port 0) 80h: Bit[21] Device specific Initialization for Port 0  Bit [2]: When set, the DSI is required ECh (Port 0) ECh: Bit [25:24] Port Number for Port 0  Bit [5:4]: It represents the logic port numbering for physical port 0 84h (Port 0) 84h: Bit [14:13] 154h (Port 0) 154h: Bit [7:1] PMCSR Data Scale for Port 0 Bit [7:6]: It represents the PMCSR Data Scale for physical port 0 VC0 TC/VC Map for Port 0  Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 Page 25 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet ADDRESS 22h PCI CFG OFFSET E0h (Port1) E0h: Bit [24] DESCRIPTION PCIe Capability Slot Implemented for Port 1  Bit [0]: When set, the slot is implemented for Port 1 F0h (Port 1) F0h: Bit [28] Slot Clock Configuration for Port 1  Bit [1]: When set, the component uses the clock provided on the Connector 80h (Port 1) 80h: Bit[21] Device specific Initialization for Port 1  Bit [2]: When set, the DSI is required ECh (Port 1) ECh: Bit [25:24] Port Number for Port 1  Bit [5:4]: It represents the logic port numbering for physical port 1 PMCSR Data Scale for Port 1 Bit [7:6]: It represents the PMCSR Data Scale for physical port 1 VC0 TC/VC Map for Port 1  Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 PCIe Capability Slot Implemented for Port 2  Bit [0]: When set, the slot is implemented for Port 2 84h (Port 1) 84h: Bit [14:13] 154h (Port 1) 154h: Bit [7:1] 24h E0h (Port 2) E0h: Bit [24] F0h (Port 2) F0h: Bit [28] Slot Clock Configuration for Port 2  Bit [1]: When set, the component uses the clock provided on the Connector 80h (Port 2) 80h: Bit[21] Device specific Initialization for Port 2  Bit [2]: When set, the DSI is required ECh (Port 2) ECh: Bit [25:24] t Number for Port 2  Bit [5:4]: It represents the logic port numbering for physical port 2 84h (Port 2) 84h: Bit [14:13] 154h (Port 2) 154h: Bit [7:1] 32h 34h 42h 44h 50h F4h (Port 1) F4h: Bit [15:0] F4h (Port 2) F4h: Bit [15:0] F4h (Port 1) F4h: Bit [31:16] F4h (Port 2) F4h: Bit [31:16] 84h (Port 0) 84h: Bit [3] 80h (Port 0) 80h: Bit [24:22] 80h: Bit [25] 80h: Bit [26] 51h 80h: Bit [29:28] 84h (Port 0) 84h: Bit [31:24] VC0 TC/VC Map for Port 2  Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 Slot Capability 0 of Port 1  Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 0 of Port 2  Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 1 of Port 1  Bit [15:0]: Mapping to the high word of slot capability register Slot Capability 1 of Port 2  Bit [15:0]: Mapping to the high word of slot capability register No_Soft_Reset for Port 0  Bit [0]: No_Soft_Reset. Power Management Capability for Port 0  Bit [3:1]: AUX Current.  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 0  Bit [15:8]: read only as Data register Page 26 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet ADDRESS 52h PCI CFG OFFSET 84h (Port 1) 84h: Bit [3] DESCRIPTION No_Soft_Reset for Port 1  Bit [0]: No_Soft_Reset. 80h (Port 1) 80h: Bit [24:22] 80h: Bit [25] Power Management Capability for Port 1  Bit [3:1]: AUX Current.  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 1  Bit [15:8]: read only as Data register No_Soft_Reset for Port 2  Bit [0]: No_Soft_Reset 80h: Bit [26] 53h 54h 80h: Bit [29:28] 84h (Port 1) 84h: Bit [31:24] 84h (Port 2) 84h: Bit [3] 80h (Port 2) 80h: Bit [24:22] 80h: Bit [25] 80h: Bit [26] 55h 60h 62h 64h 70h 72h 74h 80h 82h 84h 90h 92h 94h 80h: Bit [29:28] 84h (Port 2) 84h: Bit [31:24] 214h (Port 0) 214h– Bit [7:0] 214h– Bit [9:8] 214h– Bit [14:13] 218h– Bit [0] 214h (Port 1) 214h– Bit [7:0] 214h– Bit [9:8] 214h– Bit [14:13] 218h– Bit [0] 214h (Port 2) 214h– Bit [7:0] 214h– Bit [9:8] 214h– Bit [14:13] 218h– Bit [0] B0h (Port 0) B0h – Bit [15:0] B0h (Port 1) B0h – Bit [15:0] B0h (Port 2) B0h – Bit [15:0] B0h (Port 0) B0h – Bit [31:16] B0h (Port 1) B0h – Bit [31:16] B0h (Port 2) B0h – Bit [31:16] B4h (Port 0) B4h: Bit [31:16] B4h (Port 1) B4h: Bit [31:16] B4h (Port 2) B4h: Bit [31:16] Power Management Capability for Port 2  Bit [3:1]: AUX Current  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 2  Bit [15:8] – read only as Data register Power Budget Register for Port 0  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Power Budget Register for Port 1  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Power Budget Register for Port 2  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Replay Time-out Counter for Port 0  Bit [15:0]: Relay Time-out Counter Replay Time-out Counter for Port 1  Bit [15:0]: Relay Time-out Counter Replay Time-out Counter for Port 2  Bit [15:0]: Relay Time-out Counter Acknowledge Latency Timer for Port 0  Bit [31:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 1  Bit [31:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 2  Bit [31:16]: Acknowledge Latency Timer PHY Parameter for Port 0  Bit [31:16]: PHY Parameter PHY Parameter for Port 1  Bit [31:16]: PHY Parameter PHY Parameter for Port 2  Bit [31:16]: PHY Parameter Page 27 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet ADDRESS A0h A2h A4h PCI CFG OFFSET B0h (Port0) B0h: Bit[31] DESCRIPTION Decode VGA for Port0  Bit [7] B4h (Port 0) B4h: Bit [13:8] PM Control Parameter for Port 0  Bit [5:4] : L0s enable  Bit [3:2] : L1 delay count select  Bit [1:0] : D3 enters L1 B4h (Port 0) B4h : Bit [14] B0h (Port1) B0h: Bit[31] Rx Polarity Inversion Disable for port 0  Bit [6] : Disable Rx polarity capability Decode VGA for Port1  Bit [7] B4h (Port 1) B4h: Bit [13:8] PM Control Parameter for Port 1  Bit [5:4] : L0s enable  Bit [3:2] : L1 delay count select  Bit [1:0] : D3 enters L1 B4h (Port 1) B4h : Bit [14] B0h (Port2) B0h: Bit[31] Rx Polarity Inversion Disable for port 1  Bit [6] : Disable Rx polarity capability Decode VGA for Port2  Bit [7] B4h (Port 2) B4h: Bit [13:8] PM Control Parameter for Port 2  Bit [5:4] : L0s enable  Bit [3:2] : L1 delay count select  Bit [1:0] : D3 enters L1 B4h (Port 2) B4h : Bit [14] Rx Polarity Inversion Disable for port 2  Bit [6] : Disable Rx polarity capability Page 28 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 6.2 SMBus INTERFACE The PI7C9X20303SL provides the System Management Bus (SMBus), a two-wire interface through which a simple device can communicate with the rest of the system. The SMBus interface on the PI7C9X20303SL is a bidirectional slave interface. It can receive data from the SMBus master or send data to the master. The interface allows full access to the configuration registers. A SMBus master, such as the processor or other SMBus devices, can read or write to every RW configuration register (read/write register). In addition, the RO and HwInt registers (read-only and hardware initialized registers) that can be auto-loaded by the EEPROM interface can also be read and written by the SMBus interface. This feature allows increases in the system expandability and flexibility in system implementation. Figure 6-1 SMBus Architecture Implementation on PI7C9X20303SL Processor (SMBus Master) PI7C9X20303SL Other SMBus Devices SMBCLK SMBDATA The SMBus interface on the PI7C9X20303SL consists of one SMBus clock pin (SMBCLK), a SMBus data pin (SMBDATA), and 3 SMBus address pins (GPIO[5:7]). The SMBus clock pin provides or receives the clock signal. The SMBus data pin facilitates the data transmission and reception. Both of the clock and data pins are bidirectional. The SMBus address pins determine the address to which the PI7C9X20303SL responds to. The SMBus address pins generate addresses according to the following table: Table 6-1 SMBus Address Pin Configuration BIT 0 1 2 3 4 5 6 SMBus Address GPIO[5] GPIO[6] GPIO[7] 1 0 1 1 Page 29 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7 REGISTER DESCRIPTION 7.1 REGISTER TYPES REGISTER TYPE HwInt RO RW RWC RWCS RWS ROS 7.2 DEFINITION Hardware Initialization Read Only Read / Write Read / Write 1 to Clear Sticky - Read Only / Write 1 to Clear Sticky - Read / Write Sticky – Read Only TRANSPARENT MODE CONFIGURATION REGISTERS When the port of switch is set to operate at the transparent mode, it is represented by a logical PCI-toPCI bridge that implements type 1 configuration space header. The following table details the allocation of the register fields of the PCI 2.3 compatible type 1 configuration space header. 31 –24 23 – 16 7 –0 15 - 8 Device ID Primary Status Vendor ID Command Revision ID Primary Latency Timer Cache Line Size Reserved Secondary Latency Subordinate Bus Secondary Bus Number Primary Bus Number Timer Number Secondary Status I/O Limit Address I/O Base Address Memory Limit Address Memory Base Address Prefetchable Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Base Address Upper 32-bit Prefetchable Memory Limit Address Upper 32-bit I/O Limit Address Upper 16-bit I/O Base Address Upper 16-bit Reserved Capability Pointer to 80h Reserved Bridge Control Interrupt Pin Interrupt Line Reserved Power Management Capabilities Next Item Pointer=8C Capability ID=01 PM Data PPB Support Power Management Data Extensions Message Control Next Item Pointer= A4 Capability ID=05 Message Address Message Upper Address Reserved Message Data VPD Register Next Item Pointer=A4 Capability ID=03 VPD Data Register Length in Bytes (14h) Next Item Pointer=C0 Capability ID=09 XPIP_CSR0 XPIP_CSR1 ACK Latency Timer Replay Time-out Counter PHY Parameters Switch Operation Mode XPIP_CSR2 Reserved Reserved Next Item SSID/SSVID Pointer=E0 Capability ID=0D SSID SSVID Reserved Class Code Header Type Page 30 of 76 December 2009 – Revision 1.2 Pericom Semiconductor BYTE OFFSET 00h 04h 08h 0Ch 10h – 17h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h – 7Fh 80h 84h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h 31 –24 23 – 16 15 - 8 PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7 –0 BYTE OFFSET Reserved GPIO Data and Control EEPROM Data EEPROM Address EEPROM Control PCI Express Capabilities Register Next Item Pointer=00 Capability ID=10 Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status Slot Control Reserved C8h – D7h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh Other than the PCI 2.3 compatible configuration space header, the Switch also implements PCI express extended configuration space header, which includes advanced error reporting, virtual channel, and power budgeting capability registers. The following table details the allocation of the register fields of PCI express extended capability space header. The first extended capability always begins at offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginning of PCI compatible configuration space. 31 –24 23 – 16 15 - 8 Next Capability Offset 7 –0 Cap. PCI Express Extended Capability ID=0001h Version Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register Reserved Next Capability Offset=20Ch Cap. PCI Express Extended Capability ID=0002h Version Port VC Capability Register 1 VC Arbitration Table Port VC Capability Register 2 Offset=3 Port VC Status Register Port VC Control Register Port Arbitration Table VC Resource Capability Register (0) Offset=4 VC Resource Control Register (0) VC Resource Status Register (0) Reserved Reserved Port Arbitration Table with 128 Phases for VC0 Reserved Reserved Next Capability Offset=000h Cap. PCI Express Extended Capability ID=0004h Version Reserved Data Select Register Data Register Reserved Power Budget Capability Register Page 31 of 76 December 2009 – Revision 1.2 Pericom Semiconductor BYTE OFFSET 100h 104h 108h 10Ch 110h 114h 118h 11Ch – 128h 12Ch – 13Fh 140h 144h 148h 14Ch 150h 154h 158h 15Ch-17Ch 180h – 1BCh 1C0h – 1FCh 200h – 20Bh 20Ch 210h 214h 218h PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.1 VENDOR ID REGISTER – OFFSET 00h BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 12D8h. 7.2.2 DEVICE ID REGISTER – OFFSET 00h BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies this device as the PI7C9X20303SL. The default value may be changed by SMBus or auto-loading from EEPROM. Resets to A303h. 7.2.3 COMMAND REGISTER – OFFSET 04h BIT FUNCTION 0 I/O Space Enable 1 Memory Space Enable TYPE RW RW 2 Bus Master Enable RW 3 Special Cycle Enable Memory Write And Invalidate Enable VGA Palette Snoop Enable RO 4 5 RO RO 6 Parity Error Response Enable RW 7 Wait Cycle Control RO 8 SERR# enable RW 9 Fast Back-to-Back Enable 10 Interrupt Disable RO RW DESCRIPTION 0b: Ignores I/O transactions on the primary interface 1b: Enables responses to I/O transactions on the primary interface Resets to 0b. 0b: Ignores memory transactions on the primary interface 1b: Enables responses to memory transactions on the primary interface Reset to 0b. 0b: Does not initiate memory or I/O transactions on the upstream port and handles as an Unsupported Request (UR) to memory and I/O transactions on the downstream port. For Non-Posted Requests, a completion with UR completion status must be returned 1b: Enables the Switch Port to forward memory and I/O Read/Write transactions in the upstream direction Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. 0b: Switch may ignore any parity errors that it detects and continue normal operation 1b: Switch must take its normal action when a parity error is detected Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0. 0b: Disables the reporting of Non-fatal and Fatal errors detected by the Switch to the Root Complex b1: Enables the Non-fatal and Fatal error reporting to Root Complex Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Controls the ability of a PCI Express device to generate INTx Interrupt Messages. In the Switch, this bit does not affect the forwarding of INTx messages from the downstream ports. Reset to 0b. Page 32 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT 15:11 7.2.4 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 0b. PRIMARY STATUS REGISTER – OFFSET 04h BIT 18:16 FUNCTION Reserved 19 Interrupt Status RO 20 Capabilities List RO 21 22 66MHz Capable Reserved Fast Back-to-Back Capable RO RO 23 TYPE RO RO DESCRIPTION Reset to 000b. Indicates that an INTx Interrupt Message is pending internally to the device. In the Switch, the forwarding of INTx messages from the downstream device of the Switch port is not reflected in this bit. Must be hardwired to 0b. Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure). Reset to 1b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the primary side of the port in a Switch. 24 Master Data Parity Error RWC 26:25 DEVSEL# timing RO 27 Signaled Target Abort RO 28 29 30 31 Received Target Abort Received Master Abort Signaled System Error Detected Parity Error RO RO RWC RWC If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request on the primary side using the Completer Abort Completion Status. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status on the primary side. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status on primary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Command register is 1. Reset to 0b. Set to 1 whenever the primary side of the port in a Switch receives a Poisoned TLP. Reset to 0b. 7.2.5 REVISION ID REGISTER – OFFSET 08h BIT 7:0 7.2.6 FUNCTION Revision TYPE RO DESCRIPTION Indicates revision number of device. Hardwired to 02h. CLASS CODE REGISTER – OFFSET 08h BIT 15:8 23:16 31:24 FUNCTION Programming Interface Sub-Class Code Base Class Code TYPE RO RO RO DESCRIPTION Read as 00h to indicate no programming interfaces have been defined for PCI-to-PCI Bridges. Read as 04h to indicate device is a PCI-to-PCI Bridge. Read as 06h to indicate device is a Bridge device. Page 33 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.7 CACHE LINE REGISTER – OFFSET 0Ch BIT FUNCTION 7:0 Cache Line Size TYPE RW DESCRIPTION The cache line size register is set by the system firmware and the operating system cache line size. This field is implemented by PCI Express devices as a RW field for legacy compatibility, but it has no impact on any PCI Express device functionality. Reset to 0b. 7.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch BIT 15:8 7.2.9 7.2.10 FUNCTION Primary Latency timer TYPE RO DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. HEADER TYPE REGISTER – OFFSET 0Ch BIT FUNCTION TYPE 23:16 Header Type RO DESCRIPTION Read as 01h to indicate that the register layout conforms to the standard PCIto-PCI Bridge layout. PRIMARY BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTION 7:0 Primary Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 00h. 7.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTION 15:8 Secondary Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus to which the secondary interface is connected. The value is set in software during configuration. Reset to 00h. 7.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTION 23:16 Subordinate Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus with the highest number that is subordinate to the Bridge. The value is set in software during configuration. Reset to 00h. Page 34 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h BIT 31:24 7.2.14 FUNCTION Secondary Latency Timer TYPE RO DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. I/O BASE ADDRESS REGISTER – OFFSET 1Ch BIT 3:0 FUNCTION 32-bit Indicator 7:4 I/O Base Address [15:12] TYPE RO RW DESCRIPTION Read as 01h to indicate 32-bit I/O addressing. Defines the bottom address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register. Reset to 0h. 7.2.15 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch BIT 11:8 FUNCTION 32-bit Indicator 15:12 I/O Limit Address [15:12] TYPE RO RW DESCRIPTION Read as 01h to indicate 32-bit I/O addressing. Defines the top address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit address upper 16 bits address register. Reset to 0h. 7.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch BIT 20:16 21 22 23 FUNCTION Reserved 66MHz Capable Reserved Fast Back-to-Back Capable TYPE RO RO RO RO DESCRIPTION Reset to 00000b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the secondary side of the port in a Switch. 24 Master Data Parity Error RWC 26:25 DEVSEL_L timing RO 27 Signaled Target Abort RO 28 Received Target Abort RO If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request in the secondary side using Completer Abort Completion Status. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status in the secondary side. Reset to 0b. Page 35 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 29 Received Master Abort 30 31 Received System Error Detected Parity Error TYPE RO RWC RWC DESCRIPTION Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status in secondary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Bridge Control register is 1. Reset to 0b. Set to 1 whenever the secondary side of the port in a Switch receives a Poisoned TLP. Reset to 0b. 7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h BIT 3:0 FUNCTION Reserved 15:4 Memory Base Address [15:4] TYPE RO RW DESCRIPTION Reset to 0h. Defines the bottom address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are able to be written to. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 000h. 7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h BIT 19:16 FUNCTION Reserved 31:20 Memory Limit Address [31:20] TYPE RO RW DESCRIPTION Reset to 0h. Defines the top address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh. Reset to 000h. 7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h BIT 3:0 FUNCTION 64-bit addressing 15:4 Prefetchable Memory Base Address [31:20] TYPE RO RW DESCRIPTION Read as 0001b to indicate 64-bit addressing. Defines the bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0. The memory base register upper 32 bits contain the upper half of the base address. Reset to 000h. 7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h BIT 19:16 FUNCTION 64-bit addressing TYPE RO DESCRIPTION Read as 0001b to indicate 64-bit addressing. Page 36 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 31:20 Prefetchable Memory Limit Address [31:20] TYPE RW DESCRIPTION Defines the top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits register contains the upper half of the limit address. Reset to 000h. 7.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h BIT FUNCTION 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] TYPE RW DESCRIPTION Defines the upper 32-bits of a 64-bit bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 00000000h. 7.2.22 7.2.23 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch BIT FUNCTION 31:0 Prefetchable Memory Limit Address, Upper 32-bits [63:32] TYPE RW DESCRIPTION Defines the upper 32-bits of a 64-bit top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 00000000h. I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h BIT FUNCTION 15:0 I/O Base Address, Upper 16-bits [31:16] TYPE RW DESCRIPTION Defines the upper 16-bits of a 32-bit bottom address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. 7.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h BIT FUNCTION 31:16 I/O Limit Address, Upper 16-bits [31:16] TYPE RW DESCRIPTION Defines the upper 16-bits of a 32-bit top address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. 7.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h BIT FUNCTION 7:0 Capability Pointer TYPE RO DESCRIPTION Pointer points to the PCI power management registers (80h). Page 37 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT 7.2.26 TYPE DESCRIPTION Reset to 80h. INTERRUPT LINE REGISTER – OFFSET 3Ch BIT 7:0 7.2.27 FUNCTION FUNCTION Interrupt Line TYPE RW DESCRIPTION Reset to 00h. INTERRUPT PIN REGISTER – OFFSET 3Ch BIT FUNCTION TYPE 15:8 Interrupt Pin RO DESCRIPTION The Switch implements INTA virtual wire interrupt signals to represent hotplug events at downstream ports. The default value on the downstream ports may be changed by SMBus or auto-loading from EEPROM. Reset to 00h. 7.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch BIT FUNCTION 16 Parity Error Response 17 18 S_SERR# enable ISA Enable TYPE RW RW RW DESCRIPTION 0b: Ignore Poisoned TLPs on the secondary interface 1b: Enable the Poisoned TLPs reporting and detection on the secondary interface Reset to 0b. 0b: Disables the forwarding of EER_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary interface 1b: Enables the forwarding of EER_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary interface Reset to 0b. 0b: Forwards downstream all I/O addresses in the address range defined by the I/O Base, I/O Base, and Limit registers 1b: Forwards upstream all I/O addresses in the address range defined by the I/O Base and Limit registers that are in the first 64KB of PCI I/O address space (top 768 bytes of each 1KB block) Reset to 0b. 0: Ignores access to the VGA memory or IO address range 1: Forwards transactions targeted at the VGA memory or IO address range 19 VGA Enable RW 20 VGA 16-bit decode RW 21 Master Abort Mode RO 22 Secondary Bus Reset RW VGA memory range starts from 000A 0000h to 000B FFFFh VGA IO addresses are in the first 64KB of IO address space. AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh. Reset to 0b. Please note that this bit is reserved in Port 2. 0b: Executes 10-bit address decoding on VGA I/O accesses 1b: Executes 16-bit address decoding on VGA I/O accesses Reset to 0b. Please note that this bit is reserved in Port 2. Does not apply to PCI Express. Must be hardwired to 0b. 0b: Does not trigger a hot reset on the corresponding PCI Express Port 1b: Triggers a hot reset on the corresponding PCI Express Port At the downstream port, it asserts PORT_RST# to the attached downstream device. At the upstream port, it asserts the PORT_RST# at all the downstream ports. Reset to 0b. Page 38 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT 23 24 25 26 27 31:28 7.2.29 TYPE RO RO RO RO RO RO DESCRIPTION Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0h. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h BIT 7:0 7.2.30 FUNCTION Fast Back-to-Back Enable Primary Master Timeout Secondary Master Timeout Master Timeout Status Discard Timer SERR# enable Reserved FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 01h to indicate that these are power management enhanced capability registers. NEXT ITEM POINTER REGISTER – OFFSET 80h BIT FUNCTION 15:8 Next Item Pointer TYPE RO DESCRIPTION At upstream ports, the pointer points to the Vital Protocol Data (VPD) capability register (9Ch). At downstream ports, the pointer points to the Message capability register (8Ch). Reset to 9Ch (Upstream port). Reset to 8Ch (Downstream port). 7.2.31 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h BIT 18:16 19 20 TYPE RO RO RO 21 Device Specific Initialization RO 24:22 AUX Current RO 25 26 31:27 7.2.32 FUNCTION Power Management Revision PME# Clock Reserved D1 Power State Support D2 Power State Support PME# Support RO RO RO DESCRIPTION Read as 011b to indicate the device is compliant to Revision 1.2 of PCI Power Management Interface Specifications. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Read as 0b to indicate Switch does not have device specific initialization requirements. The default value may be changed by SMBus or auto-loading from EEPROM. Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 1b to indicate Switch supports the D1 power management state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 1b to indicate Switch supports the D2 power management state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 11111b to indicate Switch supports the forwarding of PME# message in all power states. The default value may be changed by SMBus or autoloading from EEPROM. POWER MANAGEMENT DATA REGISTER – OFFSET 84h BIT FUNCTION TYPE 1:0 Power State RW DESCRIPTION Indicates the current power state of the Switch. Writing a value of D0 when the previous state was D3 cause a hot reset without asserting DWNRST_L. Page 39 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.33 BIT FUNCTION 2 Reserved RO 3 No_Soft_Reset RO 7:4 8 Reserved PME# Enable RO RWS 12:9 Data Select RW 14:13 15 Data Scale PME status RO ROS DESCRIPTION 00b: D0 state 01b: D1 state 10b: D2 state 11b: D3 hot state Reset to 00b. Reset to 0b. When set, this bit indicates that device transitioning from D3hot to D0 does not perform an internal reset. When clear, an internal reset is performed when power state transits from D3hot to D0. This bit can be rewritten with EEPROM programming. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1b. Reset to 0b. When asserted, the Switch will generate the PME# message. Reset to 0b. Select data registers. Reset to 0h. Reset to 00b. Read as 0b as the PME# message is not implemented. PPB SUPPORT EXTENSIONS – OFFSET 84h BIT 21:16 22 23 7.2.34 TYPE FUNCTION Reserved B2_B3 Support for D3HOT Bus Power / Clock Control Enable TYPE RO RO RO DESCRIPTION Reset to 000000b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. DATA REGISTER – OFFSET 84h BIT FUNCTION TYPE 31:24 Data Register RO DESCRIPTION Data Register. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. 7.2.35 MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 05h to indicate that this is message signal interrupt capability register. Page 40 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.36 NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION Pointer points to the Vendor specific capability register (A4h). RO Reset to A4h. 7.2.37 MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) BIT FUNCTION TYPE 16 MSI Enable RW 19:17 22:20 7.2.38 Multiple Message Capable Multiple Message Enable RO RW 23 64-bit address capable RO 31:24 Reserved RO DESCRIPTION 0b: The function is prohibited from using MSI to request service 1b: The function is permitted to use MSI to request service and is prohibited from using its INTx # pin Reset to 0b. Read as 000b. Reset to 000b. 0b: The function is not capable of generating a 64-bit message address 1b: The function is capable of generating a 64-bit message address Reset to 1b. Reset to 00h. MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) BIT 1:0 FUNCTION Reserved TYPE RO 31:2 Message Address RW DESCRIPTION Reset to 00b. If the message enable bit is set, the contents of this register specify the DWORD aligned address for MSI memory write transaction. Reset to 0. 7.2.39 MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) BIT FUNCTION 31:0 Message Upper Address TYPE RW DESCRIPTION This register is only effective if the device supports a 64-bit message address is set. Reset to 00000000h. 7.2.40 MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) BIT 15:0 7.2.41 FUNCTION Message Data TYPE RW DESCRIPTION Reset to 0000h. VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only) Page 41 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.42 BIT FUNCTION 7:0 Enhanced Capabilities ID TYPE DESCRIPTION Read as 03h to indicate that these are VPD enhanced capability registers. RO Reset to 03h. NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION Pointer points to the Vendor specific capability register (A4h). RO Reset to A4h. 7.2.43 VPD REGISTER – OFFSET 9Ch (Upstream Port Only) BIT 17:16 FUNCTION Reserved TYPE RO 23:18 VPD Address RW 30:24 Reserved RO 31 VPD operation RW DESCRIPTION Reset to 00b. Contains DWORD address that is used to generate read or write cycle to the VPD table stored in EEPROM. Reset to 000000b. Reset to 0000000b. 0b: Performs VPD read command to VPD table at the location as specified in VPD address. This bit is kept ‘0’ and then set to ‘1’ automatically after EEPROM cycle is finished 1b: Performs VPD write command to VPD table at the location as specified in VPD address. This bit is kept ‘1’ and then set to ‘0’ automatically after EEPROM cycle is finished. Reset to 0b. 7.2.44 VPD DATA REGISTER – OFFSET A0h (Upstream Port Only) BIT FUNCTION 31:0 VPD Data TYPE DESCRIPTION When read, it returns the last data read from VPD table at the location as specified in VPD Address. RW When written, it places the current data into VPD table at the location as specified in VPD Address. 7.2.45 VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h BIT FUNCTION 7:0 Enhanced Capabilities ID TYPE DESCRIPTION Read as 09h to indicate that these are vendor specific capability registers. RO Reset to 09h. Page 42 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.46 NEXT ITEM POINTER REGISTER – OFFSET A4h BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION Pointer points to the SSID/SSVID capability register (C0h). RO Reset to C0h. 7.2.47 LENGTH REGISTER – OFFSET A4h BIT FUNCTION 31:16 Length Information TYPE RO DESCRIPTION The length field provides the information for number of bytes in the capability structure (including the ID and Next pointer bytes). Reset to 000Ch. 7.2.48 XPIP CSR0 – OFFSET A8h (Test Purpose Only) BIT 31:0 7.2.49 TYPE RW DESCRIPTION Reset to 04001060h. XPIP CSR1 – OFFSET ACh (Test Purpose Only) BIT 31:0 7.2.50 FUNCTION Reserved FUNCTION Reserved TYPE RW DESCRIPTION Reset to 04000800h. REPLAY TIME-OUT COUNTER – OFFSET B0h (Upstream Port) BIT FUNCTION 11:0 User Replay Timer 12 13 14 15 Enable User Replay Timer Power Management Capability Disable MSI Capability Disable AER Capability Disable TYPE RW RW RO RO RO DESCRIPTION A 12-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000h. When asserted, the user-defined replay time-out value is be employed. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Page 43 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.51 ACKNOWLEDGE LATENCY TIMER – OFFSET B0h BIT FUNCTION 29:16 User ACK Latency Timer 30 31 Enable User ACK Latency VGA Capability Enable TYPE RW RW RO DESCRIPTION A 14-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0. When asserted, the user-defined ACK latency value is be employed. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When asserted, the VGA Capability is enabled. The value may be changed by auto-loading from EEPROM. Reset to 1b. 7.2.52 SWITCH OPERATION MODE – OFFSET B4h (Upstream Port) BIT FUNCTION TYPE 0 Store-Forward RW DESCRIPTION When set, a store-forward mode is used. Otherwise, the chip is working under cut-through mode. The default value may be changed by SMBus or autoloading from EEPROM. Reset to 0b. Cut-through Threshold. When forwarding a packet from low-speed port to high-speed mode, the chip provides the capability to adjust the forwarding threshold. The default value may be changed by SMBus or auto-loading from EEPROM. 2:1 3 4 Cut-through Threshold Port Arbitration Mode Credit Update Mode RW RW RW 00b: the threshold is set at the middle of forwarding packet 01b: the threshold is set ahead 1-cycle of middle point 10b: the threshold is set ahead 2-cycle of middle point. 11b: the threshold is set ahead 3-cycle of middle point. Reset to 01b. When set, the round-robin arbitration will stay in the arbitrated port even if the credit is not enough but request is pending. When clear, the round-robin arbitration will always go to the requesting port, which the outgoing credit is enough for the packet queued in the port. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When set, the frequency of releasing new credit to the link partner will be one credit per update. When clear, the frequency of releasing new credit to the link partner will be two credits per update. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When set, there has ordering rule on packets for different egress port. The default value may be changed by SMBus or auto-loading from EEPROM. Ordering on Different Egress Port Mode RW 6 Ordering on Different Tag of Completion Mode RW Reset to 0b. When set, there has ordering rule between completion packet with different tag. The default value may be changed by SMBus or auto-loading from EEPROM. 7 Reserved RO Reset to 0b. Reset to 0. 5 Page 44 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 13:8 Power management Control parameter 14 15 16 17 RX Polarity Inversion Disable TYPE RW RO Compliance pattern Parity Control Disable RO Low Driver Current RO High Driver Current RO 21:18 Driver Transmit Current 25:22 De-emphasis Transmit Equalization RO Receive Termination Adjustment RO 27:26 RO DESCRIPTION The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000001b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Low Driver Current (LODRV). The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. High Driver Current (HIDRV). The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Driver Transmit Current (DTX[3:0]). The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000b. De-emphasis Transmit Equalization (DEQ[3:0]). The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1000b. Receive Termination Adjustment (RXTRMADJ[1:0]). The default value may be changed by SMBus or auto-loading from EEPROM. 00: Receive Termination impedance value is set to 50 ohm 01: Receive Termination impedance value is set to 41.5 ohm 10: Receive Termination impedance value is set to 55 ohm 11: Receive Termination impedance value is set to 42.5 ohm Reset to 00b. Transmit Termination Adjustment ( TXTRMADJ[1:0]). The default value may be changed by SMBus or auto-loading from EEPROM. 7.2.53 29:28 Transmit Termination Adjustment 31:30 Receiver Equalization Level Control RO RO 00: Transmit Termination impedance value is set to 50 ohm 01: Transmit Termination impedance value is set to 41.5 ohm 10: Transmit Termination impedance value is set to 55 ohm 11: Transmit Termination impedance value is set to 42.5 ohm Reset to 00b. Receiver Equalization Level Control (RXEQCTL[1:0]). The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00b. SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) BIT 7:0 FUNCTION Reserved TYPE RO 13:8 Power Management Control Parameter RW DESCRIPTION Reset to 0. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000001b. Page 45 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION TYPE 14 RX Polarity Inversion Disable RW 15 16 17 21:18 25:22 27:26 Compliance Pattern Parity Control Disable RW Low Driver Current RO High Driver Current Driver Transmit Current RO RO De-emphasis Transmit Equalization RO Receive Termination Adjustment RO DESCRIPTION The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. It indicates the status of the strapping pin LODRV. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. It indicates the status of the strapping pin HIDRV. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. It indicates the status of the strapping pins DTX[3:0]. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000b. It indicates the status of the strapping pins DEQ[3:0]. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1000b. It indicates the status of the strapping pins RXTRMADJ[1:0]. The default value may be changed by SMBus or auto-loading from EEPROM. 00: Receive Termination impedance value is set to 50 ohm 01: Receive Termination impedance value is set to 41.5 ohm 10: Receive Termination impedance value is set to 55 ohm 11: Receive Termination impedance value is set to 42.5 ohm Reset to 00b. It indicates the status of the strapping pins TXTRMADJ[1:0]. The default value may be changed by SMBus or auto-loading from EEPROM. 29:28 31:30 7.2.54 Receiver Equalization Level Control RO RO 00: Transmit Termination impedance value is set to 50 ohm 01: Transmit Termination impedance value is set to 41.5 ohm 10: Transmit Termination impedance value is set to 55 ohm 11: Transmit Termination impedance value is set to 42.5 ohm Reset to 00b. It indicates the status of the strapping pins RXEQCTL[1:0]. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00b. XPIP CSR2 – OFFSET B8h (Test Purpose Only) BIT 31:0 7.2.55 Transmit Termination Adjustment FUNCTION Reserved TYPE RO DESCRIPTION Reset to 00000030h. TL CSR – OFFSET BCh BIT 31:0 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 00000004h. Page 46 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.56 SSID/SSVID CAPABILITY ID REGISTER – OFFSET C0h BIT 7:0 7.2.57 FUNCTION SSID/SSVID Capabilities ID TYPE RO DESCRIPTION Read as 0Dh to indicate that these are SSID/SSVID capability registers. NEXT ITEM POINTER REGISTER – OFFSET C0h BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION Pointer points to the PCI Express capability register (E0h). RO Reset to E0h. 7.2.58 SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h BIT 15:0 FUNCTION SSVID TYPE RO DESCRIPTION It indicates the sub-system vendor id. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. 7.2.59 SUBSYSTEM ID REGISTER – OFFSET C4h BIT 31:16 FUNCTION SSID TYPE RO DESCRIPTION It indicates the sub-system device id. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. 7.2.60 GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only) BIT 0 FUNCTION GPIO [0] Input 1 GPIO [0] Output Enable TYPE RO RW 2 GPIO [0] Output Register RW 3 4 Reserved GPIO [1] Input RO RO 5 GPIO [1] Output Enable RW 6 GPIO [1] Output Register RW 7 8 Reserved GPIO [2] Input RO RO DESCRIPTION State of GPIO [0] pin 0b: GPIO [0] is an input pin 1b: GPIO [0] is an output pin Reset to 0b. Value of this bit will be output to GPIO [0] pin if GPIO [0] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [1] pin. 0b: GPIO [1] is an input pin 1b: GPIO [1] is an output pin Reset to 0b. Value of this bit will be output to GPIO [1] pin if GPIO [1] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [2] pin Page 47 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.61 BIT FUNCTION 9 GPIO [2] Output Enable TYPE RW 10 GPIO [2] Output Register RW 11 12 Reserved GPIO [3] Input RO RO 13 GPIO [3] Output Enable RW 14 GPIO [3] Output Register RW 15 16 Reserved GPIO [4] Input RO RO 17 GPIO [4] Output Enable RW 18 GPIO [4] Output Register RW 19 20 Reserved GPIO [5] Input RO RO 21 GPIO [5] Output Enable RW 22 GPIO [5] Output Register RW 23 24 Reserved GPIO [6] Input RO RO 25 GPIO [6] Output Enable RW 26 GPIO [6] Output Register RW 27 28 Reserved GPIO [7] Input RO RO 29 GPIO [7] Output Enable RW 30 GPIO [7] Output Register RW 31 Reserved RO DESCRIPTION 0b: GPIO [2] is an input pin 1b: GPIO [2] is an output pin Reset to 0b. Value of this bit will be output to GPIO [2] pin if GPIO [2] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [3] pin. 0b: GPIO [3] is an input pin 1b: GPIO [3] is an output pin Reset to 0b. Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [4] pin. 0b: GPIO [4] is an input pin 1b: GPIO [4] is an output pin Reset to 0b. Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [5] pin. 0b: GPIO [5] is an input pin 1b: GPIO [5] is an output pin Reset to 0b. Value of this bit will be output to GPIO [5] pin if GPIO [5] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [6] pin. 0b: GPIO [6] is an input pin 1b: GPIO [6] is an output pin Reset to 0b. Value of this bit will be output to GPIO [6] pin if GPIO [6] is configured as an output pin. Reset to 0b. Reset to 0b. State of GPIO [7] pin. 0b: GPIO [7] is an input pin 1b: GPIO [7] is an output pin Reset to 0b. Value of this bit will be output to GPIO [7] pin if GPIO [7] is configured as an output pin. Reset to 0b. Reset to 0b. EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only) Page 48 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 0 EEPROM Start TYPE DESCRIPTION Starts the EEPROM read or write cycle. RW Reset to 0b. Sends the command to the EEPROM. EEPROM Command 2 EEPROM Error Status RO EEPROM Autoload Success RO Reset to 0b. 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autolad occurred successfully after RESET. Configuration registers were loaded with values in the EEPROM RO It will be cleared when read at this bit. 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autoload occurred successfully after PREST. Configuration registers were loaded with values stored in the EEPROM 3 4 5 EEPROM Autoload Status EEPROM Autoload Disable RW 0b: EEPROM read 1b: EEPROM write 1 Reset to 0b. 1b: EEPROM acknowledge was not received during the EEPROM cycle. RW Reset to 0b. 0b: EEPROM autoload enabled 1b: EEPROM autoload disabled Reset to 1b. Determines the frequency of the EEPROM clock, which is derived from the primary clock. 7:6 EEPROM Clock Rate RW 00b: Reserved 01b: PEXCLK / 1024 (PEXCLK is 125MHz) 10b: Reserved 11b: Test Mode Reset to 01b. 7.2.62 EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only) BIT 8 FUNCTION Reserved 15:9 EEPROM Address TYPE RO DESCRIPTION Reset to 0b. Contains the EEPROM address. RW Reset to 0. 7.2.63 EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only) BIT FUNCTION 31:16 EEPROM Data TYPE RW DESCRIPTION Contains the data to be written to the EEPROM. After completion of a read cycle, this register will contain the data from the EEPROM. Reset to 0000h. 7.2.64 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 10h to indicate that these are PCI express enhanced capability registers. Page 49 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.65 NEXT ITEM POINTER REGISTER – OFFSET E0h BIT 15:8 7.2.66 TYPE RO DESCRIPTION Read as 00h. No other ECP registers. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h BIT FUNCTION 19:16 Capability Version RO 23:20 Device/Port Type RO 24 Slot Implemented HwInt 29:25 31:30 7.2.67 FUNCTION Next Item Pointer Interrupt Message Number Reserved TYPE RO RO DESCRIPTION Read as 0001b to indicate the device is compliant to the PCI Express Base Specifications. Indicates the type of PCI Express logical device. Reset to 0101b (Upstream port). Reset to 0110b (Downstream port). When set, indicates that the PCIe Link associated with this Port is connected to a slot. This field is valid for downstream port of the Switch. The default value may be changed by the status of strapped pin, SMBUs, or auto-loading from EEPROM. Read as 0b. No MSI messages are generated in the transparent mode. Reset to 00b. DEVICE CAPABILITIES REGISTER – OFFSET E4h BIT FUNCTION 2:0 Max_Payload_Size Supported 4:3 5 8:6 Phantom Functions Supported Extended Tag Field Supported Endpoint L0s Acceptable Latency TYPE RO RO RO DESCRIPTION Indicates the maximum payload size that the device can support for TLPs. Each port of the Switch supports 256 bytes max payload size. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 001b. Indicates the support for use of unclaimed function numbers as Phantom functions. Read as 00b, since the Switch does not act as a requester. Reset to 00b. Indicates the maximum supported size of Tag field as a Requester. Read as 0, since the Switch does not act as a requester. RO Reset to 0b. Acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. For Switch, the ASPM software would not check this value. Reset to 000b. Acceptable total latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. For Switch, the ASPM software would not check this value. 11:9 Endpoint L1 Acceptable Latency RO 14:12 Reserved RO 15 Role_Based Error Reporting RO Reset to 000b. Reset to 000b. When set, indicates that the device implements the functionality originally defined in the Error Reporting ECN. The default value may be changed by SMBus or auto-loading from EEPROM. 17:16 Reserved RO Reset to 1b. Reset to 00b. Page 50 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 25:18 Captured Slot Power Limit Value TYPE RO DESCRIPTION It applies to Upstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. This value is set by the Set_Slot_Power_Limit message or hardwired to 00h. Reset to 00h. It applies to Upstream Port only. Specifies the scale used for the Slot Power Limit Value. 7.2.68 27:26 Captured Slot Power Limit Scale RO 31:28 Reserved RO This value is set by the Set_Slot_Power_Limit message or hardwired to 00b. Reset to 00b. Reset to 0h. DEVICE CONTROL REGISTER – OFFSET E8h BIT FUNCTION 0 Correctable Error Reporting Enable 1 2 3 4 Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Enable Relaxed Ordering TYPE RW RW RW RW RO 7:5 Max_Payload_Size 8 Extended Tag Field Enable RW 9 Phantom Function Enable RW Auxiliary (AUX) Power PM Enable RWS 10 11 Enable No Snoop RW DESCRIPTION 0b: Disable Correctable Error Reporting 1b: Enable Correctable Error Reporting Reset to 0b. 0b: Disable Non-Fatal Error Reporting 1b: Enable Non-Fatal Error Reporting Reset to 0b. 0b: Disable Fatal Error Reporting 1b: Enable Fatal Error Reporting Reset to 0b. 0b: Disable Unsupported Request Reporting 1b: Enable Unsupported Request Reporting Reset to 0b. When set, it permits the device to set the Relaxed Ordering bit in the attribute field of transaction. Since the Switch can not either act as a requester or alter the content of packet it forwards, this bit always returns ‘0’ when read. Reset to 0b. This field sets maximum TLP payload size for the device. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported in the Device Capabilities register. Any value exceeding the Max_Payload_Size Supported written to this register results into clamping to the Max_Payload_Size Supported value. Reset to 000b. Does not apply to PCI Express Switch. Returns ‘0’ when read. Reset to 0. Does not apply to PCI Express Switch. Returns ‘0’ when read. RO Reset to 0b. When set, indicates that a device is enabled to draw AUX power independent of PME AUX power. Reset to 0b. When set, it permits to set the No Snoop bit in the attribute field of transaction. Since the Switch can not either act as a requester or alter the content of packet it forwards, this bit always returns ‘0’ when read. Reset to 0b. Page 51 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.69 BIT FUNCTION TYPE 14:12 Max_Read_ Request_Size RO DESCRIPTION This field sets the maximum Read Request size for the device as a Requester. Since the Switch does not generate read request by itself, these bits are hardwired to 000b. 15 Reserved RO Reset to 000b. Reset to 0b. DEVICE STATUS REGISTER – OFFSET E8h BIT FUNCTION TYPE 16 Correctable Error Detected RW1C DESCRIPTION Asserted when correctable error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when non-fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when unsupported request is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 17 18 7.2.70 Non-Fatal Error Detected Fatal Error Detected 19 Unsupported Request Detected 20 AUX Power Detected RO 21 Transactions Pending RO 31:22 Reserved RO Reset to 0b. Asserted when the AUX power is detected by the Switch Reset to 1b. Each port of Switch does not issue Non-posted Requests on its own behalf, so this bit is hardwired to 0b. Reset to 0b. Reset to 0. LINK CAPABILITIES REGISTER – OFFSET ECh BIT 3:0 FUNCTION Maximum Link Speed TYPE RO DESCRIPTION Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s. Indicates the maximum width of the given PCIe Link. The width of each port is determined by strapped pin or EEPROM pre-loaded value. 9:4 Maximum Link Width RO 11:10 Active State Power Management (ASPM) Support RO Reset to 000001b (x1) for Port 0. Reset to 000001b (x1) for Port 1. Reset to 000001b (x1) for Port 2. Indicates the level of ASPM supported on the given PCIe Link. Each port of Switch supports L0s and L1 entry. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 01b. Page 52 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 14:12 L0s Exit Latency RO 17:15 L1 Exit Latency RO 18 Reserved RO 19 Surprise Down Error Reporting Capable RO 20 7.2.71 TYPE Data Link Layer Active Reporting Capable DESCRIPTION Indicates the L0s exit latency for the given PCIe Link. The length of time this port requires to complete transition from L0s to L0 is in the range of 256ns to less than 512ns. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 011b. Indicates the L1 exit latency for the given PCIe Link. The length of time this port requires to complete transition from L1 to L0 is in the range of 16us to less than 32us. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000b. Reset to 0b. For a Downstream port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports, which does not support this optional capability, this bit must be hardwired to 0b. Rest to 0b. For a Downstream Port, this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port, this bit must be set to 1b. RO For Upstream Port, this bit must be hardwired to 0b. 23:21 Reserved R0 31:24 Port Number RO Reset to 0b for upstream port. Reset to 1b for downstream ports. Reset to 000b Indicates the PCIe Port Number for the given PCIe Link. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00h for Port 0. Reset to 01h for Port 1. Reset to 02h for Port 2. LINK CONTROL REGISTER – OFFSET F0h BIT FUNCTION 1:0 Active State Power Management (ASPM) Control RW 2 Reserved RO 3 Read Completion Boundary (RCB) RO Link Disable RW 4 5 Retrain Link TYPE DESCRIPTION 00b: ASPM is Disabled 01b: L0s Entry Enabled 10b: L1 Entry Enabled 11b: L0s and L1 Entry Enabled Note that the receiver must be capable of entering L0s even when the field is disabled. RW Reset to 00b. Reset to 0b. Does not apply to PCI Express Switch. Returns ‘0’ when read. Reset to 0b. At upstream port, it is not allowed to disable the link, so this bit is hardwired to ‘0’. For downstream ports, it disables the link when this bit is set. Reset to 0b. At upstream port, it is not allowed to retrain the link, so this bit is hardwired to 0b. For downstream ports, it initiates Link Retraining when this bit is set. This bit always returns 0b when read. Page 53 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.72 BIT FUNCTION 6 Common Clock Configuration RW 7 Extended Synch RW 15:8 Reserved RO DESCRIPTION 0b: The components at both ends of a link are operating with asynchronous reference clock 1b: The components at both ends of a link are operating with a distributed common reference clock Reset to 0b. When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0 state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state. Reset to 0b. Reset to 00h. LINK STATUS REGISTER – OFFSET F0h BIT FUNCTION 19:16 Link Speed RO 25:20 Negotiated Link Width RO Training Error RO 26 27 28 7.2.73 TYPE Link Training Slot Clock Configuration TYPE RO DESCRIPTION Read as 0001b to indicate the negotiated speed of the Express link is 2.5 Gb/s. Indicates the negotiated width of the given PCIe link. Reset to 000001b (x1). When set, indicates a Link training error occurred. This bit is cleared by hardware upon successful training of the link to the L0 link state. Reset to 0b. When set, indicates the link training is in progress. Hardware clears this bit once link training is complete. Reset to 0b. 0b: the Switch uses an independent clock irrespective of the presence of a reference on the connector 1b: the Switch uses the same reference clock that the platform provides on the connector HwInt The default value may be changed by the status of strapped pin, SMBus, or auto-loading from EEPROM. 29 Data Link Layer Link Active RO 31:30 Reserved RO Reset to 0b. Indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. Reset to 0b. Reset to 00b. SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h BIT FUNCTION 0 Attention Button Present TYPE RO DESCRIPTION When set, it indicates that an Attention Button is implemented on the chassis for this slot. The default value may be changed by SMBus or auto-loading from EEPROM. 1 Power Controller Present RO Reset to 0b. When set, it indicates that a Power Controller is implemented for this slot. The default value may be changed by SMBus or auto-loading from EEPROM. 2 Reserved RO Reset to 0b. Reset to 0b. Page 54 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 3 Attention Indicator Present 4 5 Power Indicator Present Hot-Plug Surprise TYPE RO DESCRIPTION When set, it indicates that an Attention Indicator is implemented on the chassis for this slot. The default value may be changed by SMBus or autoloading from EEPROM. RO Reset to 0b. When set, it indicates that a Power Indicator is implemented on the chassis for this slot. The default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 0b. When set, it indicates that a device present in this slot might be removed from the system without any prior notification. The default value may be changed by SMBus or auto-loading from EEPROM. 6 Hot-Plug Capable HwInt 14:7 Slot Power Limit Value RW 16:15 Slot Power Limit Scale RW 18:17 Reserved RO 31:19 Physical Slot Number RO Reset to 0b. When set, it indicates that this slot is capable of supporting Hot-Plug operation. The default value may be changed by the status of strapped pin or auto-loading from EEPROM. It applies to Downstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00h. It applies to Downstream Port only. Specifies the scale used for the Slot Power Limit Value. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00b. Reset to 00b. It indicates the physical slot number attached to this Port. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0. 7.2.74 SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h BIT FUNCTION 0 Attention Button Pressed Enable TYPE RW 1 Power Fault Detected Enable RW 2 Reserved RO 3 Presence Detect Changed Enable RW 4 5 Command Completed Interrupt Enable RW Hot-Plug Interrupt Enable RW DESCRIPTION When set, it enables the generation of Hot-Plug interrupt or wakeup event on an attention button pressed event. Reset to 0b. When set, it enables the generation of Hot-Plug interrupt or wakeup event on a power fault event. Reset to 0b. Reset to 0b. When set, it enables the generation of Hot-Plug interrupt or wakeup event on a presence detect changed event. Reset to 0b. When set, it enables the generation of Hot-Plug interrupt when the Hot-Plug Controller completes a command. Reset to 0b. When set, it enables generation of Hot-Plug interrupt on enabled Hot-Plug events. Reset to 0b. Page 55 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT 7:6 FUNCTION Attention Indicator Control TYPE RW DESCRIPTION Controls the display of Attention Indicator. 00b: Reserved 01b: On 10b: Blink 11b: Off Writes to this register also cause the Port to send the ATTENTION_INDICATOR_* Messages. Reset to 11b. Controls the display of Power Indicator. 9:8 Power Indicator Control RW 00b: Reserved 01b: On 10b: Blink 11b: Off Writes to this register also cause the Port to send the POWER_INDICATOR_* Messages. 7.2.75 Reset to 11b. 0b: reset the power state of the slot (Power On) 1b: set the power state of the slot (Power Off) 10 Power Controller Control RW 11 Reserved RO 12 Data Link Layer State Changed Enable RW Reset to 0b. Reset to 0b. If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed. 15:13 Reserved RO Reset to 0b. Reset to 000b SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h BIT FUNCTION TYPE 16 Attention Button Pressed RW1C Power Fault Detected RW1C 17 18 19 20 21 MRL Sensor Changed Reset to 0b. When set, it indicates a Power Fault is detected. Reset to 0b. When set, it indicates a MRL Sensor Changed is detected. RO Reset to 0b. When set, it indicates a Presence Detect Changed is detected. Presence Detect Changed RW1C Command Completed RW1C MRL Sensor State DESCRIPTION When set, it indicates the Attention Button is pressed. Reset to 0b. When set, it indicates the Hot-Plug Controller completes an issued command. Reset to 0b. Reflects the status of MRL Sensor. RO 0b: MRL Closed 1b: MRL Opened Reset to 0b. Page 56 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION TYPE DESCRIPTION Indicates the presence of a card in the slot. 0b: Slot Empty 1b: Card Present in slot 22 Presence Detect State RO 23 Reserved Data Link Layer State Changed Reserved RO 24 31:25 7.2.76 Reset to 1b. Reset to 0. This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed. Reset to 0 RW1C RO PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h BIT 15:0 7.2.77 This register is implemented on all Downstream Ports that implement slots. For Downstream Ports not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities register is 0b), this bit returns 1b. FUNCTION Extended Capabilities ID TYPE DESCRIPTION Read as 0001h to indicate that these are PCI express extended capability registers for advance error reporting. RO CAPABILITY VERSION – OFFSET 100h BIT FUNCTION 19:16 Capability Version TYPE DESCRIPTION Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. RO Reset to 1h. 7.2.78 7.2.79 NEXT ITEM POINTER REGISTER – OFFSET 100h BIT FUNCTION 31:20 Next Capability Offset TYPE DESCRIPTION Pointer points to the PCI Express Extended VC capability register (140h). RO Reset to 140h (upstream port). Reset to 20Ch (downstream port). UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h BIT FUNCTION 0 Training Error Status 3:1 Reserved 4 Data Link Protocol Error Status 11:5 Reserved 12 Poisoned TLP Status TYPE DESCRIPTION When set, indicates that the Training Error event has occurred. RW1CS Reset to 0b. Reset to 000b. When set, indicates that the Data Link Protocol Error event has occurred. RO RW1CS Reset to 0b. Reset to 0. When set, indicates that a Poisoned TLP has been received or generated. RO RW1CS Reset to 0b. Page 57 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 13 Flow Control Protocol Error Status RW1CS 14 Completion Timeout Status RW1CS 15 Completer Abort Status RW1CS 16 Unexpected Completion Status RW1CS 17 Receiver Overflow Status RW1CS 18 Malformed TLP Status RW1CS ECRC Error Status RW1CS 19 7.2.80 20 Unsupported Request Error Status 31:21 Reserved TYPE DESCRIPTION When set, indicates that the Flow Control Protocol Error event has occurred. Reset to 0b. When set, indicates that the Completion Timeout event has occurred. Reset to 0b. When set, indicates that the Completer Abort event has occurred. Reset to 0b. When set, indicates that the Unexpected Completion event has occurred. Reset to 0b. When set, indicates that the Receiver Overflow event has occurred. Reset to 0b. When set, indicates that a Malformed TLP has been received. Reset to 0b. When set, indicates that an ECRC Error has been detected. Reset to 0b. When set, indicates that an Unsupported Request event has occurred. RW1CS RO Reset to 0b. Reset to 0. UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h BIT FUNCTION TYPE 0 Training Error Mask RWS 3:1 Reserved 4 Data Link Protocol Error Mask 11:5 Reserved 12 Poisoned TLP Mask 13 14 15 16 Flow Control Protocol Error Mask Completion Timeout Mask Completer Abort Mask Unexpected Completion Mask RO RWS RO RWS RWS RWS RWS RWS DESCRIPTION When set, the Training Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 000b. When set, the Data Link Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 0. When set, an event of Poisoned TLP has been received or generated is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Flow Control Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completion Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completer Abort event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unexpected Completion event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Page 58 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION TYPE 17 Receiver Overflow Mask RWS 18 19 7.2.81 Malformed TLP Mask ECRC Error Mask 20 Unsupported Request Error Mask 31:21 Reserved RWS RWS RWS RO DESCRIPTION When set, the Receiver Overflow event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, an event of Malformed TLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, an event of ECRC Error has been detected is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unsupported Request event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 0. UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch BIT FUNCTION TYPE 0 Training Error Severity RWS 3:1 Reserved 4 Data Link Protocol Error Severity 11:5 Reserved 12 Poisoned TLP Severity 13 Flow Control Protocol Error Severity RWS Completion Timeout Error Severity RWS 14 15 16 17 18 Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity RO RWS RO RWS RWS RWS RWS RWS DESCRIPTION 0b: Non-Fatal 1b: Fatal Reset to 1b. Reset to 000b. 0b: Non-Fatal 1b: Fatal Reset to 1b. Reset to 0. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 1b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 1b. 0b: Non-Fatal 1b: Fatal Reset to 1b. Page 59 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.82 BIT FUNCTION TYPE 19 ECRC Error Severity RWS 20 Unsupported Request Error Severity 31:21 Reserved DESCRIPTION 0b: Non-Fatal 1b: Fatal Reset to 0. 0b: Non-Fatal 1b: Fatal RWS Reset to 0b. Reset to 0. RO CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h BIT FUNCTION 0 Receiver Error Status 5:1 Reserved 6 Bad TLP Status TYPE DESCRIPTION When set, the Receiver Error event is detected. RW1CS Reset to 0b. Reset to 00000b. When set, the event of Bad TLP has been received is detected. RO RW1CS Reset to 0b. When set, the event of Bad DLLP has been received is detected. 7.2.83 7 Bad DLLP Status RW1CS 8 REPLAY_NUM Rollover status 11:9 Reserved 12 Replay Timer Timeout status RW1CS 13 Advisory Non-Fatal Error status RW1CS 31:14 Reserved Reset to 0b. When set, the REPLAY_NUM Rollover event is detected. RW1CS Reset to 0b. Reset to 000b. When set, the Replay Timer Timeout event is detected. RO Reset to 0b. When set, the Advisory Non-Fatal Error event is detected. RO Reset to 0b. Reset to 0b. CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h BIT FUNCTION TYPE 0 Receiver Error Mask RWS 5:1 Reserved 6 Bad TLP Mask 7 Bad DLLP Mask 8 REPLAY_NUM Rollover Mask 11:9 Reserved RO RWS RWS RWS RO DESCRIPTION When set, the Receiver Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 00000b. When set, the event of Bad TLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the event of Bad DLLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the REPLAY_NUM Rollover event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 000b. Page 60 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.84 BIT FUNCTION TYPE 12 Replay Timer Timeout Mask RWS 13 Advisory Non-Fatal Error Mask 31:14 Reserved BIT FUNCTION 4:0 First Error Pointer 6 7 ROS Reset to 1b. Reset to 0. ECRC Generation Enable RWS ECRC Check Capable 31:9 Reserved DESCRIPTION It indicates the bit position of the first error reported in the Uncorrectable Error Status register. Reset to 00000b. When set, it indicates the Switch has the capability to generate ECRC. RO ECRC Check Enable Reset to 1b. When set, it enables the generation of ECRC when needed. Reset to 0b. When set, it indicates the Switch has the capability to check ECRC. RO Reset to 1b. When set, the function of checking ECRC is enabled. RWS RO Reset to 0b. Reset to 0. HEADER LOG REGISTER – OFFSET From 11Ch to 128h FUNCTION 1st DWORD 2nd DWORD 3rd DWORD 4th DWORD TYPE ROS ROS ROS ROS DESCRIPTION Hold the 1st DWORD of TLP Header. The Head byte is in big endian. Hold the 2nd DWORD of TLP Header. The Head byte is in big endian. Hold the 3rd DWORD of TLP Header. The Head byte is in big endian. Hold the 4th DWORD of TLP Header. The Head byte is in big endian. PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h (Upstream Only) BIT 15:0 7.2.87 TYPE ECRC Generation Capable 8 BIT 31:0 63:32 95:64 127:96 7.2.86 RO Reset to 0b. When set, the Advisory Non-Fatal Error event is not logged in the Header Long register and not issued as an Error Message to RC either. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h 5 7.2.85 RWS DESCRIPTION When set, the Replay Timer Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. FUNCTION Extended Capabilities ID TYPE RO DESCRIPTION Read as 0002h to indicate that these are PCI express extended capability registers for virtual channel. CAPABILITY VERSION – OFFSET 140h (Upstream Only) BIT FUNCTION 19:16 Capability Version TYPE DESCRIPTION Read as 1h. Indicates PCIe Base Specification compliance. RO Reset to 1h. Page 61 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.88 NEXT ITEM POINTER REGISTER – OFFSET 140h (Upstream Only) BIT FUNCTION 31:20 Next Capability Offset TYPE RO DESCRIPTION Pointer points to the PCI Express Power Budgeting Capability register (20Ch). Reset to 20Ch. 7.2.89 7.2.90 PORT VC CAPABILITY REGISTER 1 – OFFSET 144h (Upstream Only) BIT FUNCTION TYPE 2:0 Extended VC Count RO 3 Reserved RO 6:4 Low Priority Extended VC Count RO 7 Reserved RO 9:8 Reference Clock RO 11:10 Port Arbitration Table Entry Size RO 31:12 Reserved RO DESCRIPTION It indicates the number of extended Virtual Channels in addition to the default VC supported by the Switch. Reset to 000b. Reset to 0b. It indicates the number of extended Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000b. Reset to 0b. It indicates the reference clock for Virtual Channels that support time-based WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock. Reset to 00b. Read as 10b to indicate the size of Port Arbitration table entry in the device is 4 bits. Reset to 10b. Reset to 0. PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only) BIT FUNCTION TYPE 7:0 VC Arbitration Capability RO 23:8 Reserved RO 31:24 VC Arbitration Table Offset RO DESCRIPTION It indicates the types of VC Arbitration supported by the device for the LPVC group. This field is valid when LPVC is greater than 0. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round Robin arbitration with 32 phases in LPVC. Reset to 00000000b. Reset to 0. It indicates the location of the VC Arbitration Table as an offset from the base address of the Virtual Channel Capability register in the unit of DQWD (16 bytes). Reset to 00h. 7.2.91 PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only) BIT FUNCTION TYPE DESCRIPTION Page 62 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 7.2.92 7.2.93 BIT FUNCTION 0 Load VC Arbitration Table TYPE RW 3:1 VC Arbitration Select RW 15:4 Reserved RO DESCRIPTION When set, the programmed VC Arbitration Table is applied to the hardware. This bit always returns 0b when read. Reset to 0b. This field is used to configure the VC Arbitration by selecting one of the supported VC Arbitration schemes. The valid values for the schemes supported by Switch are 0b and 1b. Other value than these written into this register will be treated as default. Reset to 0b. Reset to 0. PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only) BIT FUNCTION TYPE 16 VC Arbitration Table Status RO DESCRIPTION When set, it indicates that any entry of the VC Arbitration Table is written by software. This bit is cleared when hardware finishes loading values stored in the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set. 31:17 Reserved RO Reset to 0b. Reset to 0. VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h (Upstream Only) BIT FUNCTION TYPE 7:0 Port Arbitration Capability RO 13:8 Reserved RO 14 Advanced Packet Switching RO 15 Reject Snoop Transactions RO 22:16 Maximum Time Slots RO 23 Reserved RO 31:24 Port Arbitration Table Offset RO DESCRIPTION It indicates the types of Port Arbitration supported by the VC resource. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin, Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports) and Time-based WRR with 128 phases (3~4 enabled ports). Reset to 00001001b. Reset to 000000b. When set, it indicates the VC resource only supports transaction optimized for Advanced Packet Switching (AS). Reset to 0b. This bit is not applied to PCIe Switch. Reset to 0b. It indicates the maximum numbers of time slots (minus one) are allocated for Isochronous traffic. The default value may be changed by SMBus or autoloading from EEPROM. Reset to 7Fh. Reset to 0b. It indicates the location of the Port Arbitration Table (n) as an offset from the base address of the Virtual Channel Capability register in the unit of DQWD (16 bytes). Reset to 04h for Port Arbitration Table (0). 7.2.94 VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h (Upstream Only) BIT FUNCTION TYPE DESCRIPTION Page 63 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION TYPE 7:0 TC/VC Map RW 15:8 Reserved RO 16 Load Port Arbitration Table RW 19:17 Port Arbitration Select RW 23:20 Reserved RO 26:24 VC ID RO 30:27 Reserved RO 31 VC Enable RW DESCRIPTION This field indicates the TCs that are mapped to the VC resource. Bit locations within this field correspond to TC values. When the bits in this field are set, it means that the corresponding TCs are mapped to the VC resource. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to FFh. Reset to 00h. When set, the programmed Port Arbitration Table is applied to the hardware. This bit always returns 0b when read. Reset to 0b. This field is used to configure the Port Arbitration by selecting one of the supported Port Arbitration schemes. The permissible values for the schemes supported by Switch are 000b and 011b at VC0, other value than these written into this register will be treated as default. Reset to 000b. Reset to 0h. This field assigns a VC ID to the VC resource. Reset to 000b. Reset to 0h. 0b: it disables this Virtual Channel 1b: it enables this Virtual Channel Reset to 1b. 7.2.95 7.2.96 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only) BIT 15:0 FUNCTION Reserved 16 Port Arbitration Table Status TYPE RO DESCRIPTION Reset to 0000h. When set, it indicates that any entry of the Port Arbitration Table is written by software. This bit is cleared when hardware finishes loading values stored in the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set. RO 17 VC Negotiation Pending RO 31:18 Reserved RO Reset to 0b. When set, it indicates that the VC resource is still in the process of negotiation. This bit is cleared after the VC negotiation is complete. Reset to 0b. Reset to 0. PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh (Upstream Only) The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each table entry allocates two bits to represent Port Number. The table entry size is dependent on the number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table contains 128 entries if three or four ports are to be enabled. The following table shows the register array layout for the size of entry equal to two. Table 7-1 Table Entry Size in 4 Bits 63 - 56 Phase [15:14] Phase [31:30] 55 - 48 Phase [13:12] Phase [29:28] 47 - 40 Phase [11:10] Phase [27:26] 39 - 32 Phase [9:8] Phase [25:24] 31 - 24 Phase [7:6] Phase [23:22] Page 64 of 76 December 2009 – Revision 1.2 Pericom Semiconductor 23 - 16 Phase [5:4] Phase [21:20] 15 - 8 Phase [3:2] Phase [19:18] 7-0 Phase [1:0] Phase [17:16] Byte Location 00h 08h PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 63 - 56 Phase [47:46] Phase [63:62] Phase [79:78] Phase [95:94] Phase [111:110] Phase [127:126] 7.2.97 47 - 40 Phase [43:42] Phase [59:58] Phase [75:74] Phase [91:90] Phase [107:106] Phase [123:122] 39 - 32 Phase [41:40] Phase [57:56] Phase [73:72] Phase [89:88] Phase [105:104] Phase [121:120] 31 - 24 Phase [39:38] Phase [55:54] Phase [71:70] Phase [87:86] Phase [103:102] Phase [119:118] 23 - 16 Phase [37:36] Phase [53:52] Phase [69:68] Phase [85:84] Phase [101:100] Phase [117:116] 15 - 8 Phase [35:34] Phase [51:50] Phase [67:66] Phase [83:82] Phase [99:98] Phase [115:114] 7-0 Phase [33:32] Phase [49:48] Phase [65:64] Phase [81:80] Phase [97:96] Phase [113:112] Byte Location 10h 18h 20h 28h 30h 38h PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch BIT 15:0 7.2.98 55 - 48 Phase [45:44] Phase [61:60] Phase [77:76] Phase [93:92] Phase [109:108] Phase [125:124] FUNCTION Extended Capabilities ID TYPE RO DESCRIPTION Read as 0004h to indicate that these are PCI express extended capability registers for power budgeting. CAPABILITY VERSION – OFFSET 20Ch BIT FUNCTION 19:16 Capability Version TYPE DESCRIPTION Read as 1h. Indicates PCIe Base Specification compliance. RO Reset to 1h. 7.2.99 7.2.100 7.2.101 NEXT ITEM POINTER REGISTER – OFFSET 20Ch BIT FUNCTION 31:20 Next Capability Offset TYPE DESCRIPTION Read as 000h. No other ECP registers. RO Reset to 000h. DATA SELECT REGISTER – OFFSET 210h BIT FUNCTION TYPE 7:0 Data Selection RW 31:8 Reserved RO DESCRIPTION It indexes the power budgeting data reported through the data register. When 00h, it selects D0 Max power budget When 01h, it selects D0 Sustained power budget Other values would return zero power budgets, which means not supported Reset to 00h. Reset to 000000h. POWER BUDGETING DATA REGISTER – OFFSET 214h BIT FUNCTION TYPE DESCRIPTION Page 65 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet BIT FUNCTION 7:0 Base Power 9:8 12:10 14:13 17:15 Data Scale PM Sub State PM State Type TYPE RO RO RO DESCRIPTION It specifies the base power value in watts. This value represents the required power budget in the given operation condition. The default value may be changed by auto-loading from EEPROM. Reset to 04h. It specifies the scale to apply to the base power value. The default value may be changed by auto-loading from EEPROM. Reset to 00b. It specifies the power management sub state of the given operation condition. It is initialized to the default sub state. RO Reset to 000b. It specifies the power management state of the given operation condition. It defaults to the D0 power state. The default value may be changed by autoloading from EEPROM. RO Reset to 00b. It specifies the type of the given operation condition. It defaults to the Maximum power state. The default value may be changed by auto-loading from EEPROM. Reset to 111b. It specifies the power rail of the given operation condition. 7.2.102 20:18 Power Rail RO 31:21 Reserved RO Reset to 010b. Reset to 0. POWER BUDGET CAPABILITY REGISTER – OFFSET 218h BIT FUNCTION TYPE 0 System Allocated RO DESCRIPTION When set, it indicates that the power budget for the device is included within the system power budget. The default value may be changed by auto-loading from EEPROM. 31:1 Reserved RO Reset to 0b. Reset to 0. Page 66 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 8 CLOCK SCHEME The PI7C9X20303SL requires 100MHz differential clock inputs through REFCLKP and REFCLKN Pins as shown in the following table. Table 8-1 Input Clock Requirements Symbol ClkInFREQ ClkInDC TR, TF VSW Description Reference input clock range Duty cycle of input clock Rise/Fall time of input clock Differential input voltage swing Min 40 (peak-to-peak) 800 (zero-to-peak) 400 a. RCUI (Reference Clock Unit Interval) refers to the reference clock period Page 67 of 76 December 2009 – Revision 1.2 Pericom Semiconductor Typical 100 50 - Max. 60 0.2 2000 1000 Unit MHz % RCUIa mV mV PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 9 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C9X20303SL for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins. 9.1 INSTRUCTION REGISTER The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. PI7C9X20303SL implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in Table 10-1. Those bit combinations that are not listed are equivalent to the BYPASS (11111) instruction: Table 9-1 Instruction register codes Instruction EXTEST SAMPLE HIGHZ CLAMP 9.2 Operation Code (binary) 00000 00001 00101 00100 Register Selected Boundary Scan Boundary Scan Bypass Bypass IDCODE 01100 Device ID BYPASS INT_SCAN MEM_BIST 11111 00010 01010 Bypass Internal Scan Memory BIST Operation Drives / receives off-chip test data Samples inputs / pre-loads outputs Tri-states output and I/O pins except TDO pin Drives pins from boundary-scan register and selects Bypass register for shifts Accesses the Device ID register, to read manufacturer ID, part number, and version number Selected Bypass Register Scan test Memory BIST test BYPASS REGISTER The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C9X20303SL. 9.3 DEVICE ID REGISTER This register identifies Pericom as the manufacturer of the device and details the part number and revision number for the device. Table 9-2 JTAG device ID register Bit 31-28 27-12 11-1 0 Type RO RO RO RO Value 0001 1001001000000100 01000111111 1 Description Version number Last 4 digits (hex) of the die part number Pericom identifier assigned by JEDEC Fixed bit equal to 1’b1 Page 68 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 9.4 BOUNDARY SCAN REGISTER The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X20303SL package pins. The VDD, VSS, and JTAG pins are not in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin. The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK. 9.5 JTAG BOUNDARY SCAN REGISTER ORDER Table 9-3 JTAG boundary scan register definition Boundary Scan Register Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name WAKEUP _L SLOT_IMP[2] NC TEST5 Pin No 6 7 9 10 TEST4 TEST3 SMBCLK SMBDATA PWR_SAV DEQ[3] GPIO[0] 11 12 13 16 17 18 21 GPIO[1] 22 GPIO[2] 23 GPIO[3] 24 GPIO[4] 25 GPIO[5] 26 GPIO[6] 27 GPIO[7] 28 TEST1 HIDRV LOWDRV DTX[3] EECLK EEPD 31 32 33 38 40 41 PERST_L PWR_IND[1] PWR_IND[3] PORTERR[0] ATT_IND[1] ATT_IND[3] 43 45 Page 69 of 76 December 2009 – Revision 1.2 Pericom Semiconductor Type Input Bidir Bidir Bidir Control Bidir Bidir Bidir Bidir Bidir Bidir Bidir Control Bidir Control Bidir Control Bidir Control Bidir Control Bidir Control Bidir Control Bidir Control Bidir Bidir Bidir Bidir Output2 Bidir Control Input Output2 Output2 Output2 Output2 Output2 Tri-state Control Cell 4 4 4 4 4 4 4 4 4 4 12 14 16 18 20 22 24 26 4 4 4 4 33 PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet Boundary Scan Register Number 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin Name PORTERR[1] ATT_BTN[1] ATT_BTN[3] PORTERR[2] PRSNT[1] PRSNT[3] PWR_ENA[1] PWR_ENA[3] PWR_FLT[1] PWR_FLT[3] NC TEST2 DWNRST_L[1] DWNRST_L[2] NC PWR_IND[2] TEST6 ATT_IND[2] ATT_RTN[2] SLOTCLK PRSNT[2] PWR_ENA[2] PWR_FLT[2] SLOT_IMP[1] Pin No 47 51 54 66 96 97 98 126 127 128 Page 70 of 76 December 2009 – Revision 1.2 Pericom Semiconductor Type Output2 Input Input Output2 Input Input Output2 Output2 Input Input Output2 Input Output2 Output2 Output2 Output2 Bidir Output2 Input Bidir Input Output2 Input Bidir Tri-state Control Cell 4 4 4 PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 10 POWER MANAGEMENT The PI7C9X20303SL supports D0, D1, D2, D3-hot, and D3-cold Power States. The PCI Express Physical Link Layer of the PI7C9X20303SL device supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3 ready and L3 Power States. During the transition from D3-hot to D3-cold state, the main power supplies of VDDC and VDDR are turned off to save power while keeping the VDDAUX and VAUX with the auxiliary power supplies to maintain all necessary information to be restored to the full power D0 state. PI7C9X20303SL has been designed to have sticky registers that are powered by auxiliary power supplies. PI7C9X20303SL forwards power management messages to the upstream Switches or root complex. PI7C9X20303SL also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X20303SL supports beacon generation and WAKEUP_L signal. Page 71 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 11 ELECTRICAL AND TIMING SPECIFICATIONS 11.1 ABSOLUTE MAXIMUM RATINGS Table 11-1 Absolute maximum ratings (Above which the useful life may be impaired. For user guidelines, not tested.) -65oC to 150oC -40oC to 85oC -0.3v to 3.0v Storage Temperature Ambient Temperature with power applied PCI Express supply voltage to ground potential (VDDA, VDDC, and VDDAUX) DC input voltage for PCI Express signals -0.3v to 3.0v Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 11.2 POWER CONSUMPTION Table 11-2 PI7C9X303SL power dissipation Mode L0 Normal Mode Power Saving Enabled Disabled Enabled Disabled L1 Standby Mode Typical Power Dissipation (mW) 360 510 210 420 11.3 DC SPECIFICATIONS Table 11-3 DC electrical characteristics Power Pins VDDA VDDR VDDC VAUX VDDAUX VTT Min. 0.9v 3.0v 0.9v 3.0v 0.9v VDDC Typ. 1.0v 3.3v 1.0v 3.3v 1.0v 1.5v Max. 1.1v 3.6v 1.1v 3.6v 1.1v 1.8v VDDA: analog power supply for PCI Express Interface VDDR: digital power supply for 3.3v I/O Interface VDDC: digital power supply for the core VAUX: digital auxiliary power supply for 3.3v I/O Interface VDDAUX: digital auxiliary power supply for the core VTT: transmit termination power supply for PCI Express Interface In order to support auxiliary power management fully, it is recommended to have VDDC and VDDAUX separated. Page 72 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 11.4 AC SPECIFICATIONS Table 11-4 Transmitter Characteristics Symbol Description Voltage Parameters VTX-DIFFa Output voltage compliance @ typical swing VTX-DIFFp (peak-to-peak, single ended) VTX-DIFFpp (peak-to-peak, differential) VSW Supported TX output voltage range (pp, differential) VOL Low-level output voltage VOH High-level output voltage VTX-CM-AC Transmit common-mode voltage in L0 VTX-CM-HiZ Transmit common-mode voltage in L0s (TX) & L1 VTX-DE-RATIO De-emphasized differential output voltage VTX-IDLE-DIFFp Electric Idle differential peak voltage VTX-RCVVoltage change during Receive Detection Min Typical Max. Unit 400 800 400b 500 1000 600 1200 1500c mV mV mV 0.50 VTT - 1.5 *VTX-DIFFp VTT - 0.5VTX-DIFFp VTT - VTX-DIFFp VTX-CM-AC 0 1.45 -7.96 20 VTX-DIFFp V V V V dB mV mV DETECT RLTX-DIFF RLTX-CM ZOSE ZTX-DIFF-DC TTX-RISE, TTX- Transmitter Differential Return loss Transmitter Common Mode Return loss Single-ended output impedance DC Differential TX Impedance Rise / Fall time of TxP, TxN outputs 10 6 40 80 80 dB dB Ω Ω ps 50 100 60 120 110d 400 400.12 0.25e ps UI UI 0.125 UI UI UI UI 4 11 11 2+ 200ps 6 12 16 ns 30 80 ns 10 1 10.2 2 us ns FALL Jitter Parameters UI Unit Interval TTX-MAX-JITTER Transmitter total jitter (peak-to-peak) TTX-EYE Minimum TX Eye Width (1 - TTX-MAXJITTER) TTX-EYEMaximum time between the jitter median and MEDIAN-tomaximum deviation from the median MAX-JITTER Timing Parameters LTLAT-10 Transmitter data latency (for n=10) LTLAT-20 Transmitter data latency (for n=20) LTX-SKEW Transmitter data skew between any 2 lanes 399.88 0.75 9 9 0 TTX-IDLE-SET- Maximum time to transition to a valid electrical idle after sending an Electrical Idle ordered set TEIExit Time to exit Electrical Idle (L0s) state into L0 TBTEn Time from asserting BeaconTxEn to beacon being transmitted on the lane TRxDetectEn Pulse width of RxDetectEn input 9.8 TRxDetect RxDetectEn falling edge to RxDetect delay a. Measured with Vtt = 1.2V, HiDrv=’0’,LowDrv=’0’ and Dtx=’0000’. b. Minimum swing assumes LoDrv = 1, HiDrv = 0 and Dtx =1100 c. Max swing assumes LoDrv = 0, HiDrv = 1, Dtx = 0010, VTT = 1.8V d. As measured between 20% and 80% points. Will depend on package characteristics. e. Measured using PCI Express Compliance Pattern ns TO-IDLE Page 73 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet Table 11-5 Receiver Characteristics Symbol Description Voltage Parameters VRX-DIFFp-p Differential input voltage (peak-to-peak) VRX-IDLE-DETDifferential input threshold voltage (peakto-peak) to assert TxIdleDetect output DIFFp-p VRX-CM-AC Receiver common-mode voltage for ACcoupling TRX-RISE, TRXRise time / Fall time of RxP, RxN inputs Min Typical 170 65 0 Max. Unit 1200 175 mV mV 150 mV 160 Ps 120 60 60 Ω Ω Ω FALL ZRX-DIFF-DC ZRX-COM-DC ZRX-COM- Differential input impedance (DC) Single-ended input impedance Initial input common mode impedance (DC) INITIAL-DC ZRX-COM-HIGHPowered down input common mode impedance (DC) IMP-DC RLRX-DIFF Receiver Differential Return Lossa RLRX-CM Receiver Common Mode Return Lossb Jitter Parameters TRX-MAX-JITTER Receiver total jitter tolerance TRX-EYE Minimum Receiver Eye Width TRX-EYEMaximum time between jitter median and max deviation from median MEDIAN-to-MAX- 80 40 5 100 50 50 200k Ω 10 6 dB dB 0.65 0.325 UI UI UI 29 60 1c 200 bits bits bits us 10 20 ns 5 10 ns 0.35 JITTER Timing Parameters LRLAT-10 Receiver data latency for n=10 28 LRLAT-20 Receiver data latency for n=20 49 TRX-SKEW Receiver data skew between any 2 lanes 0 TBDDly Beacon-Activity on channel to detection of Beacond TRXDelay from detection of Electrical Idle IDLE_ENTER condition on the channel to assertion of TxIdleDetect output TRXDelay from detection of L0s to L0 IDLE_EXIT transition to deassertion of TxIdleDetect output a. Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency Page 74 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 12 PACKAGE INFORMATION The package of PI7C9X20303SL is a 14mm x 14mm LQFP (128 Pin) package. The following are the package information and mechanical dimension: Figure 12-1 Package outline drawing Page 75 of 76 December 2009 – Revision 1.2 Pericom Semiconductor PI7C9X20303SL 3Port-3Lane PCI Express® Switch TM SlimLine Family Datasheet 13 ORDERING INFORMATION Part Number PI7C9X20303SL□FDEX PI 7C 9X20303SL Temperature Range -40o to 85oC (Industrial Temperature) Package 128-pin LQFP 14mm x 14mm FD E X Blank=Tray X=Tape & Reel Blank=Standard E=Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family PI=Pericom Page 76 of 76 December 2009 – Revision 1.2 Pericom Semiconductor Pb-Free & Green Yes