PI7C9X20404GP
PCI EXPRESS PACKET SWITCH
DATASHEET
REVISION 1.6
June 2009
3545 North 1ST Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
FAX: 408-435-1100
Internet: http://www.pericom.com
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
DISCLAIMER
The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this
document may be copied or reproduced in any form or by any means without prior written consent of PSC.
The information in this document is subjected to change without notice. PSC retains the right to make changes to this document at any time
without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does
not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any
use of the information contained in this document.
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Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a
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1)
2)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
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Page 2 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
REVISION HISTORY
Date
12/13/06
1/3/06
5/22/07
Revision Number
0.1
0.4
0.5
7/11/07
0.6
8/29/07
0.7
10/04/07
0.8
1/11/08
1.0
Description
Initial Preliminary Datasheet
Proofreading an Editing
Revision of the registers and the description. Packaging mechanical
added
Corrected pin description for ATT_IND[4], TEST3, TEST4, TEST5
and TEST 6 in section 3 and 4
Corrected register description for offset F0h in section 7.2.70
Removed Reference Clock Output related info from 1. Features
(advanced power saving), 3 Pin Description (RREF_CO, REFCLK,
VDDIO), 4. Pin Assignment (RREF_CO to TEST7, REFCLK to
NC, VDDIO to VDDR), 8 Clock Scheme (description), 12.2 AC
Specification (VDDIO)
Updated “ORDERING INFORMATION”
Added 12.3 AC Specifications: Transmitter and Receiver
Specifications
Updated 8 Clock Scheme (Table 8-1)
Updated Chapter 14 Ordering Information (PI7C9X20404GPNBE)
Updated Pericom Logo
Added Disclaimer
Added Chapter 6.2 SMBus
Added SMBus related items in Chapter 1 Features
Modified SMBus related pins (GPIO[5:7])
Corrected Chapter 6. EEPROM and Chapter 7. Register Description
Corrected Chapter 3. Pin Description (PORTACT, TEST) and
Chapter 4. Pin Assignment (B9, D3, D12, D14, E12, E14, G12, G14,
H12, H14, K12, K14, L12, L13, L14, N12, N14, P2, P12, P14)
Corrected Chapter 3.6 Power Pins (VDDC, VDDA, VDDCAUX to
1.1V), Chapter 3.4 Misc. Signals (TEST6 corrected, TEST7 to
PWR_SAV)
Updated Chapter 7.2.53 bit [15:0]
Updated Chapter 3.5 JTAG Signals description
Updated Chapter 7.2.53
Remove VDDP, VDDAUX from Chapter 11 Power Management
and Chapter 12.1 Absolute Maximum Ratings
Revised Chapter 11 Power Management
Updated Chapter 3 Pin Description (PERP/PERN and PETP/PETN’s
description, WAKEUP_L’s description, VC1_EN’s name and
description, SLOT_IMP’s description, HOTPLUG’s description,
SLOTCLK’s description, PWR_IND’s description, ATT_IND’s
description, MRL_PDC’s description, PWR_ENA_L’s description,
EEPD’s description, SMBDATA’s description, SCAN_EN’s
description, PORTERR’s name and description)
Updated Chapter 4 Pin Assignment (VC_RS to VC1_EN,
PORTACT to PORTERR)
Updated 5.1 Physical Layer Circuit and Chapter 5.6 Queue
Updated Disclaimer and Footer
Updated Chapter 14 Ordering Information
Fixed Chapter 6.1.4 Mapping EEPROM format
Modified Chapter 3.4 MISCELLANEOUS SIGNALS
Page 3 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
1/30/08
2/20/08
1.1
1.2
4/15/08
1.3
7/1/08
1.4
11/26/08
1.5
6/8/09
1.6
(GPIO[0,1,3,5])
Modified Chapter 4 PIN ASSIGNMENTS (GPIO[0,1,3,5])
Modified Chapter 6 EEPROM (0Ch)
Modified Chapter 7 Registers (7.2.50 Replay Time-Out Counter,
7.2.52 Switch Operation Mode Bit[14,15,17], 7.2.53 Switch
Operation Mode Bit[8:15], 7.2.64 PCI Express Capability Bit[24] ,
7.2.70 Link Status Bit[28], 7.2.103 Power Budgeting Data, 7.2.104
Power Budget Capability)
Corrected 3.5 JTAG Boundary Scan Signal
Updated Chapter 3.5 Power Pins (VDDC, VDDA, VDDCAUX)
Updated Chapter 1 Features (Power Dissipation)
Updated Chapter 12.2 DC Specification (Power Consumption,
VDDCAUX)
Updated Chapter 3.1 PCI Express Interface Signals (REFCLKP,
REFCLKN)
Corrected Chapter 12.2 DC Specifications
Modified Chapter 1 Features (Industrial Temperature)
Corrected Chapter 7.2.27 Interrupt Pin Register
Corrected Chapter 7.2.32 Power Management Data Register Bit 3
Corrected Chapter 7.2.51 Acknowledge Latency Timer
Modified Chapter 12.1 Absolute Maximum Ratings (Ambient
Temperature with power applied)
Updated Chapter 14 Ordering Information
Removed “Preliminary” and “Confidential” references
Updated Chapter 3.2 Port Configuration Signals (SLOT_IMP,
HOTPLUG, SLOTCLK)
Updated Chapter 3.3 Hot Plug Signals (PWR_IND, ATT_IND)
Updated Chapter 3.4 Miscellaneous Signals (PWR_SAV pin
removed, EEPD)
Updated Chapter 3.5 JTAG Boundary Scan Signals (TMS, TDI,
TRST_L)
Page 4 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
3.2
3.3
3.4
3.5
3.6
4
PIN ASSIGNMENTS .........................................................................................................................................15
4.1
5
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
PORT CONFIGURATION SIGNALS .......................................................................................................12
HOT PLUG SIGNALS ...............................................................................................................................13
MISCELLANEOUS SIGNALS..................................................................................................................13
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................14
POWER PINS.............................................................................................................................................14
PIN LIST OF 148-PIN LFBGA....................................................................................................................15
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH .......................................................................................................................................................19
5.6.2
PD .......................................................................................................................................................19
5.6.3
NPHD .................................................................................................................................................19
5.6.4
CPLH ..................................................................................................................................................19
5.6.5
CPLD ..................................................................................................................................................20
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................21
5.9
VC ARBITRATION ...................................................................................................................................21
5.10 FLOW CONTROL .....................................................................................................................................21
5.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS .....................................................................................................22
6.1.2
EEPROM MODE AT RESET..............................................................................................................22
6.1.3
EEPROM SPACE ADDRESS MAP ....................................................................................................22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS..........................................24
6.2
SMBUS INTERFACE .................................................................................................................................29
7
REGISTER DESCRIPTION.............................................................................................................................30
7.1
REGISTER TYPES ....................................................................................................................................30
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS ....................................................................30
7.2.1
VENDOR ID REGISTER – OFFSET 00h ...........................................................................................32
7.2.2
DEVICE ID REGISTER – OFFSET 00h.............................................................................................32
7.2.3
COMMAND REGISTER – OFFSET 04h............................................................................................32
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................33
7.2.5
REVISION ID REGISTER – OFFSET 08h .........................................................................................33
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June 2009 – Revision 1.6
Pericom Semiconductor
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7.2.53
7.2.54
7.2.55
7.2.56
7.2.57
7.2.58
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
CLASS CODE REGISTER – OFFSET 08h .........................................................................................33
CACHE LINE REGISTER – OFFSET 0Ch.........................................................................................34
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................34
HEADER TYPE REGISTER – OFFSET 0Ch......................................................................................34
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ......................................................................34
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................34
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................34
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...........................................................35
I/O BASE ADDRESS REGISTER – OFFSET 1Ch..............................................................................35
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch.............................................................................35
SECONDARY STATUS REGISTER – OFFSET 1Ch ..........................................................................35
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ...................................................................36
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ..................................................................36
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h.....................................36
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h....................................36
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h .........37
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch .......37
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h...................................................37
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h..................................................37
CAPABILITY POINTER REGISTER – OFFSET 34h .........................................................................37
INTERRUPT LINE REGISTER – OFFSET 3Ch.................................................................................38
INTERRUPT PIN REGISTER – OFFSET 3Ch ...................................................................................38
BRIDGE CONTROL REGISTER – OFFSET 3Ch ..............................................................................38
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ...........................................39
NEXT ITEM POINTER REGISTER – OFFSET 80h...........................................................................39
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h.............................................39
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................39
PPB SUPPORT EXTENSIONS – OFFSET 84h..................................................................................40
DATA REGISTER – OFFSET 84h ......................................................................................................40
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) ....................................40
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) .................................41
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) ..................................41
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) ....................................41
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ......................41
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ...........................................41
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)........................................41
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) ......................................42
VPD REGISTER – OFFSET 9Ch (Upstream Port Only)....................................................................42
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only).........................................................42
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h..................................................42
NEXT ITEM POINTER REGISTER – OFFSET A4h ..........................................................................42
LENGTH REGISTER – OFFSET A4h ................................................................................................43
XPIP CSR0 – OFFSET A8h (Test Purpose Only)...............................................................................43
XPIP CSR1 – OFFSET ACh (Test Purpose Only) ..............................................................................43
REPLAY TIME-OUT COUNTER – OFFSET B0h..............................................................................43
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h.......................................................................43
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port)......................................................44
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) .................................................45
SSID/SSVID CAPABILITY ID REGISTER – OFFSET B8h................................................................45
NEXT ITEM POINTER REGISTER – OFFSET B8h ..........................................................................46
SUBSYSTEM VENDOR ID REGISTER – OFFSET BCh....................................................................46
SUBSYSTEM ID REGISTER – OFFSET BCh ....................................................................................46
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)...............................................46
Page 6 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
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7.2.100
7.2.101
7.2.102
7.2.103
7.2.104
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)........................................47
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only).........................................48
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only)................................................48
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................48
NEXT ITEM POINTER REGISTER – OFFSET E0h ..........................................................................49
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h..............................................................49
DEVICE CAPABILITIES REGISTER – OFFSET E4h .......................................................................49
DEVICE CONTROL REGISTER – OFFSET E8h...............................................................................50
DEVICE STATUS REGISTER – OFFSET E8h...................................................................................51
LINK CAPABILITIES REGISTER – OFFSET ECh............................................................................51
LINK CONTROL REGISTER – OFFSET F0h....................................................................................52
LINK STATUS REGISTER – OFFSET F0h ........................................................................................53
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h ...................................53
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h...........................................54
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h ...............................................55
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h.56
CAPABILITY VERSION – OFFSET 100h ..........................................................................................56
NEXT ITEM POINTER REGISTER – OFFSET 100h.........................................................................56
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .................................................56
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ....................................................57
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch.............................................58
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h......................................................59
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h .........................................................59
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h.........................60
HEADER LOG REGISTER – OFFSET From 11Ch to 128h ..............................................................60
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h .......................60
CAPABILITY VERSION – OFFSET 140h ..........................................................................................60
NEXT ITEM POINTER REGISTER – OFFSET 140h.........................................................................61
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h ....................................................................61
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h ....................................................................61
PORT VC CONTROL REGISTER – OFFSET 14Ch...........................................................................61
PORT VC STATUS REGISTER – OFFSET 14Ch...............................................................................62
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h........................................................62
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h ...........................................................62
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h................................................................63
VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch .......................................................63
VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h ...........................................................64
VC RESOURCE STATUS REGISTER (1) – OFFSET 164h................................................................64
VC ARBITRATION TABLE REGISTER – OFFSET 170h...................................................................64
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ...........................65
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch ....................65
CAPABILITY VERSION – OFFSET 20Ch......................................................................................66
NEXT ITEM POINTER REGISTER – OFFSET 20Ch ....................................................................66
DATA SELECT REGISTER – OFFSET 210h .................................................................................66
POWER BUDGETING DATA REGISTER – OFFSET 214h ..........................................................66
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h .....................................................67
8
CLOCK SCHEME .............................................................................................................................................68
9
HOT PLUG OPERATION ................................................................................................................................69
10 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER....................................................................................70
10.1
INSTRUCTION REGISTER ......................................................................................................................70
Page 7 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
10.2
10.3
10.4
10.5
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BYPASS REGISTER .................................................................................................................................70
DEVICE ID REGISTER.............................................................................................................................70
BOUNDARY SCAN REGISTER...............................................................................................................71
JTAG BOUNDARY SCAN REGISTER ORDER......................................................................................71
11 POWER MANAGEMENT ................................................................................................................................73
12 ELECTRICAL AND TIMING SPECIFICATIONS .......................................................................................74
12.1
12.2
12.3
ABSOLUTE MAXIMUM RATINGS ........................................................................................................74
DC SPECIFICATIONS ..............................................................................................................................74
AC SPECIFICATIONS ..............................................................................................................................75
13 PACKAGE INFORMATION............................................................................................................................77
14 ORDERING INFORMATION..........................................................................................................................79
Page 8 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
TABLE OF FIGURES
FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X20404GP............................................................29
FIGURE 13-1 BOTTOM VIEW DRAWING ........................................................................................................................77
FIGURE 13-2 PACKAGE OUTLINE DRAWING .................................................................................................................78
LIST OF TABLES
TABLE 5-1 NOMINAL DRIVER CURRENT VALUES (INOM)............................................................................................16
TABLE 5-2 RATIO OF ACTUAL CURRENT AND NOMINAL CURRENT .............................................................................16
TABLE 5-3 DE-EMPHASIS LEVEL VERSUS DEQ [3:0]...................................................................................................17
TABLE 5-4 SUMMARY OF PCI EXPRESS ORDERING RULES ..........................................................................................20
TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION ....................................................................................................29
TABLE 7-1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION ....................................................................................65
TABLE 7-2 TABLE ENTRY SIZE IN 4 BITS .....................................................................................................................65
TABLE 8-1 INPUT CLOCK REQUIREMENTS ...................................................................................................................68
TABLE 10-1 INSTRUCTION REGISTER CODES ................................................................................................................70
TABLE 10-2 JTAG DEVICE ID REGISTER .....................................................................................................................70
TABLE 10-3 JTAG BOUNDARY SCAR REGISTER DEFINITION ........................................................................................71
TABLE 12-1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................74
TABLE 12-2 DC ELECTRICAL CHARACTERISTICS .........................................................................................................74
TABLE 12-3 TRANSMITTER CHARACTERISTICS............................................................................................................75
TABLE 12-4 RECEIVER CHARACTERISTICS ..................................................................................................................76
Page 9 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
1 Features
4-lane PCI Express Switch with 4 PCI Express ports
Non-blocking full-wired switching capability at 16 Gbps when all 4 ports are enabled
Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching
Peer-to-peer switching between any two downstream ports
150 ns typical latency for packet routed through Switch without blocking
Strapped pins configurable with optional EEPROM or SMBus
SMBus interface support
Compliant with System Management (SM) Bus, Version 1.0
Compliant with PCI Express Base Specification Revision 1.1
Compliant with PCI Express CEM Specification Revision 1.1
Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
Compliant with Advanced Configuration Power Interface (ACPI) Specification
Compliant with PCI Standard Hot-Plug Controller (SHPC) and Subsystem Specification Revision 1.0
Reliability, Availability and Serviceability
- Supports Data Poisoning and End-to-End CRC
- Advanced Error Reporting and Logging
- Hot Plug support
- IEEE 1149.6 JTAG interface support
Advanced Power Saving
- Empty downstream ports are set to idle state to minimize power consumption
Link Power Management
- Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states
- Active state power management for L0s and L1 states
- Beacon or Wake# support in L2 state
Device State Power Management
- Supports D0, D3Hot and D3Cold device power states
- 3.3V Aux Power support in D3Cold power state
Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR
Extended Virtual Channel capability
- Two Virtual Channels (VC) and Eight Traffic Class (TC) support
- Disabled VCs’ buffer is assigned to enabled VCs for resource sharing
- Independent TC/VC mapping for each port
- Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable
Weighted RR
Supports Isochronous Traffic
- Isochronous traffic class mapped to VC1 only
- Strict time based credit policing
Supports up to 256-byte maximum payload size
Programmable driver current and de-emphasis level at each individual port
Low Power Dissipation at 0.8W typical in L0 normal mode
Industrial Temperature Range -40o to 85oC
148-pin LFBGA 12mm x 12mm package, 0.8 mm Ball Pitch
Page 10 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
2 GENERAL DESCRIPTION
Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is
to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect
architecture. The 4-lane PCIE Switch can be configured as 4-port type combinations. It provides users the flexibility
to expand or fan-out the PCI Express lanes based on their application needs. For some systems that do not need all
the 4 lanes, the unused lanes can be disabled to reduce power consumption.
In the PCI Express Architecture, the PCIE Switch forwards posted and non-posted requests and completion packets
in either downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port. By
visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual
PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge
during enumeration, each port is given a unique bus number, device number, and function number by the initiating
software. The bus number, device number, and function number are combined to form a destination ID for each
specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as
well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded
address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the
packets to multiple small packets or merge the received packets into a large transmit packet. Also, the IDs of the
requesters and completers are kept unchanged along the path between ingress and egress port.
The Switch employs the architecture of Combined Input and Output Queue (CIOQ) in implementation. The main
reason for choosing CIOQ is that the required memory bandwidth of input queue equals to the bandwidth of ingress
port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at each
ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port based
on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass over
each other in case that the addressed egress port is available to accept them. As to the packets required to follow the
ordering rule, the Head-Of-Line (HOL) issue becomes unavoidable for packets destined to different egress ports
since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up
problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it
out. This can assure the maximum throughput being achieved and therefore the Switch works efficiently. Another
advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified
and streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port
maintains the credits independently without checking other ports' credit availability, which is otherwise required by
pure output queue architecture.
The Switch supports two virtual channels (VC0, VC1) and eight traffic classes (TC0 ~ TC7) at each port. The
ingress port independently assigns packets into the preferred virtual channel while the egress port outputs the packet
based on the predefined port and VC arbitration algorithm. For instance, the isochronous packet is given a special
traffic class number other than TC0 and mapped into VC1 accordingly. By employing the strict time based credit
policy for port arbitration and assigning higher priority to VC1 than VC0, the Switch can therefore guarantee the
time-sensitive packet is not blocked by regular traffic to assure the quality of service. In addition, some data-centric
applications only carry TC0/VC0 traffic. As a result, there are no packets that would consume VC1 bandwidth. In
order to improve the efficiency of buffer usage, the unused VC1 queues can be reassigned to VC0 and enable each
of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the
performance of the PCIe Switch further.
Page 11 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
3 PIN DESCRIPTION
3.1
PCI EXPRESS INTERFACE SIGNALS
NAME
REFCLKP
REFCLKN
3.2
PIN
A8
B8
TYPE
I
PERP [3:0]
G14, L14,
N12, E12
I
PERN [3:0]
H14, K14,
P12, D12
I
PETP [3:0]
H12, K12,
P14, D14
O
PETN [3:0]
G12, L12,
N14, E14
O
WAKEUP_L
A1
I
RESET_L
D2
I
DWNRST_L [3:1]
B3, A3, C2
O
DESCRIPTION
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PCI Express Data Serial Input Pairs: Differential data receive
signals in four ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
Port 3 (Downstream Port) is PERP[3] and PERN[3]
PCI Express Data Serial Output Pairs: Differential data transmit
signals in four ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
Port 3 (Downstream Port) is PETP[3] and PETN[3]
Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the
upstream port has to generate a Beacon that is propagated to the Root
Complex/Power Management Controller. Pin has an internal pull-up.
System Reset (Active LOW): When RESET_L is asserted, the
internal states of whole chip except sticky logics are initialized.
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either RESET_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2,3.
PORT CONFIGURATION SIGNALS
NAME
VC1_EN
B1
PIN
TYPE
I
SLOT_IMP [3:1]
B4, C4, E3
I
HOTPLUG [3:1]
A5, B5, C5
I
SLOTCLK
F3
I
DESCRIPTION
Virtual Channel 1 Enable: The chip provides the capability to support
virtual channel 1 (VC1), in addition to the standard virtual channel 0.
When this pin is asserted high, Virtual Channel 1 is enabled, and
virtual channel resource sharing is not available. When it is asserted
low, the chip would allocate the additional VC1 resource to VC0, and
VC1 capability is disabled. The pin has internal pull-down.
Slot Implemented: It decides if the downstream port is connected to
slot. SLOT_IMP [x] is correspondent to Portx, where x= 1,2,3.When
SLOT_IMP [x] is high, the Portx is connected to slot. By default,
downstream Port1, Port2, and Port3 are implemented with slots. The
pins have internal pull-up.
Hot Plug Capability: It determines if the downstream port is able to
support hot plug capability. HOTPLUG [x] is correspondent to Portx,
where x=1,2,3. When HOTPLUG [x] is high, Portx supports hot plug
operation. By default, downstream Port1, Port2, and Port3 are equipped
with hot plug function. The pins have internal pull-up.
Slot Clock Configuration: It determines if the all downstream
components uses the same physical reference clock that the platform
provides on the connector. When SLOTCLK is high, the platform
reference clock is employed. By default, all downstream ports use the
same physical reference clock provided by platform. The pins have
internal pull-up.
Page 12 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
3.3
3.4
HOT PLUG SIGNALS
NAME
PWR_IND [3:1]
PIN
N5, M5, L3
TYPE
O
ATT_IND [3:1]
M1, N1, N2
O
ATT_BTN [3:1]
K3, K2, K1
I
MRL_PDC [3:1]
N7, M7, J1
I
PWR_ENA_L [3:1]
P2, J2, H1
O
PWR_FLT [3:1]
N8, M8, P4
I
DESCRIPTION
Power Indicator: Indicates the power status for each slot at
downstream port. PWR_IND [x] is correspondent to Port x, where
x=1,2,3. They are active-high signals. The pins have internal pulldown.
Attention Indicator: Indicates the attention status for each slot at
downstream port. ATT_IND [x] is correspondent to Port x, where
x=1,2,3. They are active-high signals. ATT_IND[3:2] have internal
pull-down.
Attention Button: When asserted high, it represents the attention
button has been pressed for the slot at the downstream port. ATT_BTN
[x] is correspondent to Port x, where x=1,2,3.
Presence Detected Change: When asserted low, it represents the
device is present in the slot of downstream ports. Otherwise, it
represents the absence of the device. MRL_PDC [x] is correspondent
to Port x, where x=1,2,3.
SLOT Power Enable (Active LOW): Indicates the enable status of
the power connecting to the associated slot. PWR_ENA [x] is
correspondent to Portx, where x=1,2,3. They are active-low signals.
Pins are set to “000” by default.
SLOT Power Fault: When asserted high, it indicates a power fault on
one or more supply rails. PWR_FLT [x] is correspondent to Port x,
where x=1,2,3.
MISCELLANEOUS SIGNALS
NAME
EECLK
EEPD
P8
M9
PIN
TYPE
O
I/O
SMBCLK
N4
I
SMBDATA
SCAN_EN
L2
P10
I/O
I/O
PORTERR [3:0]
N9, P7, P6,
P5
O
GPIO [7:0]
F1, E1, G2,
G3, D1, C1,
F2, E2
I/O
TEST1
G1
I
TEST2
TEST3
TEST4
TEST5
TEST6
C3
C6
B6
A6
B11
I
I
TEST7
M6
I
NC
A10, A12,
A14, B10,
B12, B14,
H3, L1, M2,
M3, M4, N3
DESCRIPTION
EEPROM Clock: Clock signal to the EEPROM interface.
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin has internal pull-up.
SM Bus Clock: System management Bus Clock. Pin has an internal
pull-down.
SM Bus Data: Bi-Directional System Management Bus Data.
Full-Scan Enable Control: For normal operation, SCAN_EN is an
output with a value of “0”. SCAN_EN becomes an input during
manufacturing testing.
Port PHY Error Status: These pins are used to display the PHY Error
status of the ports. When PORTERR is flashing (alternating high and
low signals), it indicates that a PHY error is detected. When it is low,
no PHY error is detected. PORTERR [x] is correspondent to Port x,
where x=0,1,2,3.
General Purpose Input and Output: These eight general-purpose
pins are programmed as either input-only or bi-directional pins by
writing the GPIO output enable control register.
When SMBus is implemented, GPIO[7:5] act as the SMBus address
pins, which set Bit 2 to 0 of the SMBus address.
Test1: This pin is for internal test purpose. Test1 should be tied to
ground through a pull-down resistor.
Test2/3/4/5: These pins are for internal test purpose. Test2, Test3,
Test4 and Test5 should be tied to 3.3V through a pull-up resistor.
Test6: This pin is for internal test purpose. Test6 should be connected
an (475 ohm +/- 1%) external resistor to Vss.
Test7: This pin is for internal test purpose. Test7 should be tied to
ground through a pull-down resistor (5.1k ohm).
Not Connected: These pins can be just left open.
Page 13 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
3.5
3.6
JTAG BOUNDARY SCAN SIGNALS
NAME
TCK
PIN
M10
TYPE
I
TMS
P11
I
TDO
N10
O
TDI
N11
I
TRST_L
M11
I
DESCRIPTION
Test Clock: Used to clock state information and data into and out of
the chip during boundary scan. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
Test Mode Select: Used to control the state of the Test Access Port
controller. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be pulled low through a
5.1K pull-down resistor.
Test Data Output: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data out of the Test Access Port (TAP) in a serial bit
stream. When JTAG boundary scan function is not implemented, this
pin should be left open (NC).
Test Data Input: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data and instructions into the TAP in a serial bit
stream. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be left open (NC).
Test Reset (Active LOW): Active LOW signal to reset the TAP
controller into an initialized state. The pin has internal pull-up. When
JTAG boundary scan function is not implemented, this pin should be
pulled low through a 5.1K pull-down resistor.
POWER PINS
NAME
VDDC
VDDR
VDDA
VDDCAUX
VAUX
VTT
VSS
PIN
C7, F6, F7,
F9, G6, G7,
G9, H6, H7,
H9, J3, J6, J7,
J9
A4, A9, C12,
H2, N6, P13
C9, J12, J13,
J14, K13
D3, L13
A2
F12, M12
TYPE
P
DESCRIPTION
VDDC Supply (1.0V): Used as digital core power pins.
P
VDDR Supply (3.3V): Used as digital I/O power pins.
P
VDDA Supply (1.0V): Used as analog power pins.
P
P
P
A7, A11,
A13, B2, B7,
B9, B13, C8,
C10, C11,
C13, C14,
D13, E13, F8,
F13, F14, G8,
G13, H8,
H13, J8, M13,
M14, N13,
P1, P3, P9
P
VDDCAUX Supply (1.0V): Used as auxiliary core power pins.
VAUX Supply (3.3V): Used as auxiliary I/O power pins.
Transmit Termination Voltage (1.5V): Provides driver termination
voltage at transmitter. Should be given the same consideration as
VDDCAUX.
VSS Ground: Used as ground pins.
Page 14 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
4 PIN ASSIGNMENTS
4.1
PIN LIST of 148-PIN LFBGA
PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
NAME
WAKEUP_L
VAUX
DWNRST_L[2]
VDDR
HOTPLUG[3]
TEST5
VSS
REFCLKP
VDDR
NC
VSS
NC
VSS
NC
VC1_EN
VSS
DWNRST_L[3]
SLOT_IMP[3]
HOTPLUG[2]
TEST4
VSS
REFCLKN
VSS
NC
TEST6
NC
VSS
NC
GPIO[2]
DWNRST_L[1]
TEST2
SLOT_IMP[2]
HOTPLUG[1]
TEST3
VDDC
VSS
VDDA
PIN
C10
C11
C12
C13
C14
D1
D2
D3
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F6
F7
F8
F9
F12
F13
F14
G1
G2
G3
G6
G7
G8
G9
G12
G13
G14
NAME
VSS
VSS
VDDR
VSS
VSS
GPIO[3]
RESET_L
VDDCAUX
PERN[0]
VSS
PETP[0]
GPIO[6]
GPIO[0]
SLOT_IMP[1]
PERP[0]
VSS
PETN[0]
GPIO[7]
GPIO[1]
SLOTCLK
VDDC
VDDC
VSS
VDDC
VTT
VSS
VSS
TEST1
GPIO[5]
GPIO[4]
VDDC
VDDC
VSS
VDDC
PETN[3]
VSS
PERP[3]
PIN
H1
H2
H3
H6
H7
H8
H9
H12
H13
H14
J1
J2
J3
J6
J7
J8
J9
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M4
M5
Page 15 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
NAME
PWR_ENA_L[1]
VDDR
NC
VDDC
VDDC
VSS
VDDC
PETP[3]
VSS
PERN[3]
MRL_PDC[1]
PWR_ENA_L[2]
VDDC
VDDC
VDDC
VSS
VDDC
VDDA
VDDA
VDDA
ATT_BTN[1]
ATT_BTN[2]
ATT_BTN[3]
PETP[2]
VDDA
PERN[2]
NC
SMBDATA
PWR_IND[1]
PETN[2]
VDDCAUX
PERP[2]
ATT_IND[3]
NC
NC
NC
PWR_IND[2]
PIN
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
NAME
TEST7
MRL_PDC[2]
PWR_FLT[2]
EEPD
TCK
TRST_L
VTT
VSS
VSS
ATT_IND[2]
ATT_IND[1]
NC
SMBCLK
PWR_IND[3]
VDDR
MRL_PDC[3]
PWR_FLT[3]
PORTERR[3]
TDO
TDI
PERP[1]
VSS
PETN[1]
VSS
PWR_ENA_L[3]
VSS
PWR_FLT[1]
PORTERR[0]
PORTERR[1]
PORTERR[2]
EECLK
VSS
SCAN_EN
TMS
PERN[1]
VDDR
PETP[1]
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
5 FUNCTIONAL DESCRIPTION
Multiple virtual PCI-to-PCI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB
contains the complete PCIe architecture layers that consist of the physical, data link, and transaction layer. The
packets entering the Switch via one of VPPBs are first converted from serial bit-stream into parallel bus signals in
physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to
extract out the transaction header. According to the address or ID embedded in the transaction header, the entire
transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the
transmit circuits in the data link layer and physical layer. The following sections describe these function elements
for processing PCIe packets within the Switch.
5.1
PHYSICAL LAYER CIRCUIT
The physical layer circuit design is based on the PHY Interface for PCI Express Architecture (PIPE). It contains
Physical Media Attachment (PMA) and Physical Coding Sub-layer (PCS) blocks. PMA includes Serializer/
Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, beacon transmitter, electrical
idle detector, and input/output buffers. PCS consists of framer, 8B/10B encoder/decoder, receiver elastic buffer, and
PIPE PHY control/status circuitries. To provide the flexibility for port configuration, each lane has its own control
and status signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for
PHY built-in self test. The main functions of physical layer circuits include the conversion between serial-link and
parallel bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of
physical layer errors.
In order to meet the different application needs, the driving current and equalization of each transmitting channels
can be adjusted using EEPROM individually. The driver current of each channel is set to 20mA in default mode. To
change the current value, the user can program the EEPROM for nominal value (HIDRV, LODRV) or actual value
(DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current
values the chip provides.
Table 5-1 Nominal Driver Current Values (Inom)
HIDRV
0
0
1
1
LODRV
0
1
0
1
NOMINAL DRIVER CURENT
20 mA
10 mA
28 mA
Reserved
Table 5-2 Ratio of Actual Current and Nominal Current
DTX [3:0]
0000
0001
0010
0011
0100
0101
0110
1
ACTUAL CURRENT / NOMINAL CURRENT
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Multiple lanes could share the PLL.
Page 16 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
DTX [3:0]
0111
1000
1001
1010
1011
1100
1101
1110
1111
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
ACTUAL CURRENT / NOMINAL CURRENT
1.35
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
The equalization function of transmitting channels can optimize the driver current for different back-plane lengths
and materials. The table shown below lists the combinations of de-emphasized driver current (ITX –IEQ) to non-deemphasized driver current (ITX) for different values of DEQ [3:0].
Table 5-3 De-emphasis Level versus DEQ [3:0]
DEQ [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(ITX –IEQ) / ITX
1.00
0.96
0.92
0.88
0.84
0.80
0.76
0.72
0.68
0.64
0.60
0.56
0.52
0.48
0.44
0.40
De-emphasis (dB)
0.00
-0.35
-0.72
-1.11
-1.51
-1.94
-2.38
-2.85
-3.35
-3.88
-4.44
-5.04
-5.68
-6.38
-7.13
-7.96
By default, the DEQ is set to “1000” conform to the PCI Express 1.0a specification, which calls for a de-emphasis
level of between –3 dB and –4 dB.
In order to improve the data stream integrity across the channels, the receiver of each port of the Switch includes a
reception equalizer to mitigate the effects of ISI. The reception equalizer is implemented as a selectable high-pass
filter at the input node, and it is capable of removing as much as 0.4UI of ISI related jitter. The following table
shows a simple guideline for selecting the appropriate value to adapt with different lengths or connector numbers in
various applications.
Table 5-4 Rx Equalizer Settings (RXEQCTL)
RXEQCTL [1]
0
RXEQCTL [0]
0
Rx Eq Setting
Max Rx Eq
Input Jitter
> 0.25 UI
0
1
Min Rx Eq
1
X
Between 0.1 UI
and 0.25 UI
< 0.1 UI
Page 17 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
Channel Length
> 20" and two or more
connectors
Between 8'' and 20" and up to
two connectors
8" or less, up to one connector
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
5.2
DATA LINK LAYER (DLL)
The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK
protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is
protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the
incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK
data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be
sent out to acknowledge on reception of a good TLP.
In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK
DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller
than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is
returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is
triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted
after that packet.
Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit.
All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded
by 16-bit CRC to detect if data corruption occurs.
In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew,
scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is
implemented to interface physical layer with data link layer.
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION)
The receiving end of the transaction layer performs header information retrieval and TC/VC mapping (see section
5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain illegal header
or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an
error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the
TLP at the receiver if the digest bit is set in header.
5.4
ROUTING
The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing.
For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are
routed by their destination ID constituted of bus number, device number, and function number. Address routing is
employed to forward I/O or memory transactions to the destination port, which is located within the address range
indicated by the address field carried in the packet header. The packet header indicates the packet types including
memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message.
Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power
management, and so on. The message type embedded in the packet header determines the routing mechanism.
If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or
targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI
protocol.
Page 18 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
5.5
TC/VC MAPPING
The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the
differential service, a TC/VC mapping table at destination port that is pre-programmed by system software or
EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that TC0 traffic is
mapped into VC0 channel by default. After the TC/VC mapping, the receive block dispatches the incoming request,
completion, or data into the appropriate VC0 and VC1 queues.
5.6
QUEUE
In PCI Express, it defines six different packet types to represent request, completion, and data. They are respectively
Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted
Data Payload (NPD), Completion Header (CPLH) and Completion Data payload (CPLD). Each packet with
different type would be put into a separate queue in order to facilitate the following ordering processor. Since NPD
usually contains one DW, it can be merged with the corresponding NPH into a common queue named NPHD.
Except NPHD, each virtual channel (VC0 or VC1) has its own corresponding packet header and data queue. When
only VC0 is needed in some applications, VC1 can be disabled and its resources assigned to VC0 by asserting
VC1_EN (Virtual Channel 1 Enable) to low.
5.6.1
PH
PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header
space occupies sixteen bytes to accommodate 3 DW or 4 DW headers. There are two PH queues for VC0 and VC1
respectively.
5.6.2
PD
PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined
to have payload coming with the header, the payload data would be put into PD queue. There are two PD queues for
VC0 and VC1 respectively.
5.6.3 NPHD
NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO
write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW
header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data. There is only one
NPHD queue for VC0, since non-posted request cannot be mapped into VC1.
5.6.4 CPLH
CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to
accommodate a 3-DW header. Please note that there is no 4-DW completion headers. There are two CPLH queues
for VC0 and VC1 respectively.
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June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
5.6.5 CPLD
CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to
have payload coming with the header, the payload data would be put into CPLD queue. There are two CPLD queues
for VC0 and VC1 respectively.
5.7
TRANSACTION ORDERING
Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including
Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer
model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering
requirement among transactions within different TC labels. Since the transactions with the same TC label are not
allowed to map into different virtual channels, it implies no ordering relationship between the traffic in VC0 and
VC1.
Table 5-4 Summary of PCI Express Ordering Rules
Row Pass Column
Posted Request
Read Request
Non-posted Write Request
Read Completion
Non-Posted Write
Completion
Posted
Request
Yes/No1
No2
No2
Yes/No3
Yes4
Read
Request
Yes5
Yes
Yes
Yes
Yes
Non-posted Write
Request
Yes5
Yes
Yes
Yes
Yes
Read
Completion
Yes5
Yes
Yes
Yes
Yes
Non-posted Write
Completion
Yes5
Yes
Yes
Yes
Yes
1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and
message request must complete on the egress bus of VPPB in the order in which they are received on the ingress
bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted
Requests occurring before it.
2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push
the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read
Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data.
Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data.
3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ‘‘pull’’ ahead of previously queued
posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the
posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted
transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If
the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory
Write or Message Request.
4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction.
Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship.
5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as
Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions
are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write
queue and the Non-posted transaction queue.
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June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
5.8
PORT ARBITRATION
Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be
forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted
Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC
channel. It means that each port has two port arbitration circuitries for VC0 and VC1 respectively. At upstream port,
in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the
arbitration loop to get the service in Virtual Channel 0.
5.9
VC ARBITRATION
After port arbitration, VC arbitration is executed among different VC channels within the same source. Three
arbitration algorithms are provided to choose the appropriate VC. They are respectively Strict Priority, Round Robin
or Weighted Round Robin.
5.10 FLOW CONTROL
PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient. The
transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has
enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free
buffer space to an opposite transmitter to avoid packet stale. In this switch, each port has separate queues for
different traffic types and the credits are on the fly sent to data link layer, which compares the current available
credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the
credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at
each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other
ingress ports for gating the packet transmission.
5.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION)
The transmit portion of transaction layer performs the following functions. They are to construct the all types of
forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e.
configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an
upstream port.
Page 21 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS
The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bi-directional
serial data). The Switch may control an ISSI IS24C04 or compatible parts using into 512x8 bits. The EEPROM is
used to initialize a number of registers before enumeration. This is accomplished after PRST# is de-asserted, at
which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the
Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address input. It can
only access the EEPROM with address input set to 0.
The System Management Bus interface consists of two pins: SMBCLK (System Management Bus Clock input) and
SMBDATA (System Management Bus Data input/ output).
6.1
EEPROM INTERFACE
6.1.1 AUTO MODE EERPOM ACCESS
The Switch may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer.
The EEPROM start-control, address, and read/write commands can be accessed through the configuration register.
Before each access, the software should check the Autoload Status bit before issuing the next start.
6.1.2 EEPROM MODE AT RESET
During a reset, the Switch will automatically load the information/data from the EEPROM if the automatic load
condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload
initiates right after the reset.
During the autoload, the Bridge will read sequential words from the EEPROM and write to the appropriate registers.
Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading
bit [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0'
which indicates that the autoload initialization sequence is complete.
6.1.3 EEPROM SPACE ADDRESS MAP
15 – 8
7–0
EEPROM Signature (1516h)
Vendor ID
Device ID
Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port 1 ~ 3
Subsystem Vender ID
Subsystem ID
Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm
Difference
Reserved
PM Data for Port 0
PM Capability for Port 0
PM Data for Port 1
PM Capability for Port 1
PM Data for Port 2
PM Capability for Port 2
PM Data for Port 3
PM Capability for Port 3
Reserved
Reserved
Reserved
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Pericom Semiconductor
BYTE OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
15 – 8
7–0
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BYTE OFFSET
Reserved
TC/VC Map for Port 0 (VC0)
Slot Clock / LPVC Count / Port Num, Port 0
TC/VC Map for Port 1(VC0)
Slot Implemented / Slot Clock / LPVC Count
/ Port Num, Port 1
TC/VC Map for Port 2 (VC0)
Slot Implemented / Slot Clock / LPVC Count
/ Port Num, Port 2
TC/VC Map for Port 3 (VC0)
Slot Implemented / Slot Clock / LPVC Count
/ Port Num, Port 3
Reserved
Reserved
Reserved
Reserved
Reserved
Slot Capability 0 for Port 1
Slot Capability 0 for Port 2
Slot Capability 0 for Port 3
Reserved
Reserved
Reserved
Reserved
Reserved
Slot Capability 1 for Port 1
Slot Capability 1 for Port 2
Slot Capability 1 for Port 3
Reserved
Reserved
Reserved
Reserved
TC/VC Map for Port 0 (VC1)
Maximum Time Slot for Port 0
TC/VC Map for Port 1 (VC1)
Maximum Time Slot for Port 1
TC/VC Map for Port 2 (VC1)
Maximum Time Slot for Port 2
TC/VC Map for Port 3 (VC1)
Maximum Time Slot for Port 3
Reserved
Reserved
Reserved
Reserved
Power Budgeting Capability Register for Port 0
Power Budgeting Capability Register for Port 1
Power Budgeting Capability Register for Port 2
Power Budgeting Capability Register for Port 3
Reserved
Reserved
Reserved
Reserved
Replay Time-out Counter for Port 0
Replay Time-out Counter for Port 1
Replay Time-out Counter for Port 2
Replay Time-out Counter for Port 3
Reserved
Reserved
Reserved
Reserved
Acknowledge Latency Timer for Port 0
Acknowledge Latency Timer for Port 1
Acknowledge Latency Timer for Port 2
Acknowledge Latency Timer for Port 3
Reserved
Reserved
Reserved
Reserved
PHY Parameter for Port 0
PHY Parameter for Port 1
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June 2009 – Revision 1.6
Pericom Semiconductor
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
15 – 8
Reserved
Reserved
Reserved
Reserved
7–0
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BYTE OFFSET
PHY Parameter for Port 2
PHY Parameter for Port 3
Reserved
Reserved
Reserved
Reserved
PM Control Para/Rx Polarity for Port 0
PM Control Para/Rx Polarity for Port 1
PM Control Para/Rx Polarity for Port 2
PM Control Para/Rx Polarity for Port 3
94h
96h
98h
9Ah
9Ch
9Eh
A0h
A2h
A4h
A6h
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS
ADDRESS
00h
02h
04h
06h
08h
0Ah
0Ch
PCI CFG
OFFSET
DESCRIPTION
00h ~ 01h
02h ~ 03h
144h (Port 0~3)
144h: Bit [0]
EEPROM signature – 1516h
Vendor ID
Device ID
Extended VC Count for Port 0 ~ 3
Bit [0]: It represents the supported VC count other than the
default VC
ECh (Port 0~3)
ECh: Bit [14:12]
ECh: Bit [17:15]
Link Capability for Port 0 ~ 3
Bit [3:1]: It represents L0s Exit Latency for all ports
Bit [6:4]: It represents L1 Exit Latency for all ports
B4h (Port 0~3)
B4h:Bit [5]
Bit [6]
Bit [0]
Bit [2:1]
Bit [3]
Bit [4]
Switch Mode Operation for Port 0
Bit [8]: no ordering on packets for different egress port mode
Bit [9]: no ordering on different tag of completion mode
Bit [10]: Store and Forward
Bit [12:11]: Cut-through Threshold
Bit [13] : Port arbitrator Mode
Bit [14]: Credit Update Mode
3Ch (Port 1~3)
3Ch: Bit [8]]
BCh: Bit [15:0]
BCh: Bit [31:16]
E4h(Port 0~3)
E4h: Bit 0
Interrupt pin for Port 1 ~ 3
Bit [15]: Set when INTA is requested for interrupt resource
Subsystem Vender ID
Subsystem ID
Max_Payload_Size Support for Port 0 ~ 3
Bit [0]: Indicated the maximum payload size that the device can
support for the TLP
ECh(Port 0~3)
ECh: Bit[11:10]
ASPM Support for Port 0 ~ 3
Bit [2:1] : Indicate the level of ASPM supported on the PCIe link
E4h(Port 0~3)
E4h: Bit[15]
Role_Base Error Reporting for Port 0 ~ 3
Bit [3] : Indicate implement the role-base error reporting
B0h(port 0~3)
B0h : Bit [14]
MSI Capability Disable for Port 0~3
Bit [4] : Disable MSI capability
B0h(port 0~3)
B0h : Bit [15]
AER Capability Disable for Port 0~3
Bit [5] : Disable AER capability
B4h(port 0~3)
B4h : Bit [15]
Compliance Pattern Parity Control Disable for Port 0~3
Bit [6] : Disable compliance pattern parity
B0h(port 0~3)
B0h : Bit [13]
Power Management Capability Disable for Port 0~3
Bit [7] : Disable Power Management Capability
A8h(Port 0~3)
RefClk ppm Difference for Port 0 ~ 3
Page 24 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
ADDRESS
PCI CFG
OFFSET
A8h: Bit [14:13]
10h
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
11h
12h
80h: Bit [29:28]
84h (Port 0)
84h: Bit [31:24]
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
13h
14h
80h: Bit [29:28]
84h (Port 1)
84h: Bit [31:24]
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
15h
16h
80h: Bit [29:28]
84h (Port 2)
84h: Bit [31:24]
84h (Port 3)
84h: Bit [3]
80h (Port 3)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
17h
20h
80h: Bit [29:28]
84h (Port 3)
84h: Bit [31:24]
F0h (Port 0)
F0h: Bit [28]
DESCRIPTION
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
No_Soft_Reset for Port 0
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Power Management Data for Port 0
Bit [15:8]: read only as Data register
No_Soft_Reset for Port 1
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Power Management Data for Port 1
Bit [15:8] – read only as Data register
No_Soft_Reset for Port 2
Bit [0]: No_Soft_Reset
Power Management Capability for Port 2
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Power Management Data for Port 2
Bit [15:8] – read only as Data register
No_Soft_Reset for Port 3
Bit [0]: No_Soft_Reset
Power Management Capability for Port 3
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Power Management Data for Port 3
Bit [15:8] – read only as Data register
Slot Clock Configuration for Port 0
Bit [1]: When set, the component uses the clock provided on the
connector
80h (Port 0)
80h: Bit[21]
Device specific Initialization for Port 0
Bit [2]: When set, the DSI is required
144h (Port 0)
144h: Bit [4]
LPVC Count for Port 0
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 0
ECh (Port 0)
ECh: Bit [25:24]
Port Number for Port 0
Bit [5:4]: It represents the logic port numbering for physical port
0
Page 25 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
ADDRESS
22h
PCI CFG
OFFSET
DESCRIPTION
154h (Port 0)
154h: Bit [7:1]
VC0 TC/VC Map for Port 0
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
PCIe Capability Slot Implemented for Port 1
Bit [0]: When set, the slot is implemented for Port 1
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
Slot Clock Configuration for Port 1
Bit [1]: When set, the component uses the clock provided on the
Connector
80h (Port 1)
80h: Bit[21]
Device specific Initialization for Port 1
Bit [2]: When set, the DSI is required
144h (Port 1)
144h: Bit [4]
LPVC Count for Port 1
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 1
ECh (Port 1)
ECh: Bit [25:24]
Port Number for Port 1
Bit [5:4]: It represents the logic port numbering for physical port
1
VC0 TC/VC Map for Port 1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
PCIe Capability Slot Implemented for Port 2
Bit [0]: When set, the slot is implemented for Port 2
154h (Port 1)
154h: Bit [7:1]
24h
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
Slot Clock Configuration for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
80h (Port 2)
80h: Bit[21]
Device specific Initialization for Port 2
Bit [2]: When set, the DSI is required
144h (Port 2)
144h: Bit [4]
LPVC Count for Port 2
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2
ECh (Port 2)
ECh: Bit [25:24]
Port Number for Port 2
Bit [5:4]: It represents the logic port numbering for physical port
2
VC0 TC/VC Map for Port 2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
PCIe Capability Slot Implemented for Port 3
Bit [0]: When set, the slot is implemented for Port 3
154h (Port 2)
154h: Bit [7:1]
26h
E0h (Port 3)
E0h: Bit [24]
F0h (Port 3)
F0h: Bit [28]
Slot Clock Configuration for Port 3
Bit [1]: When set, the component uses the clock provided on the
Connector
80h (Port 3)
80h: Bit[21]
Device specific Initialization for Port 3
Bit [2]: When set, the DSI is required
144h (Port 3)
144h: Bit [4]
LPVC Count for Port 3
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 3
ECh (Port 3)
ECh: Bit [25:24]
Port Number for Port 3
Bit [5:4]: It represents the logic port numbering for physical port
3
VC0 TC/VC Map for Port 3
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Slot Capability 0 of Port 1
Bit [15:0]: Mapping to the low word of slot capability register
Slot Capability 0 of Port 2
Bit [15:0]: Mapping to the low word of slot capability register
154h (Port 3)
154h: Bit [7:1]
32h
34h
F4h (Port 1)
F4h: Bit [15:0]
F4h (Port 2)
F4h: Bit [15:0]
Page 26 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
ADDRESS
36h
42h
44h
46h
50h
PCI CFG
OFFSET
DESCRIPTION
F4h (Port 3)
F4h: Bit [15:0]
F4h (Port 1)
F4h: Bit [31:16]
F4h (Port 2)
F4h: Bit [31:16]
F4h (Port 3)
F4h: Bit [31:16]
15Ch (Port 0)
15Ch– Bit [22:16]
160h– Bit [7:0]
Slot Capability 0 of Port 3
Bit [15:0]: Mapping to the low word of slot capability register
Slot Capability 1 of Port 1
Bit [15:0]: Mapping to the high word of slot capability register
Slot Capability 1 of Port 2
Bit [15:0]: Mapping to the high word of slot capability register
Slot Capability 1 of Port 3
Bit [15:0]: Mapping to the high word of slot capability register
VC1 MAX Time Slot and TC/VC Map for Port 0
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into VC1
VC1 MAX Time Slot and TC/VC Map for Port 1
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into VC1
VC1 MAX Time Slot and TC/VC Map for Port 2
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into
VC1
VC1 MAX Time Slot and TC/VC Map for Port 3
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC mapped
into VC1
Power Budget Register for Port 0
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Power Budget Register for Port 1
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Power Budget Register for Port 2
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Power Budget Register for Port 3
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
Replay Time-out Counter for Port 0
Bit [15:0]: Relay Time-out Counter
Replay Time-out Counter for Port 1
Bit [15:0]: Relay Time-out Counter
Replay Time-out Counter for Port 2
Bit [15:0]: Relay Time-out Counter
Replay Time-out Counter for Port 3
Bit [15:0]: Relay Time-out Counter
Acknowledge Latency Timer for Port 0
Bit [31:16]: Acknowledge Latency Timer
Acknowledge Latency Timer for Port 1
Bit [31:16]: Acknowledge Latency Timer
Acknowledge Latency Timer for Port 2
Bit [31:16]: Acknowledge Latency Timer
Acknowledge Latency Timer for Port 3
Bit [31:16]: Acknowledge Latency Timer
PHY Parameter for Port 0
Bit [31:16]: PHY Parameter
52h
15Ch (Port 1)
15Ch– Bit [22:16]
160h– Bit [7:0]
54h
15Ch (Port 2)
15Ch– Bit [22:16]
160h– Bit [7:0]
56h
15Ch (Port 3)
15Ch– Bit [22:16]
160h– Bit [7:0]
60h
214h (Port 0)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 1)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 2)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
214h (Port 3)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
B0h (Port 0)
B0h – Bit [15:0]
B0h (Port 1)
B0h – Bit [15:0]
B0h (Port 2)
B0h – Bit [15:0]
B0h (Port 3)
B0h – Bit [15:0]
B0h (Port 0)
B0h – Bit [31:16]
B0h (Port 1)
B0h – Bit [31:16]
B0h (Port 2)
B0h – Bit [31:16]
B0h (Port 3)
B0h – Bit [31:16]
B4h (Port 0)
B4h: Bit [31:16]
62h
64h
66h
70h
72h
74h
76h
80h
82h
84h
86h
90h
Page 27 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
ADDRESS
92h
94h
96h
A0h
PCI CFG
OFFSET
DESCRIPTION
B4h (Port 1)
B4h: Bit [31:16]
B4h (Port 2)
B4h: Bit [31:16]
B4h (Port 3)
B4h: Bit [31:16]
B4h (Port 0)
B4h: Bit [13:8]
B4h (Port 0)
B4h : Bit [14]
PHY Parameter for Port 1
Bit [31:16]: PHY Parameter
PHY Parameter for Port 2
Bit [31:16]: PHY Parameter
PHY Parameter for Port 3
Bit [31:16]: PHY Parameter
PM Control Parameter for Port 0
Bit [5:4] : L0s enable
Bit [3:2] : L1 delay count select
Bit [1:0] : D3 enters L1
Rx Polarity Inversion Disable for port 0
Bit [6] : Disable Rx polarity capability
PM Control Parameter for Port 1
Bit [5:4] : L0s enable
Bit [3:2] : L1 delay count select
Bit [1:0] : D3 enters L1
Rx Polarity Inversion Disable for port 1
Bit [6] : Disable Rx polarity capability
PM Control Parameter for Port 2
Bit [5:4] : L0s enable
Bit [3:2] : L1 delay count select
Bit [1:0] : D3 enters L1
Rx Polarity Inversion Disable for port 2
Bit [6] : Disable Rx polarity capability
PM Control Parameter for Port 3
Bit [5:4] : L0s enable
Bit [3:2] : L1 delay count select
Bit [1:0] : D3 enters L1
Rx Polarity Inversion Disable for port 3
Bit [6] : Disable Rx polarity capability
A2h
B4h (Port 1)
B4h: Bit [13:8]
B4h (Port 1)
B4h : Bit [14]
A4h
B4h (Port 2)
B4h: Bit [13:8]
B4h (Port 2)
B4h : Bit [14]
A6h
B4h (Port 3)
B4h: Bit [13:8]
B4h (Port 3)
B4h : Bit [14]
Page 28 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
6.2
SMBus INTERFACE
The PI7C9X20404GP provides the System Management Bus (SMBus), a two-wire interface through which a simple
device can communicate with the rest of the system. The SMBus interface on the PI7C9X20404GP is a bidirectional slave interface. It can receive data from the SMBus master or send data to the master. The interface
allows full access to the configuration registers. A SMBus master, such as the processor or other SMBus devices,
can read or write to every RW configuration register (read/write register). In addition, the RO and HwInt registers
(read-only and hardware initialized registers) that can be auto-loaded by the EEPROM interface can also be read
and written by the SMBus interface. This feature allows increases in the system expandability and flexibility in
system implementation.
Figure 6-1 SMBus Architecture Implementation on PI7C9X20404GP
Processor
(SMBus Master)
PI6C9X20404GP
Other SMBus
Devices
SMBCLK
SMBDATA
The SMBus interface on the PI7C9X20404GP consists of one SMBus clock pin (SMBCLK), a SMBus data pin
(SMBDATA), and 3 SMBus address pins (GPIO[5:7]). The SMBus clock pin provides or receives the clock signal.
The SMBus data pin facilitates the data transmission and reception. Both of the clock and data pins are bidirectional. The SMBus address pins determine the address to which the PI7C9X20404GP responds to. The SMBus
address pins generate addresses according to the following table:
Table 6-1 SMBus Address Pin Configuration
BIT
0
1
2
3
4
5
6
SMBus Address
GPIO[5]
GPIO[6]
GPIO[7]
1
0
1
1
Page 29 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7 REGISTER DESCRIPTION
7.1
REGISTER TYPES
REGISTER TYPE
HwInt
RO
RW
RWC
RWCS
RWS
ROS
7.2
DEFINITION
Hardware Initialization
Read Only
Read / Write
Read / Write 1 to Clear
Sticky - Read Only / Write 1 to Clear
Sticky - Read / Write
Sticky – Read Only
TRANSPARENT MODE CONFIGURATION REGISTERS
When the port of switch is set to operate at the transparent mode, it is represented by a logical PCI-toPCI bridge that implements type 1 configuration space header. The following table details the
allocation of the register fields of the PCI 2.3 compatible type 1 configuration space header.
31 –24
23 – 16
15 - 8
Device ID
Primary Status
7 –0
Vendor ID
Command
Revision ID
Primary Latency Timer
Cache Line Size
Reserved
Secondary Latency
Subordinate Bus
Secondary Bus
Primary Bus Number
Timer
Number
Number
Secondary Status
I/O Limit Address
I/O Base Address
Memory Limit Address
Memory Base Address
Prefetchable Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Base Address Upper 32-bit
Prefetchable Memory Limit Address Upper 32-bit
I/O Limit Address Upper 16-bit
I/O Base Address Upper 16-bit
Reserved
Capability Pointer to
80h
Reserved
Bridge Control
Interrupt Pin
Interrupt Line
Reserved
Power Management Capabilities
Next Item Pointer=8C
Capability ID=01
PM Data
PPB Support
Power Management Data
Extensions
Message Control
Next Item Pointer=9C
Capability ID=05
Message Address
Message Upper Address
Reserved
Message Data
VPD Register
Next Item Pointer=A4
Capability ID=03
VPD Data Register
Length in Bytes (14h)
Next Item Pointer=B8
Capability ID=09
XPIP_CSR0
XPIP_CSR1
ACK Latency Timer
Replay Time-out Counter
Reserved
Forwarding Modes
Reserved
Next Item Pointer=E0
SSID/SSVID
Capability ID=0D
SSID
SSVID
Reserved
GPIO Data and Control
Reserved
Class Code
Header Type
Page 30 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BYTE OFFSET
00h
04h
08h
0Ch
10h – 17h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h – 7Fh
80h
84h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h – D7h
D8h
31 –24
23 – 16
EEPROM Data
PCI Express Capabilities Register
Device Status
Link Status
Slot Status
15 - 8
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7 –0
BYTE OFFSET
EEPROM Address
EEPROM Control
Next Item Pointer=00
Capability ID=10
Device Capabilities
Device Control
Link Capabilities
Link Control
Slot Capabilities
Slot Control
Reserved
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
Other than the PCI 2.3 compatible configuration space header, the Switch also implements PCI
express extended configuration space header, which includes advanced error reporting, virtual channel,
and power budgeting capability registers. The following table details the allocation of the register
fields of PCI express extended capability space header. The first extended capability always begins at
offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at
an offset greater than 0FFh relative to the beginning of PCI compatible configuration space.
31 –24
23 – 16
15 - 8
Next Capability Offset=140h
7 –0
Cap.
PCI Express Extended Capability ID=0001h
Version
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask Register
Advanced Error Capabilities and Control Register
Header Log Register
Reserved
Next Capability Offset=20Ch
Cap.
PCI Express Extended Capability ID=0002h
Version
Port VC Capability Register 1
VC Arbitration Table
Port VC Capability Register 2
Offset=3
Port VC Status Register
Port VC Control Register
Port Arbitration Table
VC Resource Capability Register (0)
Offset=4
VC Resource Control Register (0)
VC Resource Status Register (0)
Reserved
Port Arbitration Table
VC Resource Capability Register (1)
Offset=6
VC Resource Control Register (1)
VC Resource Status Register (1)
Reserved
Reserved
VC Arbitration Table with 32 Phases
Port Arbitration Table with 128 Phases for VC0
Port Arbitration Table with 128 Phases for VC1
Reserved
Next Capability Offset=000h
Cap.
PCI Express Extended Capability ID=0004h
Version
Reserved
Data Select Register
Data Register
Reserved
Power Budget
Capability Register
Page 31 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BYTE OFFSET
100h
104h
108h
10Ch
110h
114h
118h
11Ch – 128h
12Ch – 13Fh
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
16Ch – 168h
170h – 17Ch
180h – 1BCh
1C0h – 1FCh
200h – 20Bh
20Ch
210h
214h
218h
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.1
VENDOR ID REGISTER – OFFSET 00h
BIT
15:0
FUNCTION
Vendor ID
TYPE
RO
DESCRIPTION
Identifies Pericom as the vendor of this device. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 12D8h.
7.2.2
DEVICE ID REGISTER – OFFSET 00h
BIT
31:16
FUNCTION
Device ID
TYPE
RO
DESCRIPTION
Identifies this device as the PI7C9X20404GP. The default value may be
changed by SMBus or auto-loading from EEPROM.
Resets to 0404h.
7.2.3
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
0
I/O Space Enable
1
Memory Space
Enable
TYPE
RW
RW
2
Bus Master Enable
RW
3
Special Cycle Enable
Memory Write And
Invalidate Enable
VGA Palette Snoop
Enable
RO
4
5
RO
RO
6
Parity Error
Response Enable
RW
7
Wait Cycle Control
RO
8
SERR# enable
RW
9
Fast Back-to-Back
Enable
10
Interrupt Disable
RO
RW
DESCRIPTION
0b: Ignores I/O transactions on the primary interface
1b: Enables responses to I/O transactions on the primary interface
Resets to 0b.
0b: Ignores memory transactions on the primary interface
1b: Enables responses to memory transactions on the primary interface
Reset to 0b.
0b: Does not initiate memory or I/O transactions on the upstream port and
handles as an Unsupported Request (UR) to memory and I/O transactions
on the downstream port. For Non-Posted Requests, a completion with UR
completion status must be returned
1b: Enables the Switch Port to forward memory and I/O Read/Write
transactions in the upstream direction
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
0b: Switch may ignore any parity errors that it detects and continue normal
operation
1b: Switch must take its normal action when a parity error is detected
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0.
0b: Disables the reporting of Non-fatal and Fatal errors detected by the
Switch to the Root Complex
b1: Enables the Non-fatal and Fatal error reporting to Root Complex
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the ability of a PCI Express device to generate INTx Interrupt
Messages. In the Switch, this bit does not affect the forwarding of INTx
messages from the downstream ports.
Reset to 0b.
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June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
15:11
7.2.4
FUNCTION
Reserved
TYPE
RO
DESCRIPTION
Reset to 0b.
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
18:16
FUNCTION
Reserved
19
Interrupt Status
RO
20
Capabilities List
RO
21
22
66MHz Capable
Reserved
Fast Back-to-Back
Capable
RO
RO
23
TYPE
RO
RO
DESCRIPTION
Reset to 000b.
Indicates that an INTx Interrupt Message is pending internally to the device.
In the Switch, the forwarding of INTx messages from the downstream device
of the Switch port is not reflected in this bit. Must be hardwired to 0b.
Set to 1 to enable support for the capability list (offset 34h is the pointer to
the data structure).
Reset to 1b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the primary side of the port in a Switch.
24
Master Data Parity
Error
RWC
26:25
DEVSEL# timing
RO
27
Signaled Target
Abort
RO
28
29
30
31
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity Error
RO
RO
RWC
RWC
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request on the primary side
using the Completer Abort Completion Status.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status on the primary side.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status on primary side.
Reset to 0b.
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Command register is 1.
Reset to 0b.
Set to 1 whenever the primary side of the port in a Switch receives a Poisoned
TLP.
Reset to 0b.
7.2.5
REVISION ID REGISTER – OFFSET 08h
BIT
7:0
7.2.6
FUNCTION
Revision
TYPE
RO
DESCRIPTION
Indicates revision number of device. Hardwired to 01h.
CLASS CODE REGISTER – OFFSET 08h
BIT
15:8
23:16
31:24
FUNCTION
Programming
Interface
Sub-Class Code
Base Class Code
TYPE
RO
RO
RO
DESCRIPTION
Read as 00h to indicate no programming interfaces have been defined for
PCI-to-PCI Bridges.
Read as 04h to indicate device is a PCI-to-PCI Bridge.
Read as 06h to indicate device is a Bridge device.
Page 33 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
7:0
Cache Line Size
TYPE
RW
DESCRIPTION
The cache line size register is set by the system firmware and the operating
system cache line size. This field is implemented by PCI Express devices as a
RW field for legacy compatibility, but it has no impact on any PCI Express
device functionality.
Reset to 0b.
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
15:8
7.2.9
7.2.10
FUNCTION
Primary Latency
timer
TYPE
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
23:16
Header Type
RO
DESCRIPTION
Read as 01h to indicate that the register layout conforms to the standard PCIto-PCI Bridge layout.
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
7:0
Primary Bus Number
TYPE
RW
DESCRIPTION
Indicates the number of the PCI bus to which the primary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
15:8
Secondary Bus
Number
TYPE
RW
DESCRIPTION
Indicates the number of the PCI bus to which the secondary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
23:16
Subordinate Bus
Number
TYPE
RW
DESCRIPTION
Indicates the number of the PCI bus with the highest number that is
subordinate to the Bridge. The value is set in software during configuration.
Reset to 00h.
Page 34 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
31:24
7.2.14
FUNCTION
Secondary Latency
Timer
TYPE
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
3:0
FUNCTION
32-bit Indicator
7:4
I/O Base Address
[15:12]
TYPE
RO
RW
DESCRIPTION
Read as 01h to indicate 32-bit I/O addressing.
Defines the bottom address of the I/O address range for the Bridge to
determine when to forward I/O transactions from one interface to the other.
The upper 4 bits correspond to address bits [15:12] and are writable. The
lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The
upper 16 bits corresponding to address bits [31:16] are defined in the I/O base
address upper 16 bits address register.
Reset to 0h.
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
BIT
11:8
FUNCTION
32-bit Indicator
15:12
I/O Limit Address
[15:12]
TYPE
RO
RW
DESCRIPTION
Read as 01h to indicate 32-bit I/O addressing.
Defines the top address of the I/O address range for the Bridge to determine
when to forward I/O transactions from one interface to the other. The upper 4
bits correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16
bits corresponding to address bits [31:16] are defined in the I/O limit address
upper 16 bits address register.
Reset to 0h.
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
20:16
21
22
23
FUNCTION
Reserved
66MHz Capable
Reserved
Fast Back-to-Back
Capable
TYPE
RO
RO
RO
RO
DESCRIPTION
Reset to 00000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the secondary side of the port in a Switch.
24
Master Data Parity
Error
RWC
26:25
DEVSEL_L timing
RO
27
Signaled Target
Abort
RO
28
Received Target
Abort
RO
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request in the secondary side
using Completer Abort Completion Status.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status in the secondary side.
Reset to 0b.
Page 35 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
29
Received Master
Abort
30
31
Received System
Error
Detected Parity Error
TYPE
RO
RWC
RWC
DESCRIPTION
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status in secondary side.
Reset to 0b.
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Bridge Control register is 1.
Reset to 0b.
Set to 1 whenever the secondary side of the port in a Switch receives a
Poisoned TLP.
Reset to 0b.
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
BIT
3:0
FUNCTION
Reserved
15:4
Memory Base
Address [15:4]
TYPE
RO
RW
DESCRIPTION
Reset to 0h.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory transactions from one interface to the other. The
upper 12 bits correspond to address bits [31:20] and are able to be written to.
The lower 20 bits corresponding to address bits [19:0] are assumed to be 0.
Reset to 000h.
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
BIT
19:16
FUNCTION
Reserved
31:20
Memory Limit
Address [31:20]
TYPE
RO
RW
DESCRIPTION
Reset to 0h.
Defines the top address of an address range for the Bridge to determine when
to forward memory transactions from one interface to the other. The upper
12 bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
Reset to 000h.
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
BIT
3:0
FUNCTION
64-bit addressing
15:4
Prefetchable Memory
Base Address [31:20]
TYPE
RO
RW
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be 0. The memory base register upper 32
bits contain the upper half of the base address.
Reset to 000h.
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
BIT
19:16
FUNCTION
64-bit addressing
TYPE
RO
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
Page 36 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
31:20
Prefetchable Memory
Limit Address
[31:20]
TYPE
RW
DESCRIPTION
Defines the top address of an address range for the Bridge to determine when
to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits
register contains the upper half of the limit address.
Reset to 000h.
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER
– OFFSET 28h
BIT
FUNCTION
31:0
Prefetchable Memory
Base Address, Upper
32-bits [63:32]
TYPE
RW
DESCRIPTION
Defines the upper 32-bits of a 64-bit bottom address of an address range for
the Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
7.2.22
7.2.23
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER
– OFFSET 2Ch
BIT
FUNCTION
31:0
Prefetchable Memory
Limit Address,
Upper 32-bits
[63:32]
TYPE
RW
DESCRIPTION
Defines the upper 32-bits of a 64-bit top address of an address range for the
Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
15:0
I/O Base Address,
Upper 16-bits
[31:16]
TYPE
RW
DESCRIPTION
Defines the upper 16-bits of a 32-bit bottom address of an address range for
the Bridge to determine when to forward I/O transactions from one interface
to the other.
Reset to 0000h.
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
31:16
I/O Limit Address,
Upper 16-bits
[31:16]
TYPE
RW
DESCRIPTION
Defines the upper 16-bits of a 32-bit top address of an address range for the
Bridge to determine when to forward I/O transactions from one interface to
the other.
Reset to 0000h.
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
7:0
Capability Pointer
TYPE
RO
DESCRIPTION
Pointer points to the PCI power management registers (80h).
Page 37 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
7.2.26
TYPE
DESCRIPTION
Reset to 80h.
INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
7:0
7.2.27
FUNCTION
FUNCTION
Interrupt Line
TYPE
RW
DESCRIPTION
Reset to 00h.
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
15:8
Interrupt Pin
RO
DESCRIPTION
The Switch implements INTA virtual wire interrupt signals to represent hotplug events at downstream ports. The default value on the downstream ports
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
16
Parity Error
Response
RW
17
18
S_SERR# enable
ISA Enable
RW
RW
DESCRIPTION
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
Reset to 0b.
0b: Forwards downstream all I/O addresses in the address range defined by
the I/O Base, I/O Base, and Limit registers
1b: Forwards upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
Reset to 0b.
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
19
VGA Enable
RW
20
VGA 16-bit decode
RW
21
Master Abort Mode
RO
22
Secondary Bus Reset
RW
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
Does not apply to PCI Express. Must be hardwired to 0b.
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
Reset to 0b.
Page 38 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
23
24
25
26
27
31:28
7.2.29
TYPE
RO
RO
RO
RO
RO
RO
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0h.
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
7:0
7.2.30
FUNCTION
Fast Back-to-Back
Enable
Primary Master
Timeout
Secondary Master
Timeout
Master Timeout
Status
Discard Timer
SERR# enable
Reserved
FUNCTION
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 01h to indicate that these are power management enhanced capability
registers.
NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
RO
DESCRIPTION
At upstream ports, the pointer points to the Vital Protocol Data (VPD)
capability register (9Ch).
At downstream ports, the pointer points to the Message capability register
(8Ch).
Reset to 9Ch (Upstream port).
Reset to 8Ch (Downstream port).
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
18:16
19
20
TYPE
RO
RO
RO
21
Device Specific
Initialization
RO
24:22
AUX Current
RO
25
26
31:27
7.2.32
FUNCTION
Power Management
Revision
PME# Clock
Reserved
D1 Power State
Support
D2 Power State
Support
PME# Support
RO
RO
RO
DESCRIPTION
Read as 011b to indicate the device is compliant to Revision 1.2 of PCI
Power Management Interface Specifications.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Read as 0b to indicate Switch does not have device specific initialization
requirements. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default
value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Switch supports the D1 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Switch supports the D2 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 11111b to indicate Switch supports the forwarding of PME# message
in all power states. The default value may be changed by SMBus or autoloading from EEPROM.
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
1:0
Power State
RW
DESCRIPTION
Indicates the current power state of the Switch. Writing a value of D0 when
the previous state was D3 cause a hot reset without asserting DWNRST_L.
Page 39 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.33
BIT
FUNCTION
2
Reserved
RO
3
No_Soft_Reset
RO
7:4
8
Reserved
PME# Enable
RO
RWS
12:9
Data Select
RW
14:13
15
Data Scale
PME status
RO
ROS
DESCRIPTION
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
Reset to 0b.
When set, this bit indicates that device transitioning from D3hot to D0 does
not perform an internal reset. When clear, an internal reset is performed when
power state transits from D3hot to D0. This bit can be rewritten with
EEPROM programming. The default value may be changed by SMBus or
auto-loading from EEPROM.
Reset to 1b.
Reset to 0b.
When asserted, the Switch will generate the PME# message. Reset to 0b.
Select data registers.
Reset to 0h.
Reset to 00b.
Read as 0b as the PME# message is not implemented.
PPB SUPPORT EXTENSIONS – OFFSET 84h
BIT
21:16
22
23
7.2.34
TYPE
FUNCTION
Reserved
B2_B3 Support for
D3HOT
Bus Power / Clock
Control Enable
TYPE
RO
RO
RO
DESCRIPTION
Reset to 000000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
31:24
Data Register
RO
DESCRIPTION
Data Register. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset to 0b.
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
7:0
FUNCTION
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 05h to indicate that this is message signal interrupt capability
register.
Page 40 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.36
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the Vendor specific capability register (A4h).
RO
Reset to A4h.
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
TYPE
16
MSI Enable
RW
19:17
22:20
7.2.38
Multiple Message
Capable
Multiple Message
Enable
RO
RW
23
64-bit address
capable
RO
31:24
Reserved
RO
DESCRIPTION
0b: The function is prohibited from using MSI to request service
1b: The function is permitted to use MSI to request service and is prohibited
from using its INTx # pin
Reset to 0b.
Read as 000b.
Reset to 000b.
0b: The function is not capable of generating a 64-bit message address
1b: The function is capable of generating a 64-bit message address
Reset to 1b.
Reset to 00h.
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only)
BIT
1:0
FUNCTION
Reserved
TYPE
RO
31:2
Message Address
RW
DESCRIPTION
Reset to 00b.
If the message enable bit is set, the contents of this register specify the
DWORD aligned address for MSI memory write transaction.
Reset to 0.
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream
Port Only)
BIT
FUNCTION
31:0
Message Upper
Address
TYPE
RW
DESCRIPTION
This register is only effective if the device supports a 64-bit message address
is set.
Reset to 00000000h.
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only)
BIT
15:0
7.2.41
FUNCTION
Message Data
TYPE
RW
DESCRIPTION
Reset to 0000h.
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)
Page 41 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.42
BIT
FUNCTION
7:0
Enhanced
Capabilities ID
TYPE
DESCRIPTION
Read as 03h to indicate that these are VPD enhanced capability registers.
RO
Reset to 03h.
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the Vendor specific capability register (A4h).
RO
Reset to A4h.
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
17:16
FUNCTION
Reserved
TYPE
RO
23:18
VPD Address
RW
30:24
Reserved
RO
31
VPD operation
RW
DESCRIPTION
Reset to 00b.
Contains DWORD address that is used to generate read or write cycle to the
VPD table stored in EEPROM.
Reset to 000000b.
Reset to 0000000b.
0b: Performs VPD read command to VPD table at the location as specified
in VPD address. This bit is kept ‘0’ and then set to ‘1’ automatically
after EEPROM cycle is finished
1b: Performs VPD write command to VPD table at the location as specified
in VPD address. This bit is kept ‘1’ and then set to ‘0’ automatically
after EEPROM cycle is finished.
Reset to 0b.
7.2.44
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only)
BIT
FUNCTION
31:0
VPD Data
TYPE
DESCRIPTION
When read, it returns the last data read from VPD table at the location as
specified in VPD Address.
RW
When written, it places the current data into VPD table at the location as
specified in VPD Address.
7.2.45
7.2.46
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h
BIT
FUNCTION
7:0
Enhanced
Capabilities ID
TYPE
DESCRIPTION
Read as 09h to indicate that these are vendor specific capability registers.
RO
Reset to 09h.
NEXT ITEM POINTER REGISTER – OFFSET A4h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the SSID/SSVID capability register (B8h).
RO
Reset to B8h.
Page 42 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.47
LENGTH REGISTER – OFFSET A4h
BIT
FUNCTION
31:16
Length Information
TYPE
RO
DESCRIPTION
The length field provides the information for number of bytes in the
capability structure (including the ID and Next pointer bytes).
Reset to 000Ch.
7.2.48
XPIP CSR0 – OFFSET A8h (Test Purpose Only)
BIT
31:0
7.2.49
TYPE
RW
DESCRIPTION
Reset to 04001060h.
XPIP CSR1 – OFFSET ACh (Test Purpose Only)
BIT
31:0
7.2.50
FUNCTION
Reserved
FUNCTION
Reserved
TYPE
RW
DESCRIPTION
Reset to 04000800h.
REPLAY TIME-OUT COUNTER – OFFSET B0h
BIT
FUNCTION
11:0
User Replay Timer
12
13
14
15
Enable User Replay
Timer
Power Management
Capability Disable
MSI Capability
Disable
AER Capability
Disable
TYPE
RW
RW
RO
RO
RO
DESCRIPTION
A 12-bit register contains a user-defined value. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 000h.
When asserted, the user-defined replay time-out value is be employed. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
7.2.51
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h
BIT
FUNCTION
29:16
User ACK Latency
Timer
TYPE
RW
DESCRIPTION
A 14-bit register contains a user-defined value. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 0.
Page 43 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.52
BIT
FUNCTION
TYPE
30
Enable User ACK
Latency
RW
31
Reserved
RO
DESCRIPTION
When asserted, the user-defined ACK latency value is be employed. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
Reset to 0b.
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port)
BIT
FUNCTION
TYPE
0
Store-Forward
RW
DESCRIPTION
When set, a store-forward mode is used. Otherwise, the chip is working under
cut-through mode. The default value may be changed by SMBus or autoloading from EEPROM.
Reset to 0b.
Cut-through Threshold. When forwarding a packet from low-speed port to
high-speed mode, the chip provides the capability to adjust the forwarding
threshold. The default value may be changed by SMBus or auto-loading from
EEPROM.
2:1
3
4
Cut-through
Threshold
Port Arbitration
Mode
Credit Update Mode
RW
RW
RW
Ordering on
Different Egress Port
Mode
RW
6
Ordering on
Different Tag of
Completion Mode
RW
7
Reserved
RO
13:8
Power management
Control parameter
RW
5
14
RX Polarity
Inversion Disable
RO
00b: the threshold is set at the middle of forwarding packet
01b: the threshold is set ahead 1-cycle of middle point
10b: the threshold is set ahead 2-cycle of middle point.
11b: the threshold is set ahead 3-cycle of middle point.
Reset to 01b.
When set, the round-robin arbitration will stay in the arbitrated port even if
the credit is not enough but request is pending.
When clear, the round-robin arbitration will always go to the requesting port,
which the outgoing credit is enough for the packet queued in the port.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
When set, the frequency of releasing new credit to the link partner will be one
credit per update.
When clear, the frequency of releasing new credit to the link partner will be
two credits per update.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
When set, there has ordering rule on packets for different egress port. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
When set, there has ordering rule between completion packet with different
tag. The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
Reset to 0.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 000001b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
Page 44 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
15
Compliance pattern
Parity Control
Disable
RO
16
Low Driver Current
HwInt
17
High Driver Current
HwInt
21:18
25:22
27:26
29:28
31:30
7.2.53
HwInt
HwInt
DESCRIPTION
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
It indicates the status of the strapping pin LODRV. The default value may be
changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pin HIDRV. The default value may be
changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins DTX[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins DEQ[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
HwInt
It indicates the status of the strapping pins RXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins TXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
HwInt
It indicates the status of the strapping pins RXEQCTL[1:0]. The default value
may be changed by SMBus or auto-loading from EEPROM.
HwInt
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port)
BIT
7:0
FUNCTION
Reserved
13:8
Power management
Control parameter
TYPE
RO
RW
14
RX Polarity
Inversion Disable
15
Compliance pattern
Parity Control
Disable
RO
16
Low Driver Current
HwInt
17
High Driver Current
HwInt
21:18
25:22
27:26
29:28
31:30
7.2.54
Driver Transmit
Current
De-emphasis
Transmit
Equalization
Receive Termination
Adjustment
Transmit
Termination
Adjustment
Receiver
Equalization Level
Control
TYPE
Driver Transmit
Current
De-emphasis
Transmit
Equalization
Receive Termination
Adjustment
Transmit
Termination
Adjustment
Receiver
Equalization Level
Control
RO
HwInt
HwInt
DESCRIPTION
Reset to 0.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 000001b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 0b.
It indicates the status of the strapping pin LODRV. The default value may be
changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pin HIDRV. The default value may be
changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins DTX[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins DEQ[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
HwInt
It indicates the status of the strapping pins RXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
It indicates the status of the strapping pins TXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
HwInt
It indicates the status of the strapping pins RXEQCTL[1:0]. The default value
may be changed by SMBus or auto-loading from EEPROM.
HwInt
SSID/SSVID CAPABILITY ID REGISTER – OFFSET B8h
BIT
FUNCTION
TYPE
DESCRIPTION
Page 45 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
7:0
7.2.55
FUNCTION
SSID/SSVID
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0Dh to indicate that these are SSID/SSVID capability registers.
NEXT ITEM POINTER REGISTER – OFFSET B8h
BIT
FUNCTION
15:8
Next Item Pointer
TYPE
DESCRIPTION
Pointer points to the PCI Express capability register (E0h).
RO
Reset to E0h.
7.2.56
SUBSYSTEM VENDOR ID REGISTER – OFFSET BCh
BIT
15:0
FUNCTION
SSVID
TYPE
RO
DESCRIPTION
It indicates the sub-system vendor id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.57
SUBSYSTEM ID REGISTER – OFFSET BCh
BIT
31:16
FUNCTION
SSID
TYPE
RO
DESCRIPTION
It indicates the sub-system device id. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 0000h.
7.2.58
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)
BIT
0
FUNCTION
GPIO [0] Input
1
GPIO [0] Output
Enable
TYPE
RO
RW
2
GPIO [0] Output
Register
RW
3
4
Reserved
GPIO [1] Input
RO
RO
5
GPIO [1] Output
Enable
RW
6
GPIO [1] Output
Register
RW
7
8
Reserved
GPIO [2] Input
RO
RO
9
GPIO [2] Output
Enable
RW
DESCRIPTION
State of GPIO [0] pin
0b: GPIO [0] is an input pin
1b: GPIO [0] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [0] pin if GPIO [0] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [1] pin.
0b: GPIO [1] is an input pin
1b: GPIO [1] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [1] pin if GPIO [1] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [2] pin
0b: GPIO [2] is an input pin
1b: GPIO [2] is an output pin
Reset to 0b.
Page 46 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.59
BIT
FUNCTION
TYPE
10
GPIO [2] Output
Register
RW
11
12
Reserved
GPIO [3] Input
RO
RO
13
GPIO [3] Output
Enable
RW
14
GPIO [3] Output
Register
RW
15
16
Reserved
GPIO [4] Input
RO
RO
17
GPIO [4] Output
Enable
RW
18
GPIO [4] Output
Register
RW
19
20
Reserved
GPIO [5] Input
RO
RO
21
GPIO [5] Output
Enable
RW
22
GPIO [5] Output
Register
RW
23
24
Reserved
GPIO [6] Input
RO
RO
25
GPIO [6] Output
Enable
RW
26
GPIO [6] Output
Register
RW
27
28
Reserved
GPIO [7] Input
RO
RO
29
GPIO [7] Output
Enable
RW
30
GPIO [7] Output
Register
RW
31
Reserved
RO
DESCRIPTION
Value of this bit will be output to GPIO [2] pin if GPIO [2] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [3] pin.
0b: GPIO [3] is an input pin
1b: GPIO [3] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [4] pin.
0b: GPIO [4] is an input pin
1b: GPIO [4] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [5] pin.
0b: GPIO [5] is an input pin
1b: GPIO [5] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [5] pin if GPIO [5] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [6] pin.
0b: GPIO [6] is an input pin
1b: GPIO [6] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [6] pin if GPIO [6] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
State of GPIO [7] pin.
0b: GPIO [7] is an input pin
1b: GPIO [7] is an output pin
Reset to 0b.
Value of this bit will be output to GPIO [7] pin if GPIO [7] is configured as
an output pin.
Reset to 0b.
Reset to 0b.
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)
BIT
FUNCTION
0
EEPROM Start
TYPE
DESCRIPTION
Starts the EEPROM read or write cycle.
RW
Reset to 0b.
Page 47 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
1
EEPROM Command
2
EEPROM Error
Status
RO
EEPROM Autoload
Success
RO
Reset to 0b.
0b: EEPROM autoload was unsuccessful or is disabled
1b: EEPROM autolad occurred successfully after RESET. Configuration
registers were loaded with values in the EEPROM
RO
It will be cleared when read at this bit.
0b: EEPROM autoload was unsuccessful or is disabled
1b: EEPROM autoload occurred successfully after PREST. Configuration
registers were loaded with values stored in the EEPROM
3
4
5
EEPROM Autoload
Status
EEPROM Autoload
Disable
TYPE
RW
DESCRIPTION
Sends the command to the EEPROM.
0b: EEPROM read
1b: EEPROM write
Reset to 0b.
1b: EEPROM acknowledge was not received during the EEPROM cycle.
RW
Reset to 0b.
0b: EEPROM autoload enabled
1b: EEPROM autoload disabled
Reset to 1b.
Determines the frequency of the EEPROM clock, which is derived from the
primary clock.
7:6
EEPROM Clock
Rate
RW
00b: Reserved
01b: PEXCLK / 1024 (PEXCLK is 125MHz)
10b: Reserved
11b: Test Mode
Reset to 01b.
7.2.60
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only)
BIT
8
FUNCTION
Reserved
15:9
EEPROM Address
TYPE
RO
DESCRIPTION
Reset to 0b.
Contains the EEPROM address.
RW
Reset to 0.
7.2.61
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only)
BIT
FUNCTION
31:16
EEPROM Data
TYPE
RW
DESCRIPTION
Contains the data to be written to the EEPROM. After completion of a read
cycle, this register will contain the data from the EEPROM.
Reset to 0000h.
7.2.62
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h
BIT
7:0
FUNCTION
Enhanced
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 10h to indicate that these are PCI express enhanced capability
registers.
Page 48 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.63
NEXT ITEM POINTER REGISTER – OFFSET E0h
BIT
15:8
7.2.64
TYPE
RO
DESCRIPTION
Read as 00h. No other ECP registers.
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
BIT
FUNCTION
19:16
Capability Version
RO
23:20
Device/Port Type
RO
24
Slot Implemented
HwInt
29:25
31:30
7.2.65
FUNCTION
Next Item Pointer
Interrupt Message
Number
Reserved
TYPE
RO
RO
DESCRIPTION
Read as 0001b to indicate the device is compliant to Revision 1.0a of PCI
Express Base Specifications.
Indicates the type of PCI Express logical device.
Reset to 0101b (Upstream port).
Reset to 0110b (Downstream port).
When set, indicates that the PCIe Link associated with this Port is connected
to a slot. This field is valid for downstream port of the switch. The default
value may be changed by the status of strapped pin, SMBus, or auto-loading
from EEPROM.
Read as 0b. No MSI messages are generated in the transparent mode.
Reset to 00b.
DEVICE CAPABILITIES REGISTER – OFFSET E4h
BIT
FUNCTION
2:0
Max_Payload_Size
Supported
4:3
5
8:6
Phantom Functions
Supported
Extended Tag Field
Supported
Endpoint L0s
Acceptable Latency
TYPE
RO
RO
RO
DESCRIPTION
Indicates the maximum payload size that the device can support for TLPs.
Each port of the Switch supports 256 bytes max payload size. The default
value may be changed by SMBus or auto-loading from EEPROM.
Reset to 001b.
Indicates the support for use of unclaimed function numbers as Phantom
functions. Read as 00b, since the Switch does not act as a requester.
Reset to 00b.
Indicates the maximum supported size of Tag field as a Requester. Read as 0,
since the Switch does not act as a requester.
RO
Reset to 0b.
Acceptable total latency that an Endpoint can withstand due to the transition
from L0s state to the L0 state. For Switch, the ASPM software would not
check this value.
Reset to 000b.
Acceptable total latency that an Endpoint can withstand due to the transition
from L1 state to the L0 state. For Switch, the ASPM software would not
check this value.
11:9
Endpoint L1
Acceptable Latency
RO
14:12
Reserved
RO
15
Role_Based Error
Reporting
RO
Reset to 000b.
Reset to 000b.
When set, indicates that the device implements the functionality originally
defined in the Error Reporting ECN. The default value may be changed by
SMBus or auto-loading from EEPROM.
17:16
Reserved
RO
Reset to 1b.
Reset to 00b.
Page 49 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
25:18
Captured Slot Power
Limit Value
TYPE
RO
DESCRIPTION
It applies to Upstream Port only. In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or hardwired to 00h.
Reset to 00h.
It applies to Upstream Port only. Specifies the scale used for the Slot Power
Limit Value.
7.2.66
27:26
Captured Slot Power
Limit Scale
RO
31:28
Reserved
RO
This value is set by the Set_Slot_Power_Limit message or hardwired to 00b.
Reset to 00b.
Reset to 0h.
DEVICE CONTROL REGISTER – OFFSET E8h
BIT
FUNCTION
0
Correctable Error
Reporting Enable
1
2
3
4
Non-Fatal Error
Reporting Enable
Fatal Error Reporting
Enable
Unsupported Request
Reporting Enable
Enable Relaxed
Ordering
TYPE
RW
RW
RW
RW
RO
7:5
Max_Payload_Size
8
Extended Tag Field
Enable
RW
9
Phantom Function
Enable
RW
Auxiliary (AUX)
Power PM Enable
RWS
10
11
Enable No Snoop
RW
DESCRIPTION
0b: Disable Correctable Error Reporting
1b: Enable Correctable Error Reporting
Reset to 0b.
0b: Disable Non-Fatal Error Reporting
1b: Enable Non-Fatal Error Reporting
Reset to 0b.
0b: Disable Fatal Error Reporting
1b: Enable Fatal Error Reporting
Reset to 0b.
0b: Disable Unsupported Request Reporting
1b: Enable Unsupported Request Reporting
Reset to 0b.
When set, it permits the device to set the Relaxed Ordering bit in the attribute
field of transaction. Since the Switch can not either act as a requester or alter
the content of packet it forwards, this bit always returns ‘0’ when read.
Reset to 0b.
This field sets maximum TLP payload size for the device. Permissible values
that can be programmed are indicated by the Max_Payload_Size Supported in
the Device Capabilities register. Any value exceeding the Max_Payload_Size
Supported written to this register results into clamping to the
Max_Payload_Size Supported value.
Reset to 000b.
Does not apply to PCI Express Switch. Returns ‘0’ when read.
Reset to 0.
Does not apply to PCI Express Switch. Returns ‘0’ when read.
RO
Reset to 0b.
When set, indicates that a device is enabled to draw AUX power independent
of PME AUX power.
Reset to 0b.
When set, it permits to set the No Snoop bit in the attribute field of
transaction. Since the Switch can not either act as a requester or alter the
content of packet it forwards, this bit always returns ‘0’ when read.
Reset to 0b.
Page 50 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.67
BIT
FUNCTION
TYPE
14:12
Max_Read_
Request_Size
RO
DESCRIPTION
This field sets the maximum Read Request size for the device as a Requester.
Since the Switch does not generate read request by itself, these bits are
hardwired to 000b.
15
Reserved
RO
Reset to 000b.
Reset to 0b.
DEVICE STATUS REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
16
Correctable Error
Detected
RW1C
DESCRIPTION
Asserted when correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when non-fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
RW1C
Reset to 0b.
Asserted when unsupported request is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register.
17
18
7.2.68
Non-Fatal Error
Detected
Fatal Error Detected
19
Unsupported Request
Detected
20
AUX Power
Detected
RO
21
Transactions Pending
RO
31:22
Reserved
RO
Reset to 0b.
Asserted when the AUX power is detected by the Switch
Reset to 1b.
Each port of Switch does not issue Non-posted Requests on its own behalf, so
this bit is hardwired to 0b.
Reset to 0b.
Reset to 0.
LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
3:0
FUNCTION
Maximum Link
Speed
TYPE
RO
DESCRIPTION
Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s.
Indicates the maximum width of the given PCIe Link. The width of each port
is determined by strapped pin or EEPROM pre-loaded value.
9:4
Maximum Link
Width
RO
11:10
Active State Power
Management
(ASPM) Support
RO
Reset to 000001b (x1) for Port 0.
Reset to 000001b (x1) for Port 1.
Reset to 000001b (x1) for Port 2.
Reset to 000001b (x1) for Port 3.
Indicates the level of ASPM supported on the given PCIe Link. Each port of
Switch supports L0s and L1 entry. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 01b.
Page 51 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.69
BIT
FUNCTION
14:12
L0s Exit Latency
TYPE
RO
17:15
L1 Exit
Latency
RO
19:18
Reserved
RO
20
Data Link Layer
Active Reporting
Capable
RO
DESCRIPTION
Indicates the L0s exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be changed
by SMBus or auto-loading from EEPROM.
Reset to 011b.
Indicates the L1 exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L1 to L0 is in
the range of 16us to less than 32us. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 00b.
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug capable Downstream
Port, this bit must be set to 1b.
For Upstream Port, this bit must be hardwired to 0b.
23:21
Reserved
R0
31:24
Port Number
RO
Reset to 0b for upstream port.
Reset to 1b for downstream ports.
Reset to 000b
Indicates the PCIe Port Number for the given PCIe Link. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h for Port 0.
Reset to 01h for Port 1.
Reset to 02h for Port 2.
Reset to 03h for Port 3.
LINK CONTROL REGISTER – OFFSET F0h
BIT
FUNCTION
1:0
Active State Power
Management
(ASPM) Control
RW
2
Reserved
RO
3
Read Completion
Boundary (RCB)
RO
Link Disable
RW
4
5
6
Retrain Link
Common Clock
Configuration
TYPE
DESCRIPTION
00b: ASPM is Disabled
01b: L0s Entry Enabled
10b: L1 Entry Enabled
11b: L0s and L1 Entry Enabled
Note that the receiver must be capable of entering L0s even when the field is
disabled.
RW
RW
Reset to 00b.
Reset to 0b.
Does not apply to PCI Express Switch. Returns ‘0’ when read.
Reset to 0b.
At upstream port, it is not allowed to disable the link, so this bit is hardwired
to ‘0’. For downstream ports, it disables the link when this bit is set.
Reset to 0b.
At upstream port, it is not allowed to retrain the link, so this bit is hardwired
to 0b. For downstream ports, it initiates Link Retraining when this bit is set.
This bit always returns 0b when read.
0b: The components at both ends of a link are operating with asynchronous
reference clock
1b: The components at both ends of a link are operating with a distributed
common reference clock
Reset to 0b.
Page 52 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.70
BIT
FUNCTION
7
Extended Synch
RW
15:8
Reserved
RO
DESCRIPTION
When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0
state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state.
Reset to 0b.
Reset to 00h.
LINK STATUS REGISTER – OFFSET F0h
BIT
FUNCTION
19:16
Link Speed
RO
25:20
Negotiated Link
Width
RO
Training Error
RO
26
27
28
7.2.71
TYPE
Link Training
Slot Clock
Configuration
TYPE
RO
DESCRIPTION
Read as 0001b to indicate the negotiated speed of the Express link is 2.5
Gb/s.
Indicates the negotiated width of the given PCIe link.
Reset to 000001b (x1).
When set, indicates a Link training error occurred.
This bit is cleared by hardware upon successful training of the link to the L0
link state.
Reset to 0b.
When set, indicates the link training is in progress. Hardware clears this bit
once link training is complete.
Reset to 0b.
0b: the Switch uses an independent clock irrespective of the presence of a
reference on the connector
1b: the Switch uses the same reference clock that the platform provides on the
connector
HwInt
The default value may be changed by the status of strapped pin, SMBus, or
auto-loading from EEPROM.
29
Data Link Layer
Link Active
RO
31:30
Reserved
RO
Reset to 0b.
Indicates the status of the Data Link Control and Management State Machine.
It returns a 1b to indicate the DL_Active state, 0b otherwise.
Reset to 0b.
Reset to 00b.
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h
BIT
FUNCTION
0
Attention Button
Present
TYPE
RO
DESCRIPTION
When set, it indicates that an Attention Button is implemented on the chassis
for this slot. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset to 0b.
When set, it indicates that a Power Controller is implemented for this slot.
The default value may be changed by SMBus or auto-loading from
EEPROM.
1
Power Controller
Present
RO
2
Reserved
RO
3
Attention Indicator
Present
RO
Reset to 0b.
Reset to 0b.
When set, it indicates that an Attention Indicator is implemented on the
chassis for this slot. The default value may be changed by SMBus or autoloading from EEPROM.
Reset to 0b.
Page 53 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
4
Power Indicator
Present
5
Hot-Plug Surprise
TYPE
RO
DESCRIPTION
When set, it indicates that a Power Indicator is implemented on the chassis
for this slot. The default value may be changed by SMBus or auto-loading
from EEPROM.
RO
Reset to 0b.
When set, it indicates that a device present in this slot might be removed from
the system without any prior notification. The default value may be changed
by SMBus or auto-loading from EEPROM.
6
Hot-Plug Capable
HwInt
14:7
Slot Power Limit
Value
RW
16:15
Slot Power Limit
Scale
RW
18:17
Reserved
RO
31:19
Physical Slot
Number
RO
Reset to 0b.
When set, it indicates that this slot is capable of supporting Hot-Plug
operation. The default value may be changed by the status of strapped pin or
auto-loading from EEPROM.
It applies to Downstream Port only. In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot. Writes to this
register also cause the Port to send the Set_Slot_Power_Limit message. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
It applies to Downstream Port only. Specifies the scale used for the Slot
Power Limit Value. Writes to this register also cause the Port to send the
Set_Slot_Power_Limit message. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 00b.
Reset to 00b.
It indicates the physical slot number attached to this Port. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 0.
7.2.72
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h
BIT
FUNCTION
0
Attention Button
Pressed Enable
TYPE
RW
1
Power Fault Detected
Enable
RW
2
Reserved
RO
3
Presence Detect
Changed Enable
RW
4
5
Command
Completed Interrupt
Enable
RW
Hot-Plug Interrupt
Enable
RW
DESCRIPTION
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
an attention button pressed event.
Reset to 0b.
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
a power fault event.
Reset to 0b.
Reset to 0b.
When set, it enables the generation of Hot-Plug interrupt or wakeup event on
a presence detect changed event.
Reset to 0b.
When set, it enables the generation of Hot-Plug interrupt when the Hot-Plug
Controller completes a command.
Reset to 0b.
When set, it enables generation of Hot-Plug interrupt on enabled Hot-Plug
events.
Reset to 0b.
Page 54 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
7:6
FUNCTION
Attention Indicator
Control
TYPE
RW
DESCRIPTION
Controls the display of Attention Indicator.
00b: Reserved
01b: On
10b: Blink
11b: Off
Writes to this register also cause the Port to send the
ATTENTION_INDICATOR_* Messages.
Reset to 11b.
Controls the display of Power Indicator.
9:8
Power Indicator
Control
RW
00b: Reserved
01b: On
10b: Blink
11b: Off
Writes to this register also cause the Port to send the
POWER_INDICATOR_* Messages.
7.2.73
Reset to 11b.
0b: reset the power state of the slot (Power On)
1b: set the power state of the slot (Power Off)
10
Power Controller
Control
RW
11
Reserved
RO
12
Data Link Layer
State Changed
Enable
RW
Reset to 0b.
Reset to 0b.
If the Data Link Layer Link Active capability is implemented, when set to 1b,
this field enables software notification when Data Link Layer Link Active
field is changed.
15:13
Reserved
RO
Reset to 0b.
Reset to 000b
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h
BIT
FUNCTION
TYPE
16
Attention Button
Pressed
RW1C
Power Fault Detected
RW1C
17
18
19
20
21
MRL Sensor
Changed
Reset to 0b.
When set, it indicates a Power Fault is detected.
Reset to 0b.
When set, it indicates a MRL Sensor Changed is detected.
RO
Reset to 0b.
When set, it indicates a Presence Detect Changed is detected.
Presence Detect
Changed
RW1C
Command
Completed
RW1C
MRL Sensor State
DESCRIPTION
When set, it indicates the Attention Button is pressed.
Reset to 0b.
When set, it indicates the Hot-Plug Controller completes an issued command.
Reset to 0b.
Reflects the status of MRL Sensor.
RO
0b: MRL Closed
1b: MRL Opened
Reset to 0b.
Page 55 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
TYPE
DESCRIPTION
Indicates the presence of a card in the slot.
0b: Slot Empty
1b: Card Present in slot
22
Presence Detect State
RO
23
Reserved
Data Link Layer
State Changed
Reserved
RO
24
31:25
7.2.74
Reset to 1b.
Reset to 0.
This bit is set when the value reported in the Data Link Layer Link Active
field of the Link Status register is changed.
Reset to 0
RW1C
RO
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID
REGISTER – OFFSET 100h
BIT
15:0
7.2.75
This register is implemented on all Downstream Ports that implement slots.
For Downstream Ports not connected to slots (where the Slot Implemented bit
of the PCI Express Capabilities register is 0b), this bit returns 1b.
FUNCTION
Extended
Capabilities ID
TYPE
DESCRIPTION
Read as 0001h to indicate that these are PCI express extended capability
registers for advance error reporting.
RO
CAPABILITY VERSION – OFFSET 100h
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCI-SIG defined PCI Express capability structure
version number.
RO
Reset to 1h.
7.2.76
7.2.77
NEXT ITEM POINTER REGISTER – OFFSET 100h
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
DESCRIPTION
Pointer points to the PCI Express Extended VC capability register (140h).
RO
Reset to 140h.
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h
BIT
FUNCTION
0
Training Error Status
3:1
Reserved
4
Data Link Protocol
Error Status
11:5
Reserved
12
Poisoned TLP Status
13
Flow Control
Protocol Error Status
TYPE
DESCRIPTION
When set, indicates that the Training Error event has occurred.
RW1CS
Reset to 0b.
Reset to 000b.
When set, indicates that the Data Link Protocol Error event has occurred.
RO
RW1CS
Reset to 0b.
Reset to 0.
When set, indicates that a Poisoned TLP has been received or generated.
RO
RW1CS
Reset to 0b.
When set, indicates that the Flow Control Protocol Error event has occurred.
RW1CS
Reset to 0b.
Page 56 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.78
BIT
FUNCTION
14
Completion Timeout
Status
TYPE
DESCRIPTION
When set, indicates that the Completion Timeout event has occurred.
RW1CS
15
Completer Abort
Status
RW1CS
16
Unexpected
Completion Status
RW1CS
17
Receiver Overflow
Status
RW1CS
18
Malformed TLP
Status
RW1CS
19
ECRC Error Status
RW1CS
20
Unsupported Request
Error Status
31:21
Reserved
Reset to 0b.
When set, indicates that the Completer Abort event has occurred.
Reset to 0b.
When set, indicates that the Unexpected Completion event has occurred.
Reset to 0b.
When set, indicates that the Receiver Overflow event has occurred.
Reset to 0b.
When set, indicates that a Malformed TLP has been received.
Reset to 0b.
When set, indicates that an ECRC Error has been detected.
Reset to 0b.
When set, indicates that an Unsupported Request event has occurred.
RW1CS
RO
Reset to 0b.
Reset to 0.
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h
BIT
FUNCTION
TYPE
0
Training Error Mask
RWS
3:1
Reserved
4
Data Link Protocol
Error Mask
11:5
Reserved
12
Poisoned TLP Mask
13
14
15
16
17
Flow Control
Protocol Error Mask
Completion Timeout
Mask
Completer Abort
Mask
Unexpected
Completion Mask
Receiver Overflow
Mask
RO
RWS
RO
RWS
RWS
RWS
RWS
RWS
RWS
DESCRIPTION
When set, the Training Error event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 000b.
When set, the Data Link Protocol Error event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 0.
When set, an event of Poisoned TLP has been received or generated is not
logged in the Header Log register and not issued as an Error Message to RC
either.
Reset to 0b.
When set, the Flow Control Protocol Error event is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Completion Timeout event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Completer Abort event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Unexpected Completion event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Receiver Overflow event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Page 57 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
TYPE
18
Malformed TLP
Mask
RWS
19
7.2.79
ECRC Error Mask
20
Unsupported Request
Error Mask
31:21
Reserved
RWS
RWS
RO
DESCRIPTION
When set, an event of Malformed TLP has been received is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, an event of ECRC Error has been detected is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the Unsupported Request event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 0.
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch
BIT
FUNCTION
TYPE
0
Training Error
Severity
RWS
3:1
Reserved
4
Data Link Protocol
Error Severity
11:5
Reserved
12
Poisoned TLP
Severity
13
14
15
16
17
18
19
RO
RWS
RO
RWS
Flow Control
Protocol Error
Severity
RWS
Completion Timeout
Error Severity
RWS
Completer Abort
Severity
Unexpected
Completion Severity
Receiver Overflow
Severity
Malformed TLP
Severity
ECRC Error Severity
RWS
RWS
RWS
RWS
RWS
DESCRIPTION
0b: Non-Fatal
1b: Fatal
Reset to 1b.
Reset to 000b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
Reset to 0.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 0b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 1b.
0b: Non-Fatal
1b: Fatal
Reset to 0.
Page 58 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.80
BIT
FUNCTION
TYPE
20
Unsupported Request
Error Severity
RWS
31:21
Reserved
DESCRIPTION
0b: Non-Fatal
1b: Fatal
Reset to 0b.
Reset to 0.
RO
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h
BIT
FUNCTION
0
Receiver Error Status
5:1
Reserved
6
Bad TLP Status
TYPE
DESCRIPTION
When set, the Receiver Error event is detected.
RW1CS
Reset to 0b.
Reset to 00000b.
When set, the event of Bad TLP has been received is detected.
RO
RW1CS
Reset to 0b.
When set, the event of Bad DLLP has been received is detected.
7.2.81
7
Bad DLLP Status
RW1CS
8
REPLAY_NUM
Rollover status
11:9
Reserved
12
Replay Timer
Timeout status
RW1CS
13
Advisory Non-Fatal
Error status
RW1CS
31:14
Reserved
Reset to 0b.
When set, the REPLAY_NUM Rollover event is detected.
RW1CS
Reset to 0b.
Reset to 000b.
When set, the Replay Timer Timeout event is detected.
RO
Reset to 0b.
When set, the Advisory Non-Fatal Error event is detected.
RO
Reset to 0b.
Reset to 0b.
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h
BIT
FUNCTION
TYPE
0
Receiver Error Mask
RWS
5:1
Reserved
6
Bad TLP Mask
7
Bad DLLP Mask
8
REPLAY_NUM
Rollover Mask
11:9
Reserved
12
Replay Timer
Timeout Mask
RO
RWS
RWS
RWS
RO
RWS
DESCRIPTION
When set, the Receiver Error event is not logged in the Header Log register
and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 00000b.
When set, the event of Bad TLP has been received is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the event of Bad DLLP has been received is not logged in the
Header Log register and not issued as an Error Message to RC either.
Reset to 0b.
When set, the REPLAY_NUM Rollover event is not logged in the Header
Log register and not issued as an Error Message to RC either.
Reset to 0b.
Reset to 000b.
When set, the Replay Timer Timeout event is not logged in the Header Log
register and not issued as an Error Message to RC either.
Reset to 0b.
Page 59 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.82
7.2.83
BIT
FUNCTION
TYPE
13
Advisory Non-Fatal
Error Mask
RWS
31:14
Reserved
BIT
FUNCTION
4:0
First Error Pointer
5
ECRC Generation
Capable
RO
6
ECRC Generation
Enable
RWS
7
ECRC Check
Capable
8
ECRC Check Enable
31:9
Reserved
TYPE
ROS
DESCRIPTION
It indicates the bit position of the first error reported in the Uncorrectable
Error Status register.
Reset to 00000b.
When set, it indicates the Switch has the capability to generate ECRC.
Reset to 1b.
When set, it enables the generation of ECRC when needed.
Reset to 0b.
When set, it indicates the Switch has the capability to check ECRC.
RO
Reset to 1b.
When set, the function of checking ECRC is enabled.
RWS
RO
Reset to 0b.
Reset to 0.
HEADER LOG REGISTER – OFFSET From 11Ch to 128h
FUNCTION
1st DWORD
2nd DWORD
3rd DWORD
4th DWORD
TYPE
ROS
ROS
ROS
ROS
DESCRIPTION
Hold the 1st DWORD of TLP Header. The Head byte is in big endian.
Hold the 2nd DWORD of TLP Header. The Head byte is in big endian.
Hold the 3rd DWORD of TLP Header. The Head byte is in big endian.
Hold the 4th DWORD of TLP Header. The Head byte is in big endian.
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET
140h
BIT
15:0
7.2.85
Reset to 1b.
Reset to 0.
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET
118h
BIT
31:0
63:32
95:64
127:96
7.2.84
RO
DESCRIPTION
When set, the Advisory Non-Fatal Error event is not logged in the Header
Long register and not issued as an Error Message to RC either.
FUNCTION
Extended
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0002h to indicate that these are PCI express extended capability
registers for virtual channel.
CAPABILITY VERSION – OFFSET 140h
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCIe Base Specification REV. 1.0a.
RO
Reset to 1h.
Page 60 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.86
NEXT ITEM POINTER REGISTER – OFFSET 140h
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
RO
DESCRIPTION
Pointer points to the PCI Express Power Budgeting Capability register
(20Ch).
Reset to 20Ch.
7.2.87
7.2.88
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h
BIT
FUNCTION
TYPE
2:0
Extended VC Count
HwInt
3
Reserved
RO
6:4
Low Priority
Extended VC Count
RO
7
Reserved
RO
9:8
Reference Clock
RO
11:10
Port Arbitration
Table Entry Size
RO
31:12
Reserved
RO
DESCRIPTION
It indicates the number of extended Virtual Channels in addition to the default
VC supported by the Switch. The default value may be changed by the status
of strapped pin or auto-loading from EEPROM.
Reset to 001b.
Reset to 0b.
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 0b.
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
Reset to 0.
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h
BIT
FUNCTION
TYPE
7:0
VC Arbitration
Capability
RO
23:8
Reserved
RO
31:24
VC Arbitration Table
Offset
RO
DESCRIPTION
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Switch supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000011b.
Reset to 0.
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 03h.
7.2.89
PORT VC CONTROL REGISTER – OFFSET 14Ch
BIT
FUNCTION
0
Load VC Arbitration
Table
TYPE
RW
DESCRIPTION
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
Page 61 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.90
7.2.91
BIT
FUNCTION
TYPE
3:1
VC Arbitration
Select
RW
15:4
Reserved
RO
DESCRIPTION
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Switch are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
Reset to 0.
PORT VC STATUS REGISTER – OFFSET 14Ch
BIT
FUNCTION
TYPE
16
VC Arbitration Table
Status
RO
DESCRIPTION
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
31:17
Reserved
RO
Reset to 0b.
Reset to 0.
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h
BIT
FUNCTION
TYPE
7:0
Port Arbitration
Capability
RO
13:8
Reserved
RO
14
Advanced Packet
Switching
RO
Reset to 00001001b.
Reset to 000000b.
When set, it indicates the VC resource only supports transaction optimized
for Advanced Packet Switching (AS).
Reset to 0b.
This bit is not applied to PCIe Switch.
Reject Snoop
Transactions
RO
22:16
Maximum Time
Slots
RO
23
Reserved
RO
31:24
Port Arbitration
Table Offset
RO
15
DESCRIPTION
It indicates the types of Port Arbitration supported by the VC resource. The
Switch supports Hardware fixed arbitration scheme, e.g., Round Robin,
Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports)
and Time-based WRR with 128 phases (3~4 enabled ports). Note that the
Time-based WRR is only valid in VC1.
Reset to 0b.
It indicates the maximum numbers of time slots (minus one) are allocated for
Isochronous traffic. The default value may be changed by SMBus or autoloading from EEPROM.
Reset to 7Fh.
Reset to 0b.
It indicates the location of the Port Arbitration Table (n) as an offset from the
base address of the Virtual Channel Capability register in the unit of DQWD
(16 bytes).
Reset to 04h for Port Arbitration Table (0).
7.2.92
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h
BIT
FUNCTION
TYPE
7:0
TC/VC Map
RW
DESCRIPTION
This field indicates the TCs that are mapped to the VC resource. Bit locations
within this field correspond to TC values. When the bits in this field are set, it
means that the corresponding TCs are mapped to the VC resource. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to FFh.
Page 62 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
15:8
FUNCTION
Reserved
16
Load Port Arbitration
Table
TYPE
RO
RW
19:17
Port Arbitration
Select
RW
23:20
Reserved
RO
26:24
VC ID
RW
30:27
Reserved
RO
31
VC Enable
RW
DESCRIPTION
Reset to 00h.
When set, the programmed Port Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
This field is used to configure the Port Arbitration by selecting one of the
supported Port Arbitration schemes. The permissible values for the schemes
supported by Switch are 000b and 011b at VC0, other value than these
written into this register will be treated as default.
Reset to 000b.
Reset to 0h.
This field assigns a VC ID to the VC resource.
Reset to 000b.
Reset to 0h.
0b: it disables this Virtual Channel
1b: it enables this Virtual Channel
Reset to 1b.
7.2.93
7.2.94
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h
BIT
15:0
FUNCTION
Reserved
16
Port Arbitration
Table Status
TYPE
RO
RO
17
VC Negotiation
Pending
RO
31:18
Reserved
RO
DESCRIPTION
Reset to 0000h.
When set, it indicates that any entry of the Port Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set.
Reset to 0b.
When set, it indicates that the VC resource is still in the process of
negotiation. This bit is cleared after the VC negotiation is complete.
Reset to 0b.
Reset to 0.
VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch
BIT
FUNCTION
TYPE
7:0
Port Arbitration
Capability
RO
13:8
Reserved
RO
14
Advanced Packet
Switching
RO
DESCRIPTION
It indicates the types of Port Arbitration supported by the VC resource. The
Switch supports Hardware fixed arbitration scheme, e.g., Round Robin,
Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports)
and Time-based WRR with 128 phases (3~4 enabled ports). Note that the
Time-based WRR is only valid in VC1.
Reset to 00011001b.
Reset to 000000b.
When set, it indicates the VC resource only supports transaction optimized
for Advanced Packet Switching (AS).
Reset to 0b.
This bit is not applied to PCIe Switch.
Reject Snoop
Transactions
RO
22:16
Maximum Time
Slots
RO
Reset to 0b.
It indicates the maximum numbers of time slots (minus one) are allocated for
Isochronous traffic. The default value may be changed by SMBus or autoloading from EEPROM.
23
Reserved
RO
Reset to 7Fh.
Reset to 0b.
15
Page 63 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
BIT
FUNCTION
31:24
Port Arbitration
Table Offset
TYPE
DESCRIPTION
It indicates the location of the Port Arbitration Table (n) as an offset from the
base address of the Virtual Channel Capability register in the unit of DQWD
(16 bytes).
RO
Reset to 08h for Port Arbitration Table (1)
7.2.95
VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h
BIT
FUNCTION
TYPE
7:0
TC/VC Map
RW
(Exception
for bit0)
15:8
Reserved
RO
16
Load Port
Arbitration Table
RW
19:17
Port Arbitration
Select
RW
23:20
Reserved
RO
26:24
VC ID
RW
30:27
Reserved
RO
31
VC Enable
RW
DESCRIPTION
This field indicates the TCs that are mapped to the VC resource. Bit
locations within this field correspond to TC values. When the bits in this
field are set, it means that the corresponding TCs are mapped to the VC
resource. Bit 0 of this filed is read-only and must be set to “0” for the VC1.
The default value may be changed by SMBus or auto-loading from
EEPROM.
Reset to 00h.
Reset to 00h.
When set, the programmed Port Arbitration Table is applied to the
hardware. This bit always returns 0b when read.
Reset to 0b.
This field is used to configure the Port Arbitration by selecting one of the
supported Port Arbitration schemes. The permissible values for the
schemes supported by Switch are 000b, 011b and 100b at VC1, other value
than these written into this register will be treated as default.
Reset to 000b.
Reset to 0h.
This field assigns a VC ID to the VC resource.
Reset to 001b.
Reset to 0h.
0b: it disables this Virtual Channel
1b: it enables this Virtual Channel
Reset to 0b.
7.2.96
7.2.97
VC RESOURCE STATUS REGISTER (1) – OFFSET 164h
BIT
15:0
FUNCTION
Reserved
16
Port Arbitration
Table Status
TYPE
RO
RO
17
VC Negotiation
Pending
RO
31:18
Reserved
RO
DESCRIPTION
Reset to 0000h.
When set, it indicates that any entry of the Port Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set.
Reset to 0b.
When set, it indicates that the VC resource is still in the process of
negotiation. This bit is cleared after the VC negotiation is complete.
Reset to 0b.
Reset to 0.
VC ARBITRATION TABLE REGISTER – OFFSET 170h
Page 64 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
The VC arbitration table is a read-write register array that contains a table for VC arbitration. Each
table entry allocates four bits, of which three bits are used to represent VC ID and one bit is reserved.
A total of 32 entries are used to construct the VC arbitration table. The layout for this register array is
shown below.
Table 7-1 Register Array Layout for VC Arbitration
31 - 28
Phase
[7]
Phase
[15]
Phase
[23]
Phase
[31]
7.2.98
27 - 24
Phase
[6]
Phase
[14]
Phase
[22]
Phase
[30]
23 - 20
Phase
[5]
Phase
[13]
Phase
[21]
Phase
[29]
19 - 16
Phase
[4]
Phase
[12]
Phase
[20]
Phase
[28]
15 - 12
Phase
[3]
Phase
[11]
Phase
[19]
Phase
[27]
11 - 8
Phase
[2]
Phase
[10]
Phase
[18]
Phase
[26]
7-4
Phase
[1]
Phase
[9]
Phase
[17]
Phase
[25]
3-0
Phase
[0]
Phase
[8]
Phase
[16]
Phase
[24]
Byte Location
00h
04h
08h
0Ch
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and
1C0h
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-2 Table Entry Size in 4 Bits
63 - 56
Phase
[15:14]
Phase
[31:30]
Phase
[47:46]
Phase
[63:62]
Phase
[79:78]
Phase
[95:94]
Phase
[111:110]
Phase
[127:126]
7.2.99
55 - 48
Phase
[13:12]
Phase
[29:28]
Phase
[45:44]
Phase
[61:60]
Phase
[77:76]
Phase
[93:92]
Phase
[109:108]
Phase
[125:124]
47 - 40
Phase
[11:10]
Phase
[27:26]
Phase
[43:42]
Phase
[59:58]
Phase
[75:74]
Phase
[91:90]
Phase
[107:106]
Phase
[123:122]
39 - 32
Phase
[9:8]
Phase
[25:24]
Phase
[41:40]
Phase
[57:56]
Phase
[73:72]
Phase
[89:88]
Phase
[105:104]
Phase
[121:120]
31 - 24
Phase
[7:6]
Phase
[23:22]
Phase
[39:38]
Phase
[55:54]
Phase
[71:70]
Phase
[87:86]
Phase
[103:102]
Phase
[119:118]
23 - 16
Phase
[5:4]
Phase
[21:20]
Phase
[37:36]
Phase
[53:52]
Phase
[69:68]
Phase
[85:84]
Phase
[101:100]
Phase
[117:116]
15 - 8
Phase
[3:2]
Phase
[19:18]
Phase
[35:34]
Phase
[51:50]
Phase
[67:66]
Phase
[83:82]
Phase
[99:98]
Phase
[115:114]
7-0
Phase
[1:0]
Phase
[17:16]
Phase
[33:32]
Phase
[49:48]
Phase
[65:64]
Phase
[81:80]
Phase
[97:96]
Phase
[113:112]
Byte Location
00h
08h
10h
18h
20h
28h
30h
38h
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
BIT
15:0
FUNCTION
Extended
Capabilities ID
TYPE
RO
DESCRIPTION
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
Page 65 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.100
CAPABILITY VERSION – OFFSET 20Ch
BIT
FUNCTION
19:16
Capability Version
TYPE
DESCRIPTION
Read as 1h. Indicates PCIe Base Specification REV. 1.0a.
RO
Reset to 1h.
7.2.101
7.2.102
7.2.103
NEXT ITEM POINTER REGISTER – OFFSET 20Ch
BIT
FUNCTION
31:20
Next Capability
Offset
TYPE
DESCRIPTION
Read as 000h. No other ECP registers.
RO
Reset to 000h.
DATA SELECT REGISTER – OFFSET 210h
BIT
FUNCTION
TYPE
7:0
Data Selection
RW
31:8
Reserved
RO
DESCRIPTION
It indexes the power budgeting data reported through the data register.
When 00h, it selects D0 Max power budget
When 01h, it selects D0 Sustained power budget
Other values would return zero power budgets, which means not supported
Reset to 00h.
Reset to 000000h.
POWER BUDGETING DATA REGISTER – OFFSET 214h
BIT
FUNCTION
TYPE
7:0
Base Power
RO
9:8
12:10
14:13
17:15
Data Scale
PM Sub State
PM State
Type
RO
RO
DESCRIPTION
It specifies the base power value in watts. This value represents the required
power budget in the given operation condition. The default value may be
changed by auto-loading from EEPROM. The default value may be changed
by auto-loading from EEPROM.
Reset to 04h.
It specifies the scale to apply to the base power value. The default value may
be changed by auto-loading from EEPROM.
Reset to 00b.
It specifies the power management sub state of the given operation condition.
It is initialized to the default sub state.
RO
Reset to 000b.
It specifies the power management state of the given operation condition.
It defaults to the D0 power state. The default value may be changed by autoloading from EEPROM.
RO
Reset to 00b.
It specifies the type of the given operation condition.
It defaults to the Maximum power state. The default value may be changed by
auto-loading from EEPROM.
Reset to 111b.
It specifies the power rail of the given operation condition.
20:18
Power Rail
RO
31:21
Reserved
RO
Reset to 010b.
Reset to 0.
Page 66 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
7.2.104
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h
BIT
FUNCTION
TYPE
0
System Allocated
RO
DESCRIPTION
When set, it indicates that the power budget for the device is included within
the system power budget. The default value may be changed by auto-loading
from EEPROM.
31:1
Reserved
RO
Reset to 0b.
Reset to 0.
Page 67 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
8
CLOCK SCHEME
The PI7C9X20404GP requires 100MHz differential clock inputs through REFCLKP and REFCLKN Pins as
shown in the following table.
Table 8-1 Input Clock Requirements
Symbol
ClkInFREQ
ClkInDC
TR, TF
VSW
Description
Reference input clock range
Duty cycle of input clock
Rise/Fall time of input clock
Differential input voltage swing
Min
40
(peak-to-peak)
800
(zero-to-peak)
400
a. RCUI (Reference Clock Unit Interval) refers to the reference clock period
Page 68 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
Typical
100
50
-
Max.
60
0.2
2000
1000
Unit
MHz
%
RCUIa
mV
mV
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
9 HOT PLUG OPERATION
The PI7C9X20404GP is compliant with the PCI Standard Hot-Plug Controller (SHPC) and Subsystem
Specification Revision 1.0.
Systems with the Hot Plug capability allow the attachment and removal of components from the running system
without severely affecting the normal operation of the system. This feature prevents down-time of the system when
faulty components need to be replaced or the re-configuration of the system needs to be performed. This feature also
allows the system to isolate a faulty component and maintain the stability of the rest of the system upon the
detection of such event. Each downstream port of the device has its own Hot Plug Controller, which operates
independently from the others. The Hot Plug Controller of the device provides the parallel interface bus to the slot,
and, therefore, no extra logic is required to convert the signals from the serial interface bus into parallel.
The Hot Plug operation of the PI7C9X20404GP is implemented by the Hot Plug Signal Pins (Section 3.3) and Hot
Plug Capability related register sets (Section 7.2.71 to 7.2.73). The Hot Plug Signal Pins of the device consist of
"PWR_IND", "ATT_IND", "ATT_BTN", "MRL_PDC", "PWR_ENA_L" and "PWR_FLT" pins. The Hot Plug
Capability register sets provide Hot Plug related status reporting. Additionally, the register sets provide interrupt
messaging, which signal the occurrences of various Hot Plug events that take place on the slots. Upon receiving of
the interrupt events, the system software can use the Hot Plug Capability registers to respond to these events.
Page 69 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
10 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X20404GP for board-level continuity test and diagnostics. The TAP pins assigned are TCK,
TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
10.1 INSTRUCTION REGISTER
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up.
PI7C9X20404GP implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined
instruction codes are shown in Table 10-1. Those bit combinations that are not listed are equivalent to the BYPASS
(11111) instruction:
Table 10-1 Instruction register codes
Instruction
EXTEST
SAMPLE
HIGHZ
CLAMP
Operation Code (binary)
00000
00001
00101
00100
Register Selected
Boundary Scan
Boundary Scan
Bypass
Bypass
IDCODE
01100
Device ID
BYPASS
INT_SCAN
MEM_BIST
11111
00010
01010
Bypass
Internal Scan
Memory BIST
Operation
Drives / receives off-chip test data
Samples inputs / pre-loads outputs
Tri-states output and I/O pins except TDO pin
Drives pins from boundary-scan register and selects Bypass
register for shifts
Accesses the Device ID register, to read manufacturer ID, part
number, and version number
Selected Bypass Register
Scan test
Memory BIST test
10.2 BYPASS REGISTER
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a
bypass instruction is in effect. This allows rapid movement of test data to and from other components on the
board. This path can be selected when no test operation is being performed on the PI7C9X20404GP.
10.3 DEVICE ID REGISTER
This register identifies Pericom as the manufacturer of the device and details the part number and revision
number for the device.
Table 10-2 JTAG device ID register
Bit
31-28
27-12
11-1
0
Type
RO
RO
RO
RO
Value
0001
1001001000000100
01000111111
1
Description
Version number
Last 4 digits (hex) of the die part number
Pericom identifier assigned by JEDEC
Fixed bit equal to 1’b1
Page 70 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
10.4 BOUNDARY SCAN REGISTER
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by
connected the internal signal of the PI7C9X20404GP package pins. The VDD, VSS, and JTAG pins are not
in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is
TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function. Data may be
loaded into the boundary scan register master cells from the device input pins and output pin-drivers in
parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising
edge of TCK.
10.5 JTAG BOUNDARY SCAN REGISTER ORDER
Table 10-3 JTAG boundary scar register definition
Boundary Scan
Register Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Pin Name
CLKREQ1_L
DWNRST_L[1]
CLKREQ2_L
DWNRST_L[2]
CLKREQ3_L
DWNRST_L[3]
PERST_L
WAKE_L
DEBUG_OUT[0]
DEBUG_OUT[1]
DEBUG_OUT[2]
DEBUG_OUT[3]
DEBUG_OUT[4]
DEBUG_OUT[5]
Ball Location
H15
P11
P12
P13
N14
L14
K14
H14
G14
D16
D15
C16
C15
C14
DEBUG_OUT[6]
DEBUG_OUT[7]
DEBUG_OUT[8]
DEBUG_OUT[9]
DEBUG_OUT[10]
DEBUG_OUT[11]
GPIO[0]
B16
B15
B14
A16
A15
A14
A13
GPIO[1]
B13
GPIO[2]
A12
GPIO[3]
B12
GPIO[4]
A11
GPIO[5]
B11
GPIO[6]
A10
GPIO[7]
B10
PWR_IND[1]
PWR_IND[2]
PWR_IND[3]
D2
E1
F1
Page 71 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
Type
Input
Output2
Input
Output2
Input
Output2
Input
Input
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Control
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Bidir
Control
Output2
Output2
Output2
Tri-state Control Cell
14
14
14
14
14
14
14
14
14
14
14
14
22
24
26
28
30
32
34
36
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
Boundary Scan
Register Number
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Pin Name
ATT_IND[1]
ATT_IND[2]
ATT_IND[3]
ATT_BTN[1]
ATT_BTN[2]
ATT_BTN[3]
MRL_PDC[1]
MRL_PDC[2]
MRL_PDC[3]
PWR_ENA[1]
PWR_ENA[2]
PWR_ENA[3]
PWR_FLT[1]
PWR_FLT[2]
PWR_FLT[3]
LANEACT[0]
LANEACT[1]
LANEACT[2]
LANEACT[3]
EECLK
EEPD
Ball Location
G3
G1
H1
F2
F3
G2
H3
J3
K3
L3
M3
P3
P4
P5
P6
J1
K1
L1
M1
N1
N2
Page 72 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
Type
Output2
Output2
Output2
Input
Input
Input
Input
Input
Input
Output2
Output2
Output2
Input
Input
Input
Output2
Output2
Output2
Output2
Output2
Bidir
Control
Tri-state Control Cell
61
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
11 POWER MANAGEMENT
The PI7C9X20404GP supports D0, D1, D2, D3-hot, and D3-cold Power States. The PCI Express Physical Link
Layer of the PI7C9X20404GP device supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3
ready and L3 Power States.
During the transition from D3-hot to D3-cold state, the main power supplies of VDDC and VDDR are turned off to
save power while keeping the VDDCAUX and VAUX with the auxiliary power supplies to maintain all necessary
information to be restored to the full power D0 state. PI7C9X20404GP has been designed to have sticky registers
that are powered by auxiliary power supplies. PI7C9X20404GP forwards power management messages to the
upstream Switches or root complex.
PI7C9X20404GP also supports ASPM (Active State Power Management) to facilitate the link power saving.
PI7C9X20404GP supports beacon generation and WAKEUP_L signal.
Page 73 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
12 ELECTRICAL AND TIMING SPECIFICATIONS
12.1 ABSOLUTE MAXIMUM RATINGS
Table 12-1 Absolute maximum ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
-65oC to 150oC
-40oC to 85oC
-0.3v to 3.0v
Storage Temperature
Ambient Temperature with power applied
PCI Express supply voltage to ground potential (VDDA, VDDC, and
VDDCAUX)
DC input voltage for PCI Express signals
-0.3v to 3.0v
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
12.2 DC SPECIFICATIONS
Table 12-2 DC electrical characteristics
Power Pins
VDDA
VDDR
VDDC
VAUX
VDDCAUX
VTT
Min.
0.9v
3.0v
0.9v
3.0v
0.9v
VDDC
Typ.
1.0v
3.3v
1.0v
3.3v
1.0v
1.5v
Max.
1.1v
3.6v
1.1v
3.6v
1.1v
1.8v
VDDA: analog power supply for PCI Express Interface
VDDR: digital power supply for 3.3v I/O Interface
VDDC: digital power supply for the core
VAUX: digital auxiliary power supply for 3.3v I/O Interface
VDDCAUX: digital auxiliary power supply for the core
VTT: transmit termination power supply for PCI Express Interface
In order to support auxiliary power management fully, it is recommended to have VDDC and VDDCAUX
separated.
The typical power consumption of PI7C9X20404GP is about 0.8 watt.
Page 74 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
12.3 AC SPECIFICATIONS
Table 12-3 Transmitter Characteristics
Symbol
Description
Voltage Parameters
VTX-DIFFa
Output voltage compliance @ typical swing
VTX-DIFFp (peak-to-peak, single ended)
VTX-DIFFpp (peak-to-peak, differential)
VSW
Supported TX output voltage range (pp,
differential)
VOL
Low-level output voltage
VOH
High-level output voltage
VTX-CM-AC
Transmit common-mode voltage in L0
VTX-CM-HiZ
Transmit common-mode voltage in L0s
(TX) & L1
VTX-DE-RATIO
De-emphasized differential output voltage
VTX-IDLE-DIFFp
Electric Idle differential peak voltage
Voltage change during Receive Detection
VTX-RCV-
Min
Typical
Max.
Unit
400
800
400b
500
1000
600
1200
1500c
mV
mV
mV
0.50
VTT - 1.5 *VTX-DIFFp
VTT - 0.5VTX-DIFFp
VTT - VTX-DIFFp
VTX-CM-AC
0
1.45
-7.96
20
VTX-DIFFp
V
V
V
V
dB
mV
mV
DETECT
RLTX-DIFF
RLTX-CM
ZOSE
ZTX-DIFF-DC
TTX-RISE, TTX-
Transmitter Differential Return loss
Transmitter Common Mode Return loss
Single-ended output impedance
DC Differential TX Impedance
Rise / Fall time of TxP, TxN outputs
10
6
40
80
80
dB
dB
Ω
Ω
ps
50
100
60
120
110d
400
400.12
0.25e
ps
UI
UI
0.125
UI
UI
UI
UI
4
11
11
2+
200ps
6
12
16
ns
30
80
ns
10
1
10.2
2
us
ns
FALL
Jitter Parameters
UI
Unit Interval
TTX-MAX-JITTER
Transmitter total jitter (peak-to-peak)
TTX-EYE
Minimum TX Eye Width (1 - TTX-MAXJITTER)
Maximum time between the jitter median
TTX-EYEand
MEDIAN-tomaximum deviation from the median
MAX-JITTER
Timing Parameters
LTLAT-10
Transmitter data latency (for n=10)
LTLAT-20
Transmitter data latency (for n=20)
LTX-SKEW
Transmitter data skew between any 2 lanes
399.88
0.75
9
9
0
Maximum time to transition to a valid
electrical idle after sending an Electrical
Idle ordered set
TEIExit
Time to exit Electrical Idle (L0s) state into
L0
TBTEn
Time from asserting BeaconTxEn to
beacon being transmitted on the lane
TRxDetectEn
Pulse width of RxDetectEn input
9.8
TRxDetect
RxDetectEn falling edge to RxDetect
delay
a. Measured with Vtt = 1.2V, HiDrv=’0’,LowDrv=’0’ and Dtx=’0000’.
b. Minimum swing assumes LoDrv = 1, HiDrv = 0 and Dtx =1100
c. Max swing assumes LoDrv = 0, HiDrv = 1, Dtx = 0010, VTT = 1.8V
d. As measured between 20% and 80% points. Will depend on package characteristics.
e. Measured using PCI Express Compliance Pattern
TTX-IDLE-SET-
ns
TO-IDLE
Page 75 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
Table 12-4 Receiver Characteristics
Symbol
Description
Voltage Parameters
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
Differential input threshold voltage (peakVRX-IDLE-DETto-peak) to assert TxIdleDetect output
DIFFp-p
VRX-CM-AC
Receiver common-mode voltage for ACcoupling
Rise time / Fall time of RxP, RxN inputs
TRX-RISE, TRX-
Min
Typical
170
65
0
Max.
Unit
1200
175
mV
mV
150
mV
160
Ps
120
60
60
Ω
Ω
Ω
FALL
ZRX-DIFF-DC
ZRX-COM-DC
ZRX-COM-INITIAL-
Differential input impedance (DC)
80
Single-ended input impedance
40
Initial input common mode impedance
5
(DC)
DC
Powered down input common mode
200k
ZRX-COM-HIGHimpedance (DC)
IMP-DC
RLRX-DIFF
Receiver Differential Return Lossa
10
RLRX-CM
Receiver Common Mode Return Lossb
6
Jitter Parameters
TRX-MAX-JITTER
Receiver total jitter tolerance
TRX-EYE
Minimum Receiver Eye Width
0.35
Maximum time between jitter median and
TRX-EYE-MEDIANmax deviation from median
to-MAX-JITTER
Timing Parameters
LRLAT-10
Receiver data latency for n=10
28
LRLAT-20
Receiver data latency for n=20
49
TRX-SKEW
Receiver data skew between any 2 lanes
0
TBDDly
Beacon-Activity on channel to detection of
Beacond
TRXDelay from detection of Electrical Idle
IDLE_ENTER condition on the channel to assertion of
TxIdleDetect output
TRXDelay from detection of L0s to L0
IDLE_EXIT
transition to deassertion of TxIdleDetect
output
a. Over a frequency range of 50 MHz to 1.25 GHz.
b. Over a frequency range of 50 MHz to 1.25 GHz.
c. Assuming synchronized bit streams at the respective receiver inputs.
d. This is a function of beacon frequency
Page 76 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
100
50
50
Ω
dB
dB
0.65
0.325
UI
UI
UI
29
60
1c
200
bits
bits
bits
us
10
20
ns
5
10
ns
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
13 PACKAGE INFORMATION
The package of PI7C9X20404GP is a 12mm x 12mm LFBGA (148 Pin) package. The ball pitch is 0.8mm and the
ball size is 0.5mm. The following are the package information and mechanical dimension:
Figure 13-1 Bottom view drawing
Page 77 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
Figure 13-2 Package outline drawing
Page 78 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacketTM Family
Datasheet
14 ORDERING INFORMATION
Part Number
PI7C9X20404GP□NBE
PI 7C 9X20404GP
Temperature Range
-40o to 85oC
(Industrial Temperature)
NB E
Blank=Standard
E=Pb-Free and Green
Package Code
Blank=Standard
=Revision
Device Type
Device Number
Family
PI=Pericom
Page 79 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
Package
148-pin LFBGA
12mm x 12mm
Pb-Free & Green
Yes
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