PI7C9X2G404SLBFDEX

PI7C9X2G404SL PCI EXPRESS GEN 2 PACKET SWITCH 4-Port, 4-Lane, SlimPacket PCIe2.0 Packet Switch DATASHEET REVISION 2-2 September 2017 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS40068 Rev 2-2 PI7C9X2G404SL IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes w ithout further notice to this document and any product described herein. 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Copyright © 2016, Diodes Incorporated www.diodes.com PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 2 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL REVISION HISTORY Date 06/09/10 10/19/10 Revision Number 0.1 0.2 07/12/11 0.3 11/23/11 0.4 06/27/12 0.5 07/25/12 1.0 01/02/13 1.1 07/15/14 1.2 10/22/14 11/17/14 1.3 1.4 07/16/15 1.5 09/07/15 12/23/15 1.6 1.7 03/04/16 1.8 05/12/17 1.9 08/29/17 2-2 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Description Preliminary Datasheet Added Section 6 EEPROM Interface And System M anagement Bus Added Section 7 Register Description Added Industrial Temperature Support (Section 1 Features, Section 11.1 Absolute M aximum Ratings, Section 13 Ordering Information) Updated Section 1 Features (integrated reference clock) Updated Section 3.1 PCI Express Interface Signals (Added REFCLKI_P, REFCLKI_N, REFCLKO_P[3:0], REFCLKO_N[3:0], and IREF) Updated Section 3.2 Port Configuration Signals (RXPOLINV_DIS) Updated Section 3.3 M iscellaneous Signals (TEST4 and TEST5) Updated Section 1 Features (OBFF and LTR support) Updated Section 3 Pin Description (RXPOLINV_DIS, PRSNT [3:1], TEST4, T EST5, and CVDDR) Updated Section 6 EEPROM Interface And System M anagement Bus Updated Section 7 Register Description Updated Section 3 Pin Description (PWR_SAV, TCK, and TRST_L) Added Section 11.4 AC Switching Characteristics of Clock Buffer Updated Table 8-1 Clock Requirement Updated Table 3.5 Power Pins Updated Table 4.1 Pin List of 129-Pin LQFP Updated Section 1 (512-byte maximum payload size support, No-blocking capability) Updated Section 3.2 Port Configuration Signals Updated Section 3.3 M iscellaneous Signals Updated Section 5.1 Physical Layer Circuit Updated Section 5.1.7 Drive De-Emphasis Updated Section 7.2.75 Device Capabilities Register (M ax_Payload_Size Supported) Updated Section 13 Ordering Information Updated Table 11-2 DC Electrical Characteristics Updated Section 13 Ordering Information Updated Section 7.2 Transparent M ode Configuration Registers Updated Section 8 Clock Scheme Updated Section 3.1 PCI Express Interface Signals Updated Section 3.2 Port Configuration Signals Updated Section 5.1 Physical Layer Circuit Updated Section 6.1 EEPROM Interface Updated Section 7.2 Transparent M ode Configuration Registers Updated Section 8 Clock Scheme Updated Table 9-1 Instruction Register Codes Updated Table 9-2 JTAG Device ID Register Updated Table 9-3 JTAG Boundary Scan Register Definition Updated Table 11-2 DC Electrical Characteristics Updated Table 11-1 Absolute M aximum Ratings Updated Section 3 PIN Description Updated Table 11-1 Absolute M aximum Ratings Updated Table 11-2 DC Electrical Characteristics Added Section 11 Power Sequence Updated Section 4.1 Pin List Of 128-Pin LQFP Updated Section 12.1 Absolute M aximum Ratings Added Section 12.4 Operating Ambient Temperature Updated Section 12.4 Operating Ambient Temperature Added Section 12.5 Power Consumption Updated Section 1 Features Updated Section 3.2 Port Configuration Signals Updated Section 5.1 Physical Layer Circuit Updated Section 6.1.4 M apping EEPROM Contents to Configuration Registers Updated Section 7.2 Transparent M ode Configuration Registers Updated Section 12.1 Absolute M aximum Ratings Updated Table 12-2 DC Electrical Characteristics Page 3 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL Added Section 12.4 Operating Ambient Temperature Added Section 12.5 Power Consumption Revision numbering system changed to whole number PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 4 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL TABLE OF CONTENTS 1 FEATUR ES ....................................................................................................................................................................................... 10 2 GEN ERAL DES CRIPTION ......................................................................................................................................................... 11 3 PIN DES CRIPTION ....................................................................................................................................................................... 13 3.1 3.2 3.3 3.4 3.5 4 PIN ASSIGNMENTS ...................................................................................................................................................................... 17 4.1 5 PCI EXPRESS INTERFACE SIGNA LS .................................................................................................................... 13 PORT CONFIGURATION SIGNA LS ........................................................................................................................14 MISCELLANEOUS SIGNA LS....................................................................................................................................14 JTA G BOUNDARY SCAN SIGNA LS .......................................................................................................................15 POW ER PINS ..................................................................................................................................................................16 PIN LIST OF 128-PIN LQFP .........................................................................................................................................17 FUNCTIONAL DES CRIPTION ................................................................................................................................................. 18 5.1 PHYSICA L LA YER CIRCUIT ....................................................................................................................................18 5.1.1 RECEIVER DETECTION .................................................................................................................................... 18 5.1.2 RECEIVER SIGNAL DETEC TION .................................................................................................................... 18 5.1.3 RECEIVER EQUALIZATION ............................................................................................................................. 19 5.1.4 TRANSMITTER S WING ....................................................................................................................................... 19 5.1.5 DRIVE AMPLITUDE AN D DE-EMPHASIS SETTINGS ............................................................................... 19 5.1.6 DRIVE AMPLITUDE............................................................................................................................................ 20 5.1.7 DRIVE DE-EMPHASIS ........................................................................................................................................ 21 5.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY ............................................................................................ 21 5.2 DATA LINK LA YER (DLL) ........................................................................................................................................21 5.3 TRANSACTION LA YER RECEIVE BLOCK (TLP DECAPSULATION) ........................................................ 22 5.4 ROUTING ........................................................................................................................................................................22 5.5 TC/ VC MAPPING ..........................................................................................................................................................22 5.6 QUEUE .............................................................................................................................................................................22 5.6.1 PH ............................................................................................................................................................................ 23 5.6.2 PD ............................................................................................................................................................................ 23 5.6.3 NPHD ...................................................................................................................................................................... 23 5.6.4 CPLH ....................................................................................................................................................................... 23 5.6.5 CPLD ....................................................................................................................................................................... 23 5.7 TRANSACTION ORDERING .....................................................................................................................................23 5.8 PORT ARBITRATION ..................................................................................................................................................24 5.9 VC A RBITRATION .......................................................................................................................................................24 5.10 FLOW CONTROL ..........................................................................................................................................................24 5.11 TRANSATION LA YER TRANSMIT BLOCK (TLP ENCAPSULATION) ....................................................... 25 6 EEPROM INTERFACE AND S YSTEM MANAGEMENT B US ...................................................................................... 26 6.1 EEPROM INTERFA CE .................................................................................................................................................26 6.1.1 AUTO MODE EERPOM ACCESS ..................................................................................................................... 26 6.1.2 EEPROM MODE AT RESET .............................................................................................................................. 26 6.1.3 EEPROM SPACE ADDRESS MAP.................................................................................................................... 26 6.1.4 MAPPIN G EEPROM CONTENTS TO C ONFIGURATION REGISTERS .................................................. 29 6.2 SMBUS INTERFA CE .....................................................................................................................................................37 7 REGISTER DES CRIPTION ........................................................................................................................................................ 38 7.1 REGISTER TYPES.........................................................................................................................................................38 7.2 TRANSPA RENT MODE CONFIGURATION REGISTERS ................................................................................ 38 7.2.1 VENDOR ID REGISTER – OFFSET 00h ......................................................................................................... 40 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 5 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 7.2.43 7.2.44 7.2.45 7.2.46 7.2.47 7.2.48 7.2.49 7.2.50 7.2.51 7.2.52 7.2.53 7.2.54 7.2.55 7.2.56 7.2.57 DEVICE ID REGISTER – OFFSET 00h ........................................................................................................... 40 COMMAND REGISTER – OFFSET 04h .......................................................................................................... 40 PRIMARY STATUS REGISTER – OFFSET 04h.............................................................................................. 41 REVISION ID REGISTER – OFFSET 08h ....................................................................................................... 42 CLASS CODE REGISTER – OFFSET 08h ....................................................................................................... 42 CACHE LINE REGISTER – OFFSET 0Ch....................................................................................................... 42 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................................................... 42 HEADER TYPE REGISTER – OFFSET 0Ch ................................................................................................... 42 PRIMARY BUS NUMBER REGIS TER – OFFSET 18h.................................................................................. 42 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................... 42 SUBORDINATE BUS N UMBER REGISTER – OFFSET 18h....................................................................... 43 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ..................................................................... 43 I/O BASE ADDRESS REGISTER – OFFSET 1Ch .......................................................................................... 43 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ......................................................................................... 43 SECONDARY STATUS REGISTER – OFFSET 1Ch ...................................................................................... 43 MEMORY BASE ADDRESS REGISTER – OFFSET 20h............................................................................... 44 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ............................................................................. 44 PREFETC HABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h............................................. 44 PREFETC HABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ........................................... 44 PREFETC HABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ............. 45 PREFETC HABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ........... 45 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ............................................................ 45 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................................... 45 CAPABILITY POIN TER REGISTER – OFFSET 34h ..................................................................................... 45 INTERRUPT LINE REGISTER – OFFSET 3Ch.............................................................................................. 46 INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................................ 46 BRIDGE C ONTROL REGISTER – OFFSET 3Ch ........................................................................................... 46 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ......................................................... 47 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ...................................................................... 47 PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................... 48 DATA REGISTER – OFFSET 44h...................................................................................................................... 48 MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only).................................................. 48 MESSAGE CON TROL REGISTER – OFFSET 4Ch (Downstream Port Only).......................................... 48 MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) ........................................... 48 MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) ............................ 49 MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ................................................... 49 VPD CAPABILITY REGISTER – OFFSET 5Ch (Upstream Port Only)...................................................... 49 VPD REGISTER – OFFSET 5Ch (Upstream Port Only) ............................................................................... 49 VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ................................................................... 49 VENDOR SPECIFIC CAPABILITY REGIS TER – OFFSET 64h ................................................................. 50 XPIP CSR0 – OFFSET 68h (Test Purpose Only) ............................................................................................ 50 XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) ........................................................................................... 50 REPLAY TIME-OUT C OUNTER – OFFSET 70h ........................................................................................... 50 ACKNOWLEDGE LATENCY TIMER – OFFSET 70h ................................................................................... 50 SWITCH OPERATION MODE – OFFSET 74h (Upstream Port Only) ...................................................... 51 SWITCH OPERATION MODE – OFFSET 74h (Downstream Port Only) ................................................. 52 XPIP_CSR2 – OFFSET 78h ................................................................................................................................ 52 PHY PARAMETER 1 – OFFSET 78h ................................................................................................................ 52 PHY PARAMETER 2 – OFFSET 7Ch ............................................................................................................... 53 XPIP_CSR3 – OFFSET 80h ................................................................................................................................ 54 XPIP_CSR4 – OFFSET 84h ................................................................................................................................ 54 XPIP_CSR5 – OFFSET 88h ................................................................................................................................ 54 TL_CSR – OFFSET 8Ch ...................................................................................................................................... 54 PHY PARAMETER 3 – OFFSET 90h ................................................................................................................ 55 PHY PARAMETER 4 - OFFSET 94h................................................................................................................. 55 OPERATION MODE –OFFSET 98h ................................................................................................................. 56 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 6 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.58 7.2.59 7.2.60 7.2.61 7.2.62 7.2.63 7.2.64 7.2.65 7.2.66 7.2.67 7.2.68 7.2.69 7.2.70 7.2.71 7.2.72 7.2.73 7.2.74 7.2.75 7.2.76 7.2.77 7.2.78 7.2.79 7.2.80 7.2.81 7.2.82 7.2.83 7.2.84 7.2.85 7.2.86 7.2.87 7.2.88 7.2.89 7.2.90 7.2.91 7.2.92 7.2.93 7.2.94 7.2.95 7.2.96 7.2.97 7.2.98 7.2.99 7.2.100 7.2.101 7.2.102 7.2.103 7.2.104 7.2.105 7.2.106 7.2.107 7.2.108 7.2.109 7.2.110 7.2.111 7.2.112 7.2.113 SSID/SSVID CAPABILITY REGISTER – OFFSET B0h................................................................................. 56 SUBSYSTEM VENDOR ID REGISTER – OFFSET B4h ................................................................................ 56 SUBSYSTEM ID REGISTER – OFFSET B4h .................................................................................................. 56 GPIO C ONTROL REGISTER – OFFSET B8h (Upstream Port Only) ........................................................ 56 EEPROM CON TROL REGIS TER – OFFSET BCh (Upstream Port Only) ................................................ 58 EEPROM ADDRESS REGIS TER – OFFSET BCh (Upstream Port Only) ................................................. 58 EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only) ......................................................... 58 PCI EXPRESS CAPABILITY REGISTER – OFFSET C0h ............................................................................ 59 DEVICE CAPABILITIES REGISTER – OFFSET C4h ................................................................................... 59 DEVICE CON TROL REGISTER – OFFSET C8h ........................................................................................... 60 DEVICE STATUS REGIS TER – OFFSET C8h................................................................................................ 61 LINK CAPABILITIES REGISTER – OFFSET CCh ........................................................................................ 61 LINK C ONTROL REGISTER – OFFSET D0h................................................................................................. 62 LINK STATUS REGISTER – OFFSET D0h ..................................................................................................... 63 SLOT C APABILITIES REGISTER – OFFSET D4h (Downstream Port Only) .......................................... 63 SLOT C ONTROL REGISTER – OFFSET D8h (Downstream Port Only)................................................... 64 SLOT S TATUS REGISTER OFFSET D8h (Downstream Port Only)........................................................... 65 DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h ................................................................................ 66 DEVICE CON TROL REGISTER 2 – OFFSET E8h ........................................................................................ 66 DEVIDE S TATUS REGISTER 2 – OFFSET E8h ............................................................................................ 66 LINK CAPABILITIES REGISTER 2 – OFFSET ECh ..................................................................................... 66 LINK C ONTROL REGISTER 2 – OFFSET F0h .............................................................................................. 66 LINK STATUS REGISTER 2 – OFFSET F0h................................................................................................... 67 SLOT C APABILITIES REGISTER 2 – OFFSET F4h ..................................................................................... 67 SLOT C ONTORL REGISTER 2 – OFFSET F8h ............................................................................................. 67 SLOT S TATUS REGISTER 2 – OFFSET F8h .................................................................................................. 67 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h .......... 67 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .......................................................... 67 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .............................................................. 68 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ..................................................... 69 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ............................................................... 70 CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ................................................................... 70 ADVANCE ERROR CAPABILITIES AND CON TROL REGISTER – OFFSET 118h ............................... 71 HEADER LOG REGISTER – OFFSET From 11Ch to 128h ......................................................................... 71 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h................................... 71 PORT VC CAPABILITY REGISTER 1 – OFFSET 144h ................................................................................ 71 PORT VC CAPABILITY REGISTER 2 – OFFSET 148h ................................................................................ 72 PORT VC C ONTROL REGISTER – OFFSET 14Ch....................................................................................... 72 PORT VC STATUS REGISTER – OFFSET 14Ch ........................................................................................... 72 VC RESOURCE CAPABILITY REGIS TER (0) – OFFSET 150h.................................................................. 73 VC RESOURCE C ONTROL REGISTER (0) – OFFSET 154h...................................................................... 73 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h .......................................................................... 74 VC RESOURCE CAPABILITY REGIS TER (1) – OFFSET 15Ch ............................................................ 74 VC RESOURCE C ONTROL REGISTER (1) – OFFSET 160h ................................................................. 74 VC RESOURCE STATUS REGISTER (1) – OFFSET 164h ...................................................................... 75 VC ARBITRATION TABLE REGISTER – OFFSET 170h ......................................................................... 75 PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ............................. 75 PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch ........................... 76 DATA SELECT REGISTER – OFFSET 210h .............................................................................................. 76 POWER BUDGETING DATA REGISTER – OFFSET 214h..................................................................... 76 POWER BUDGET C APABILITY REGISTER – OFFSET 218h ............................................................... 77 ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only) ...................... 77 ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only) ........................................... 77 EGRESS CON TROL VEC TOR – OFFSET 228h (Downstream Port Only) ........................................... 78 LTR EXTEN DED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only) ............................ 78 MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) ..................................... 78 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 7 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.114 MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only).............................. 79 8 CLOCK SCHEME .......................................................................................................................................................................... 80 9 IEEE 1149.1 COMPATIB LE JTAG CONTROLLER .......................................................................................................... 81 9.1 9.2 9.3 9.4 9.5 INSTRUCTION REGISTER.........................................................................................................................................81 BYPASS REGISTER .....................................................................................................................................................81 DEVICE ID REGISTER ................................................................................................................................................81 BOUNDA RY SCAN REGISTER ................................................................................................................................82 JTA G BOUNDARY SCAN REGISTER ORDER..................................................................................................... 82 10 POWER MANAGEMENT ........................................................................................................................................................... 84 11 POWER S EQUENCE..................................................................................................................................................................... 85 12 EL ECTRICAL AND TIMING SPECIFICATIONS.............................................................................................................. 86 12.1 12.2 12.3 12.4 12.5 ABSOLUTE MAXIMUM RATINGS .........................................................................................................................86 DC SPECIFICATIONS ..................................................................................................................................................86 AC SPECIFICATIONS ..................................................................................................................................................86 OPERATING AM BIENT TEMPERATURE............................................................................................................. 88 POW ER CONSUMPTION............................................................................................................................................88 13 PACKAGE INFORMATION....................................................................................................................................................... 89 14 ORDERING INFORMATION .................................................................................................................................................... 90 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 8 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL TABLE OF FIGURES FIGURE 5-1 DRIVER OUTPUT WAVEFORM.....................................................................................................................................20 FIGURE 6-1 SMBUS A RCHIT ECTURE IMPLEMENTATION ON PI7C9X2G404SL....................................................................... 37 FIGURE 11-1 INIT IAL POWER-UP SEQUENCE.................................................................................................................................85 FIGURE 13-1 PACKAGE OUT LINE DRAWING...................................................................................................................................89 LIST OF TABLES TABLE 5-1 RECEIVER DET ECTION THRESHOLD SETTINGS .......................................................................................................... 18 TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD.................................................................................................................... 19 TABLE 5-3 RECEIVER EQUALIZATION SETTINGS ..........................................................................................................................19 TABLE 5-4 TRANSMITTER SWING SETTINGS..................................................................................................................................19 TABLE 5-5 DRIVE A MPLIT UDE BASE LEVEL REGIST ERS............................................................................................................. 20 TABLE 5-6 DRIVE A MPLIT UDE BASE LEVEL SETTINGS ............................................................................................................... 20 TABLE 5-7 DRIVE DE-EMPHASIS BASE LEVEL REGIST ER ........................................................................................................... 21 TABLE 5-8 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ........................................................................................................... 21 TABLE 5-9 SUMMARY OF PCI EXPRESS ORDERING RULES......................................................................................................... 23 TABLE 6-1 SMBUS A DDRESS PIN CONFIGURATION..................................................................................................................... 37 TABLE 7-1 REGI ST ER A RRAY LAYOUT FOR VC A RBIT RATION.................................................................................................. 75 TABLE 7-2 TABLE ENT RY SIZE IN 4 BIT S.......................................................................................................................................76 TABLE 8-1 AC SWIT CHING CHARACT ERISTICS.............................................................................................................................80 TABLE 9-1 INST RUCT ION REGISTER CODES...................................................................................................................................81 TABLE 9-2 JTA G DEVICE ID REGIST ER..........................................................................................................................................81 TABLE 9-3 JTA G BOUNDARY SCAN REGIST ER DEFINITION....................................................................................................... 82 TABLE 12-1 A BSOLUTE M AXIMUM RAT INGS................................................................................................................................86 TABLE 12-2 DC ELECT RICAL CHARACTERISTICS.........................................................................................................................86 TABLE 12-3 PCI EXPRESS INTERFACE - DIFFERENT IAL TRANSMITTER (TX) OUT PUT (5.0 GBPS) CHARACTERIST ICS ..... 86 TABLE 12-4 PCI EXPRESS INTERFACE - DIFFERENT IAL TRANSMITTER (TX) OUT PUT (2.5 GBPS) CHARACTERIST ICS ..... 87 TABLE 12-5 PCI EXPRESS INTERFACE - DIFFERENT IAL RECEIVER (RX) INPUT (5.0 GBPS) CHARACT ERIST ICS ................ 87 TABLE 12-6 PCI EXPRESS INTERFACE - DIFFERENT IAL RECEIVER (RX) INPUT (2.5 GBPS) CHARACT ERIST ICS ................ 88 TABLE 12-7 OPERATING A MBIENT TEMPERATURE ..................................................................................................................... 88 TABLE 12-8 POWER CONSUMPTION................................................................................................................................................88 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 9 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 1 FEATURES • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-lane PCI Express Gen 2 Switch with 4 PCI Express ports Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching Peer-to-peer switching between any two downstream ports 150 ns typical latency for packet routed through Switch without blocking Integrated reference clock for downstream ports Strapped pins configurable with optional EEPROM or SMBus SMBus interface support Compliant with System Management (SM) Bus, Version 1.0 Compliant with PCI Express Base Specification Revision 2.1 Compliant with PCI Express CEM Specification Revision 2.0 Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Compliant with Advanced Configuration Power Interface (ACPI) Specification Reliability, Availability and Serviceability Supports Data Poisoning and End-to-End CRC Advanced Error Reporting and Logging IEEE 1149.1 JTAG interface support Advanced Power Saving Empty downstream ports are set to idle state to minimize power consumption Link Power Management Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states Active state power management for L0s and L1 states Device State Power Management Supports D0, D3Hot and D3Cold device power states 3.3V Aux Power support in D3Cold power state Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Extended Virtual Channel capability Two Virtual Channels (VC) and Eight Traffic Class (TC) support Disabled VCs’ buffer is assigned to enabled VCs for resource sharing Independent TC/VC mapping for each port Provides VC arb itration selections: Strict Priority, Round Robin (RR) and Programmab le Weighted RR Supports Isochronous Traffic Isochronous traffic class mapped to VC1 only Strict time based credit policing Supports up to 512-byte maximu m payload size Programmable driver current and de-emphasis level at each individual port Support Access Control Service (ACS) for peer-to-peer traffic Support Address Translation (AT) packet for SR-IOV application Support OBFF and LTR Low Power Dissipation: 650 mW typical in L0 normal mode Industrial Temperature Range -40o to 85o C 128-pin LQFP 14mm x 14mm package PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 10 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 2 GENERAL DESCRIPTION Similar to the role o f PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect architecture. The 4-Lane PCIe Switch is in 4-Port type configuration. It provides users the flexib ility to expand or fan-out the PCI Express lanes based on their application needs. In the PCI Exp ress Architecture, the PCIE Switch forwards posted and non-posted requests, and completion packets in either downstream or upstream direct ion concurrently as if a v irtual PCI Bridge is in operation on each port. By visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multip le virtual PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge during enumerat ion, each port is given a unique bus number, device nu mber, and function nu mber by the init iating software. The bus number, device nu mber, and function number are co mb ined to form a destination ID for each specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded address or destination ID. To ensure the packet integrity during forward ing, the Switch is not allowed to split the packets to mult iple s mall packets or merge the received packets into a large transmit packet. Also, the IDs of the requesters and completers are kept unchanged along the path between ingress and egress port. The Switch emp loys the architecture of Co mbined Input and Output Queue (CIOQ) in imp lementation. The main reason for choosing CIOQ is that the required memo ry bandwidth of input queue equals to the bandwidth of ingress port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at each ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port based on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass over each other in case that the addressed egress port is availab le to accept them. As to the packets required to follow the ordering rule, the Head-Of-Line (HOL) issue becomes unavoidable for packets destined to different egress ports since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it out. This can assure the maximu m throughput being achieved and therefore the Switch works efficiently. Another advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simp lified and streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port maintains the credits independently without checking other ports' credit availability, wh ich is otherwise required by pure output queue architecture. The Switch supports two virtual channels (VC0, VC1) and eight traffic classes (TC0 ~ TC7) at each port. The ingress port independently assigns packets into the preferred virtual channel while the egress port outputs the packet based on the predefined port and VC arb itration algorithm. For instance, the isochronous packet is given a special traffic class number other than TC0 and mapped into VC1 accord ingly. By employing the strict time based credit policy for port arbitration and assigning higher priority to VC1 than VC0, the Switch can therefore guarantee the time-sensitive packet is not blocked by regular traffic to assure the quality of service. In addition, some data-centric applications only carry TC0/ VC0 traffic. As a result, there are no packets that would consume VC1 bandwidth. In order to improve the efficiency of buffer usage, the unused VC1 queues can be reassigned to VC0 and enable each of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the performance of the PCIe Switch further. The Switch provides the advanced feature of Access Control Serv ice (A CS). This feature regulates which co mponents are allowed to commun icate with each other within the PCIe mu ltip le-point fabric, and allows the system to have more control over packet routing in the Switch. As a result, peer-to-peer traffic can be facilitated more accurately and efficiently. When the system also implements Address Translation Service (ATS), the peer-to-peer requests with translated address can be routed directly by enabling the corresponding option in ACS to avoid possible performance bottleneck associated with re-direction, which introduces extra latency and may increase link and RC congestion. The built-in Integrated Reference Clock Buffer of the PCI Exp ress Switch supports three reference clock outputs. The clock buffer is fro m a single 100MHz clock input, and distributes the clock source to three outputs, which can be PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 11 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL used by the downstream PCI Express end devices. The clock buffer feature can be enabled and disabled by strapping pin setting. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 12 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 3 PIN DESCRIPTION 3.1 PCI EXPRESS INTERFACE SIGNALS NAME REFCLKP REFCLKN PERP [3:0] PIN 110, 111 122, 102, 97, 128 TYPE I I PERN [3:0] 121, 103, 98, 127 I PET P [3:0] 118, 106, 100, 124 O PET N [3:0] 117, 107, 101, 123 O PERST _L 10 I DWNRST _L[3:1] 7, 6, 5 O REXT 116 I REXT _GND 115 I REFCLKI_P, REFCLKI_N REFCLKO_P[3:0], REFCLKO_N[3:0] 74, 73 I 76, 78, 81, 85, 75, 77, 80, 83 O IREF 86 I CLKBUF_PD 60 I PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N Re fe rence Clock Input Pair: Connect to 100MHz differential clock when integrated reference clock buffer is disabled (CLKBUF_PD=1), or connect to one of the Integrated Reference Clock Output Pairs (REFCLKO_P and REFCLKO_N) of this Switch when integrated reference clock buffer is enabled (CLKBUF_PD=0). T he input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. It is recommended that a 0.1uF be used in the AC-coupling. PCI Expre ss Data Serial Input Pairs: Differential data receive signals in four ports. Port 0 (Upstream Port) is PERP[0] and PERN[0] Port 1 (Downstream Port) is PERP[1] and PERN[1] Port 2 (Downstream Port) is PERP[2] and PERN[2] Port 3 (Downstream Port) is PERP[3] and PERN[3] PCI Expre ss Data Serial Output Pairs: Differential data transmit signals in four ports. Port 0 (Upstream Port) is PETP[0] and PETN[0] Port 1 (Downstream Port) is PETP[1] and PETN[1] Port 2 (Downstream Port) is PETP[2] and PETN[2] Port 3 (Downstream Port) is PETP[3] and PETN[3] System Reset (Active LOW): When PERST_L is asserted, the internal states of whole chip except sticky logics are initialized. Please refer to Table 11-2 for PERST _L spec. Downstream Device Reset (Active LOW): DWNRST_L provides a reset signal to the devices connected to the downstream ports of the switch. T he signal is active when either PERST_L is asserted or the device is just plugged into the switch. DWNRST _L [x] corresponds to Portx, where x= 1,2,3. Exte rnal Reference Resistor: Connect an external resistor (1.43K Ohm +/- 1%) to REXT_GND to provide a reference to both the bias currents and impedance calibration circuitry. Exte rnal Reference Resistor Ground: Connect to an external resistor to REXT . Inte grated Reference Clock Input Pair: Connect to external 100MHz differential clock for the integrated reference clock buffer. Inte grated Reference Clock Output Pairs: 100MHz external differential HCSL clock outputs for the integrated reference clock buffer. Diffe rential Reference Clock Output Current Resistor: External resistor (475 Ohm +/- 1%) connection to set the differential reference clock output current. Re fe rence Clock Output Pairs Power Down: When CLKBUF_PD is asserted high, the integrated reference clock buffer and Reference Clock Outputs are disabled. When it is asserted low, the integrated reference clock buffer and Reference Clock Outputs are enabled. This pin has internal pull-down. If no board trace is connected to this pin, the internal pull-down resistor of this pin is enough. However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. Page 13 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 3.2 PORT CONFIGURATION SIGNALS NAME VC1_EN 18 PIN TYPE I RXPOLINV_DIS 24 I PL_512B 53 I PRSNT [3:1] 21, 20, 19 I SLOT CLK 33 I SLOT _IMP[3:1] 47, 46, 45 I PORT ST ATUS[2:0] 69, 68, 67 O DESCRIPTIO N Virtual Channel 1 Re source Sharing Enable: The chip provides the capability to support virtual channel 1 (VC1), in addition to the standard virtual channel 0. When this pin is asserted high, Virtual Channel 1 is enabled, and virtual channel resource sharing is not available. When it is asserted low, the chip would allocate the additional VC1 resource to VC0, and VC1 capability is disabled. T his pin has internal pull-down resistor. If no board trace is connected to this pin, the internal pull-down resistor of this pin is enough. However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. Rx Polarity Inversion Disable: When RXPOLINV_DIS is asserted high, it indicates to disable Rx Polarity Inversion detection function. Otherwise, it indicates to enable Rx Polarity Inversion detection function. This pin has internal pull-down resistor. If no board trace is connected to this pin, the internal pull-down resistor of this pin is enough. However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. Max. Payload Size 512B: When PL_512B is asserted high, it indicates the max. payload size capability is 512B. Otherwise, it indicates the max. Payload size is 256B. This pin has internal pulldown resistor. If no board trace is connected to this pin, the internal pull-down resistor of this pin is enough. However, if pin is connected to a board trace and not driven, it is recommended that an external 330ohm pull-down resistor be used. Pre sent: When PRSNT is asserted low, it indicates that the device is present in the slot of downstream port. Otherwise, it indicates the absence of the device. PRSNT[x] is correspondent to Port x, where x=1,2,3. T hese pins have internal pull-down resistors. Slot Clock Configuration: It determines if the downstream component uses the same physical reference clock that the platform provides on the connector. When SLOT CLK is high, the platform reference clock is employed. By default, all downstream ports use the same physical reference clock provided by platform. T his pin has internal pull-down resistor. If no board trace is connected to this pin, the internal pull-down resistor of this pin is enough. However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. Slot Implemented: T hese signals are asserted to indicate that the downstream ports are connected to slots. SLOT_IMP[x] corresponds to Portx, where x= 1, 2, 3. When SLOT_IMP[x] is asserted, the Portx is connected to slot. Otherwise, it is chip-to-chip connection directly. T hese pins have internal pull-down resistors. If no board trace is connected to these pins, the internal pull-down resistors of these pins are enough. However, if pins are connected to a board trace and not driven, it is recommended that external 330-ohm pull-down resistors be used. Port Status: These signals indicate the status of each port. Please connect to pin header for debug used. PORT ST ATUS[x] is correspondent to Port x, where x=0, 1, 2. 3.3 MISCELLANEOUS SIGNALS NAME EECLK EEPD 70 71 SMBCLK 26 I SMBDAT A 27 I/O PI7C9X2G404SL Document Number DS40068 Rev 2-2 PIN TYPE O I/O DESCRIPTIO N EEPRO M Clock: Clock signal to the EEPROM interface. EEPRO M Data: Bi-directional serial data interface to and from the EEPROM. The pin is set to ‘1’ by default. SM Bus Clock: System management Bus Clock. This pin requires an external 5.1K-ohm pull-up resistor. SM Bus Data: Bi-Directional System Management Bus Data. This pin requires an external 5.1K-ohm pull-up resistor. Page 14 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL NAME SCAN_EN GPIO[7:0] PIN 44, 43, 42, 39, 38, 37, 35, 36 TYPE I/O I/O PWR_SAV 28 I T EST 3 T EST 5 T EST 6 T EST 4 17 25 51 22 I T EST 1 3.4 72 I 9 I T EST 2 16 I NC 48, 52, 54, 57, 58, 59, 114 DESCRIPTIO N Full-Scan Enable Control: For normal operation, SCAN_EN is an output with a value of “0”. SCAN_EN becomes an input during manufacturing testing. Ge neral Purpose Input and Output: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. When SMBus is implemented, GPIO[7:5] act as the SMBus address pins, which set Bit 2 to 0 of the SMBus address. De bug Mode Selection: In debug mode, GPIO[4:0] are used for Debug Mode Selection. Powe r Saving Mode: PWR_SAV is a strapping pin. When this pin is pulled high when system is reset, the Power Saving Mode is enabled. When this pin is pulled low when system is reset, the Power Saving Mode is disabled. When this pin is pulled low, it should be tied to ground through a 330-ohm pull-down resistor. When this pin is pulled high, a 5.1K-ohm pull-up resistor should be used. Te st3/5/6: These pins are for internal test purpose. T est3, T est5 and T est6 should be tied to ground through a 330-ohm pull-down resistor. Te st4: T he pin is for internal test purpose. It should be tied to ground through a 330-ohm pull-down resistor for normal operation. Port Status Output Enable: In debug mode, it is used to enable PortStatus output. Te st1: T he pin is for internal test purpose. It should be tied to 3.3V through a 5.1K-ohm pull-up resistor for normal operation. De bug Mode Enable: In debug mode, it need be tired to low through a 330-ohm pull-down resistor. Te st2: T he pin is for internal test purpose. Test2 should be tied to 3.3V through a 5.1K-ohm pull-up resistor. Not Connected: T hese pins can be just left open. JTAG BOUNDARY SCAN SIGNALS Name T CK 89 T MS 92 I T DO 88 O T DI 93 I T RST _L 94 I PI7C9X2G404SL Document Number DS40068 Rev 2-2 Pin Type I De scription Te st Clock: Used to clock state information and data into and out of the chip during boundary scan. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Te st Mode Select: Used to control the state of the Test Access Port controller. When JT AG boundary scan function is not implemented, this pin should be pulled low through a 330-Ohm pull-down resistor. Te st Data Output: When SCAN_EN is high, it is used (in conjunction with T CK) to shift data out of the Test Access Port (TAP) in a serial bit stream. When JT AG boundary scan function is not implemented, this pin should be left open (NC). Te st Data Input: When SCAN_EN is high, it is used (in conjunction with T CK) to shift data and instructions into the TAP in a serial bit stream. When JT AG boundary scan function is not implemented, this pin should be left open (NC). Te st Re set (Active LOW): Active LOW signal to reset the TAP controller into an initialized state. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 330-Ohm pull-down resistor. Page 15 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 3.5 POWER PINS NAME VDDC VDDR CVDDR VDDCAUX VAUX AVDD AVDDH CGND VSS PI7C9X2G404SL Document Number DS40068 Rev 2-2 PIN 3, 23, 29, 31, 40, 55, 62, 65, 91 1, 8, 49, 64, 96 79, 82, 84 13, 14 15 99, 105, 108, 119, 125 113 TYPE P 109, 112 2, 4, 11, 12, 30, 32, 34, 41, 50, 56, 61, 63, 66, 87, 90, 95, 104, 120, 126,129 P P DESCRIPTIO N VDDC Supply (1.0V): Used as digital core power pins. P P P P P VDDR Supply (3.3V): Used as digital I/O power pins. VDDR Supply (3.3V): Used as reference clock power pins. VDDCAUX Supply (1.0V): Used as auxiliary core power pins. VAUX Supply (3.3V): Used as auxiliary I/O power pins. AVDD Supply (1.0V): Used as PCI Express analog power pins. P AVDDH Supply (3.3V): Used as PCI Express analog high voltage power pins. Ground: Used as reference clock ground pins. VSS Ground: Used as ground pins. Page 16 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 4 PIN ASSIGNMENTS 4.1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 129 PIN LIST of 128-PIN LQFP NAME VDDR VSS VDDC VSS DWNRST _L[1] DWNRST _L[2] DWNRST _L[3] VDDR T EST 1 PERST _L VSS VSS VDDCAUX VDDCAUX VAUX T EST 2 T EST 3 VC1_EN PRSNT [1] PRSNT [2] PRSNT [3] T EST 4 VDDC RXPOLINV_DIS T EST 5 SMBCLK SMBDAT A PWR_SAV VDDC VSS VDDC VSS E_PAD PI7C9X2G404SL Document Number DS40068 Rev 2-2 PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME SLOT CLK VSS GPIO[1] GPIO[0] GPIO[2] GPIO[3] GPIO[4] VDDC VSS GPIO[5] GPIO[6] GPIO[7] SLOT _IMP[1] SLOT _IMP[2] SLOT _IMP[3] NC VDDR VSS T EST 6 NC PL_512B NC VDDC VSS NC NC NC CLKBUF_PD VSS VDDC VSS VDDR PIN 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Page 17 of 90 www.diodes.com NAME VDDC VSS PORT ST ATUS[0] PORT ST ATUS[1] PORT ST ATUS[2] EECLK EEPD SCAN_EN REFCLKI_N REFCLKI_P REFCLKO_N[3] REFCLKO_P[3] REFCLKO_N[2] REFCLKO_P[2] CVDDR REFCLKO_N[1] REFCLKO_P[1] CVDDR REFCLKO_N[0] CVDDR REFCLKO_P[0] IREF VSS T DO T CK VSS VDDC T MS T DI T RST _L VSS VDDR PIN 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME PERP[1] PERN[1] AVDD PET P[1] PET N[1] PERP[2] PERN[2] VSS AVDD PET P[2] PET N[2] AVDD CGND REFCLKP REFCLKN CGND AVDDH NC REXT _GND REXT PET N[3] PET P[3] AVDD VSS PERN[3] PERP[3] PET N[0] PET P[0] AVDD VSS PERN[0] PERP[0] September 2017 © Diodes Incorporated PI7C9X2G404SL 5 FUNCTIONAL DESCRIPTION Multiple virtual PCI-to-PCI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB contains the comp lete PCIe architecture layers that consist of the physical, data link, and transaction layer. The packets entering the Switch via one of VPPBs are first converted from serial bit-stream into parallel bus signals in physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to extract out the transaction header. According to the address or ID embedded in the transaction header, the entire transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the transmit circuits in the data link layer and physical layer. The following sections describe these function elements for processing PCIe packets within the Switch. 5.1 PHYSICAL LAYER CIRCUIT The physical layer circu it design is based on the PHY Interface for PCI Exp ress Architecture (PIPE). It contains Physical Media Attachment (PMA) and Physical Cod ing Sub-layer (PCS) b locks. PMA includes Serializer/ Deserializer (SERDES), PLL 1 , Clock Recovery module, receiver detection circuits, beacon transmitter, electrical idle detector, and input/output buffers. PCS consists of framer, 8B/10B encoder/decoder, receiver elastic buffer, and PIPE PHY control/status circuitries. To provide the flexib ility for port configuration, each lane has its own control and status signals for MA C to access individually. In addition, a pair of PRBS generator and checker is included for PHY built-in self test. The main functions of physical layer circuits include the conversion between serial-link and parallel bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of physical layer errors. In order to meet the needs of different application, the drive amp litude, de-emphasis and equalization of each transmitting channels can be adjusted using EEPROM indiv idually. De-emphasis of -3.5 db is imp lemented by the transmitters when full swing signaling is used, while an offset can be individually applied to each channel. 5.1.1 RECEIVER DETECTION The physical layer circu its imp lement receiver detection, wh ich detects the presence of an attached 50 oh m to ground termination as per PCI Express Specificat ion. The detect circuits determine if the voltage levels of the receiver have crossed the internal threshold after a configurable time determined by the Receiver Detection Threshold field in the PHY Parameter 2 Register (offset 7Ch, bit[6:4]), which can be configured by EEPROM or SMBUS settings. Table 5-1 Receiver Detection Threshold Settings Re ce ive r De te ction Thre shold 000 001 010 011 100 101 110 111 Thre shold 1.0 us 2.0 us 4.0 us (Recommended) 5.0 us 10 us 20 us 40 us 50 us 5.1.2 RECEIVER SIGNAL DETECTION 1 Multiple lanes could share the PLL. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 18 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL Receiver signal idling is detected with levels above a p rogrammable threshold specified by Receiver Signal Detect field in the PHY Parameter 2 Register (Offset 7Ch, bit [21:20]), wh ich can be configured on a per-port basis via EEPROM or SMBUS settings. Table 5-2 Receiver Signal Detect Threshold Re ce ive r Signal De te ct 00 01 (Recommended) 10 11 Min (mV ppd) 50 65 75 120 Max (mV ppd) 80 175 200 240 5.1.3 RECEIVER EQUALIZATION The receiver imp lements programmable equalizer v ia the Receiver Equalizat ion field in the PHY Parameter 2 Register (Offset 7Ch, bit[25:22]), which can be configured on a per-port basis via EEPROM or SMBUS settings. Table 5-3 Receiver Equalization Settings Re ce ive r Equaliz ation 0000 0010 0110 (Recommended) 1110 Equaliz ation Off Low Medium High 5.1.4 TRANSMITTER SWING The PCI Exp ress transmitters support implementations of both full voltage swing and half (lo w) voltage swing. In fu ll swing signaling mode, the transmitters implement de-emphasis, while in half swing mode, the transmitters do not. The Transmitter Swing field in the PHY Parameter 2 Register 2 (offset 7Ch, Bit [30]) is used for the selection of full swing signaling or half swing signaling, which can be configured on a per-port basis via EEPROM or SMBUS settings. Table 5-4 Transmitter Swing Settings Transmitte r Swing 0 1 Mode Full Voltage Swing Half Voltage Swing De -e mphasis Implemented Not implemented 5.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS Depending on the operation condition (voltage swing and de-emphasis condition), one of the Drive A mp litude Base Level fields in the Switch Operation Mode Register (o ffset 74h) and one of the Drive De-Emphasis Base Level fields in the PHY Parameter 1 Register (offset 7Ah) are active for configuration of the amplitude and de-emphasis. The final drive amp litude and drive de-emphasis are the summation of the base level value and the offset value. The offset value for drive amplitude is 25 mV pd, and 6.25 mV pd for drive de-emphasis. The driver output waveform is the synthesis of amplitude and de-emphasis. The driver amplitude without de-emphasis is specified as a peak differential voltage level (mVpd), and the driver de-emphasis modifies the driver amplitude. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 19 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL Amplitude + De-Emphasis Amplitude – De-Emphasis 1 1 1 1 0 0 0 0 - (Amplitude) + De-Emphasis - (Amplitude) – De-Emphasis Input digital wave form Output analog waveform Figure 5-1 Driver Output Waveform 5.1.6 DRIVE AMPLITUDE Only one of the Drive Amp litude Level field in the Switch Operation Mode Reg ister (offset 74h, bit [20:16], bit [25:21] and bit[30:26]) is active depending on the de-emphasis and swing condition. The settings and the corresponding values of the amplitude level, which can be configured by EEPROM or SMBUS settings. Table 5-5 Drive Amplitude Base Level Registers Re giste r C_DRV_LVL_3P5_NOM C_DRV_LVL_6P0_NOM C_DRV_LVL_HALF_NOM De -Emphasis Condition -3.5 db -6.0 db N/A Swing Condition Full Full Half Table 5-6 Drive Amplitude Base Level Settings Se tting Amplitude (mV pd) 0 25 50 75 100 125 150 Se tting Amplitude (mV pd) 175 200 225 250 275 300 325 Se tting Amplitude (mV pd) 350 375 400 425 450 475 Reserved 00000 00111 01110 00001 01000 01111 00010 01001 10000 00011 01010 10001 00100 01011 10010 00101 01100 10011 00110 01101 Others Note : 1. Nominal levels. Actual levels will vary with temperature, voltage and board effects. 2. T he maximum nominal amplitude of the output driver is 475 mV pd. Combined values of driver amplitude and de-emphasis greater than 475 mV pd should be avoided. 3. At higher amplitudes, actual swings will be less than the theoretical value due to process variations and environment factors, such as voltage overhead compression, package losses, board losses, and other effects. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 20 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 5.1.7 DRIVE DE-EMPHASIS The Drive De-Emphasis Level field in the PHY Parameter 1 Register (Offset 78h, bit[20:16], bit[25:21] and bit[30:26]) controls the de-emphasis base level. The settings and the corresponding values of the de-emphasis level, which can be globally via EEPROM or SMBUS settings. Table 5-7 Drive De-Emphasis Base Level Register Re giste r C_EMP_POST _GEN1_3P5_NOM C_EMP_POST _GEN2_3P5_NOM C_EMP_POST _GEN2_6P0_NOM De -Emphasis Condition -3.5 db -3.5 db -6.0 db Table 5-8 Drive De-Emphasis Base Level Settings Se tting De -Emphasis (mV pd) 0.0 6.0 12.5 19.0 25.0 31.0 37.5 44.0 50.0 56.0 62.5 Se tting De -Emphasis (mV pd) 69.0 75.0 81.0 87.0 94.0 100.0 106.0 112.5 119.0 125.0 131.0 Se tting De -Emphasis (mV pd) 137.5 144.0 150.0 156.0 162.5 169.0 175.0 181.0 187.5 194.0 - 00000 01011 10110 00001 01100 10111 00010 01101 11000 00011 01110 11001 00100 01111 11010 00101 10000 11011 00110 10001 11100 00111 10010 11101 01000 10011 11110 01001 10100 11111 01010 10101 Note : 1. Nominal levels. Actual levels will vary with temperature, voltage and board effects. 2. T he maximum nominal amplitude of the output driver is 475 mV pd. Combined values of driver amplitude and de-emphasis greater than 475 mV pd should be avoided. 3. At higher amplitudes, actual swings will be less than the theoretical value due to process variations and environment factors, such as voltage overhead compression, package losses, board losses, and other effects. 5.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY After the last character of the PCI Express transmission, the output current is reduced, and a differential voltage of less than 20 mV with co mmon mode of VTX-CM -DC is established within 20 UI. This delay time is programmab le via Transmitter PHY Latency field in the PHY Parameter 2 Register (Offset 7Ch, bit[3:0]), wh ich can be configured by EEPROM or SMBUS settings. 5.2 DATA LINK LAYER (DLL) The Data Link Layer (DLL) provides a reliab le data transmission between two PCI Express points. An ACK/NA CK protocol is emp loyed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calcu lation to determine if the incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter wou ld issue a NACK data lin k layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an A CK DLLP would be sent out to acknowledge on reception of a good TLP. In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NA CK DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller than that carried in the ACK wou ld be flushed out from the buffer. If a NA CK is received or no ACK/NA CK is returned fro m the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is triggered to re-t ransmit the corresponding packet that receives NACK or time-out and any other TLP t ransmitted after that packet. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 21 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL Meanwhile, the DLL is also responsible for the initialization, updating, and mon itoring o f the flow-control cred it. A ll of the flo w control informat ion is carried by DLLP to the other end o f the link. Unlike TLP, DLLP is guarded by 16-bit CRC to detect if data corruption occurs. In addition, the Media Access Control (MAC) block, wh ich is consisted of LTSSM , mult iple lanes de-skew, scrambler/de-scramb ler, clock correct ion fro m inserting skip order-set, and PIPE-related control/status circuits, is implemented to interface physical layer with data link layer. 5.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) The receiving end of the transaction layer performs header info rmation retrieval and TC/ VC mapp ing (see section 5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain an illegal header or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the TLP at the receiver if the digest bit is set in header. 5.4 ROUTING The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing. For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are routed by their destination ID constituted of bus number, device nu mber, and function number. Address routing is emp loyed to forward I/O or memory transactions to the destination port, which is located within the address range indicated by the address field carried in the packet header. The packet header indicates the packet types including memory read, memo ry write, IO read, IO write, Message Signaling Interrupt (M SI) and user-defined message. Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power management, and so on. The message type embedded in the packet header determines the routing mechanism. If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI protocol. 5.5 TC/VC MAPPING The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the differential service, a TC/ VC mapping table at destination port that is pre-programmed by system software or EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that TC0 t raffic is mapped into VC0 channel by default. After the TC/ VC mapping, the receive block d ispatches the incoming request, comp letion, o r data into the appropriate VC0 and VC1 queues. 5.6 QUEUE In PCI Exp ress, it defines six different packet types to represent request, completion, and data. They are respectively Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted Data Payload (NPD), Co mpletion Header (CPLH) and Co mp letion Data payload (CPLD). Each packet with different type would be put into a separate queue in order to facilitate the fo llo wing ordering processor. Since NPD usually contains one DW, it can be merged with the corresponding NPH into a co mmon queue named NPHD. Except NPHD, each virtual channel (VC0 or VC1) has its own corresponding packet header and data queue. When only VC0 is needed in some applications, VC1 can be disabled and its resources assigned to VC0 by asserting VC1_EN (Virtual Channel 1 Enable) to low. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 22 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 5.6.1 PH PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header space occupies sixteen bytes to accommodate 3 DW o r 4 DW headers. There are two PH queues for VC0 and VC1 respectively. 5.6.2 PD PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined to have payload coming with the header, the payload data would be put into PD queue. There are two PD queues for VC0 and VC1 respectively. 5.6.3 NPHD NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data. There is only one NPHD queue for VC0, since non-posted request cannot be mapped into VC1. 5.6.4 CPLH CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to accommodate a 3-DW header. Please note that there are no 4-DW comp letion headers. There are two CPLH queues for VC0 and VC1 respectively. 5.6.5 CPLD CPLD queue is used for storing complet ion data. If the received TLP is of the complet ion type and is determined to have payload coming with the header, the payload data would be put into CPLD queue. There are two CPLD queues for VC0 and VC1 respectively. 5.7 TRANSACTION ORDERING Within a VPPB, a set of o rdering rules is defined to regulate the transactions on the PCI Express Switch including Memory, IO, Configurat ion and Messages, in order to avoid deadlocks and to support the Producer-Consumer model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering requirement among transactions within different TC labels. Since the transactions with the same TC label are not allowed to map into different virtual channels, it implies no ordering relationship between the traffic in VC0 and VC1. Table 5-9 Summary of PCI Express Ordering Rules Row Pass Column Posted Request Read Request Non-posted Write Request Read Completion Non-Posted Write Completion PI7C9X2G404SL Document Number DS40068 Rev 2-2 Posted Re quest Yes/No 1 No 2 No 2 Yes/No 3 Yes4 Re ad Re quest Yes5 Yes Yes Yes Yes Non-posted Write Re quest Yes5 Yes Yes Yes Yes Page 23 of 90 www.diodes.com Re ad Completion Yes5 Yes Yes Yes Yes Non-posted Write Completion Yes5 Yes Yes Yes Yes September 2017 © Diodes Incorporated PI7C9X2G404SL 1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and message request must complete on the egress bus of VPPB in the order in which they are received on the ingress bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted Requests occurring before it. 2. A Read Request transmitting in the same d irection as a previously queued Posted Request transaction must push the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data. Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data. 3. When the Relaxed Ordering Attribute bit is cleared, a Read co mpletion must ‘‘pull’’ ahead of previously queued posted data transmitting in the same d irect ion. In this case, the read data transmits in the same d irection as the posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If the Relaxed Ordering Attribute bit is set, then a read co mplet ion is permitted to pass a previously queued Memory Write or Message Request. 4. Non-Posted Write Co mplet ions are permitted to pass a previous Memory Write or Message Request transaction. Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship. 5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as Co mplet ions. Otherwise, deadlocks may occur when some older bridges, which do not support delayed transactions are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write queue and the Non-posted transaction queue 5.8 PORT ARBITRATION Among mult iple ingress ports, the port arbitration built in the egress port determines which inco ming packets to be forwarded to the output port. The arbitration algorith m contains hardware fixed Round Robin, 128-phase Weighted Round-Robin and programmab le 128-phase time-based WRR. The port arb itration is held within the same VC channel. It means that each port has two port arbitration circuitries for VC0 and VC1 respectively. At the upstream ports, in addition to the inter-port packets, the intra-port packet such as configurations completion would also jo in the arbitration loop to get the service from Virtual Channel 0. 5.9 VC ARBITRATION After port arb itration, VC arbit ration is executed among different VC channels within the same source. Three arbitration algorith ms are provided to choose the appropriate VC: Strict Priority, Round Robin o r Weighted Round Robin. 5.10 FLOW CONTROL PCI Express employs Credit-Based Flo w Control mechanis m to make buffer utilization more efficient. The transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free buffer space to an opposite transmitter to avoid packet stale. In this Switch, each port has its own separate queues for different traffic types and the credits are sent to data link layer on the fly. The data lin k layer co mpares the current available credits with the monitored ones and reports the updated credit to the counterpart. If no new credit is acquired, the credit reported is scheduled for every 30 us to prevent the lin k fro m entering retrain. On the other hand, the receiver at each egress port gets the usable credits fro m the opposite end in a link. The output port broadcasts them to all the other ingress ports to get packet transmission. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 24 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 5.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) The transmit portion of transaction layer performs the following functions. They construct the all types of forwarded TLP generated fro m VC arbiter, respond with the co mp letion packets when the local resource (i.e. configuration register) is accessed, and regenerate the message that terminates at receiver to RC if acting as an upstream port. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 25 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bi-d irectional serial data). The Switch may control an ISSI IS24C04 o r co mpatib le parts using into 512x8 bits. The EEPROM is used to init ialize a nu mber of reg isters before enumerat ion. Th is is acco mplished after PRST# is de-asserted, at which time the data fro m the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address input. It can only access the EEPROM with address input set to 0. The System Management Bus interface consists of two pins: SM BCLK (System Management Bus Clock input) and SMBDATA (System Management Bus Data input/ output). 6.1 EEPROM INTERFACE 6.1.1 AUTO MODE EERPOM ACCESS The Switch may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer. The EEPROM start-control, address, and read/write commands can be accessed through the configuration register. Before each access, the software should check the Autoload Status bit before issuing the next start. 6.1.2 EEPROM MODE AT RESET During a reset, the Switch will automat ically load the information/data fro m the EEPROM if the auto matic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload initiates right after the reset. During the autoload, the Bridge will read sequential wo rds from the EEPROM and write to the appropriate registers. Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading b it [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0' which indicates that the autoload initialization sequence is complete. 6.1.3 EEPROM SPACE ADDRESS MAP 15 – 8 7–0 EEPROM Signature (1516h) Vendor ID Device ID Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port 1 ~ 3 Subsystem Vender ID Subsystem ID Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting Global PHY T X Margin Parameter for Port 0~3 Global PHY Parameter 0 for Port 0~3 Global XPIP_CSR6[0] / Global PHY Parameter 1 for Port 0~3 Global XPIP_CSR6[4:1] / Global PHY Parameter 2/3 for Port 0~3 Global XPIP_CSR4[15:0] for Port 0~3 Global XPIP_CSR4[31:16] for Port 0~3 Global XPIP_CSR5[15:0] for Port 0~3 Buffer_ctrl[4:0] / Global XPIP_CSR5[23:16] for Port 0~3 Global XPIP_CSR6[7:5] for Port 0~3 MAC_CT R / Global PHY Parameter 3 for Port 0~3 NFT S / Scramble / XPIP_CSR2 / Deskew mode select for Port 0 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 26 of 90 www.diodes.com BYTE O FFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h September 2017 © Diodes Incorporated PI7C9X2G404SL 15 – 8 7–0 NFT S / Scramble / XPIP_CSR2 / Deskew mode select for Port 1 NFT S / Scramble / XPIP_XSR2 / Deskew mode select for Port 2 NFT S / Scramble / XPIP_CSR2 / Deskew mode select for Port 3 Reserved Reserved Reserved Reserved PHY Parameter2_1 for Port 0 PHY Parameter2_1 for Port 1 PHY Parameter2_1 for Port 2 PHY Parameter2_1 for Port 3 Reserved Reserved Reserved Reserved Do_change_rate_cnt/ PHY Parameter 3/ PHY Parameter2_2 for Port 0 XPIP_CSR_2 for Port 0 Sel_deemp/ PHY Parameter 3/ PHY Parameter2_2 for Port 1 Do_change_rate_cnt/ XPIP_CSR_2 for Port 1 Sel_deemp/ PHY Parameter 3/ PHY Parameter2_2 for Port 2 Do_change_rate_cnt/ XPIP_CSR_2 for Port 2 Sel_deemp/ PHY Parameter 3/ PHY Parameter2_2 for Port 3 Do_change_rate_cnt/ XPIP_XSR_2 for Port 3 Reserved Reserved Reserved Reserved PM Data for Port 0 PM Capability for Port 0 PM Data for Port 1 PM Capability for Port 1 PM Data for Port 2 PM Capability for Port 2 PM Data for Port 3 PM Capability for Port 3 Reserved Reserved Reserved Reserved T C/VC Map for Port 0 (VC0) Slot Clock / LPVC Count / Port Num, Port 0 T C/VC Map for Port 1 (VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 1 T C/VC Map for Port 2 (VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 2 T C/VC Map for Port 3 (VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 3 Reserved Reserved Reserved Reserved Power Budgeting Capability Register for Port 0 Power Budgeting Capability Register for Port 1 Power Budgeting Capability Register for Port 2 Power Budgeting Capability Register for Port 3 Reserved Reserved Reserved Reserved XPIP_CSR5[30:24] for Port 0 PM Control Para/Rx Polarity for Port 0 XPIP_CSR5[30:24] for Port 1 PM Control Para/Rx Polarity for Port 1 XPIP_CSR5[30:24] for Port 2 PM Control Para/Rx Polarity for Port 2 XPIP_CSR5[30:24] for Port 3 PM Control Para/Rx Polarity for Port 3 Reserved Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 27 of 90 www.diodes.com BYTE O FFSET 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h September 2017 © Diodes Incorporated PI7C9X2G404SL 15 – 8 Reserved Reserved Reserved 7–0 Reserved Reserved Reserved Reserved Slot Capability 0 for Port 1 Slot Capability 0 for Port 2 Slot Capability 0 for Port 3 Reserved Reserved Reserved Reserved Reserved Slot Capability 1 for Port 1 Slot Capability 1 for Port 2 Slot Capability 1 for Port 3 Reserved Reserved Reserved Reserved XPIP_CSR3[15:0] for Port 0 XPIP_CSR3[15:0] for Port 1 XPIP_CSR3[15:0] for Port 2 XPIP_CSR3[15:0] for Port 3 Reserved Reserved Reserved Reserved XPIP_CSR3[16:31] for Port 0 XPIP_CSR3[16:31] for Port 1 XPIP_CSR3[16:31] for Port 2 XPIP_CSR3[16:31] for Port 3 Reserved Reserved Reserved Reserved REV_T S_CT R/Replay T ime-out Counter for Port 0 REV_T S_CT R /Replay T ime-out Counter for Port 1 REV_T S_CT R /Replay T ime-out Counter for Port 2 REV_T S_CT R /Replay T ime-out Counter for Port 3 Reserved Reserved Reserved Reserved Acknowledge Latency T imer for Port 0 Acknowledge Latency T imer for Port 1 Acknowledge Latency T imer for Port 2 Acknowledge Latency T imer for Port 3 Reserved Reserved Reserved Reserved T C/VC Map for Port 0 (VC1) Maximum T ime Slot T C/VC Map for Port 1 (VC1) Maximum T ime Slot T C/VC Map for Port 2 (VC1) Maximum T ime Slot T C/VC Map for Port 3 (VC1) Maximum T ime Slot Reserved Reserved Reserved Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 28 of 90 www.diodes.com for for for for Port Port Port Port 0 0 0 0 BYTE O FFSET 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h Bah BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh D0h D2h D4h D6h D8h DAh DCh DEh E0h E2h E4h E6h E8h EAh ECh EEh F0h F2h F4h F6h F8h FAh FCh FEh September 2017 © Diodes Incorporated PI7C9X2G404SL 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ADDRESS 00h 02h 04h 06h 08h 0Ah 0Ch PI7C9X2G404SL PCI CFG O FFSET DESCRIPTIO N 00h ~ 01h 02h ~ 03h 144h (Port 0~2) 144h: Bit [0] EEPRO M signature – 1516h Ve ndor ID De vice ID Exte nded VC Count for Port 0~2  Bit [0]: It represents the supported VC count other than the default VC CCh (Port 0~2) CCh: Bit [14:12] CCh: Bit [17:15] Link Capability for Port 0~2  Bit [3:1]: It represents L0s Exit Latency for all ports  Bit [6:4]: It represents L1 Exit Latency for all ports 74h (Port 0~2) 74h: Bit [5] 74h: Bit [6] 74h: Bit [0] 74h: Bit [2:1] 74h: Bit [3] 74h: Bit [4] Switch Mode Operation for Port 0  Bit [8]: no ordering on packets for different egress port mode  Bit [9]: no ordering on different tag of completion mode  Bit [10]: Store and Forward  Bit [12:11]: Cut-through Threshold  Bit [13] : Port arbitrator Mode  Bit [14]: Credit Update Mode 3Ch (Port 1~2) 3Ch: Bit [8] B4h ~ B5h B6h ~ B7h C4h (Port 0~2) C4h: Bit [1:0] Inte rrupt pin for Port 1~2  Bit [15]: Set when INTA is requested for interrupt resource Subsystem Vender ID Subsystem ID Max_Payload_Size Support for Port 0~2  Bit [1:0]: Indicated the maximum payload size that the device can support for the T LP CCh (Port 0~2) CCh: Bit [11:10] ASPM Support for Port 0~2  Bit [3:2] : Indicate the level of ASPM supported on the PCIe link C4h (Port 0~2) C4h: Bit [15] Role _Base Error Re porting for Port 0~2  Bit [4] : Indicate implement the role-base error reporting 70h (Port 0~2) 70h: Bit [14] MSI Capability Disable for Port 0~2  Bit [5] : Disable MSI capability 74h (Port 0~2) 74h: Bit [15] Compliance Pattern Parity Control Disable for Port 0~2  Bit [6] : Disable compliance pattern parity 70h (Port 0~2) 70h: Bit [13] Powe r Management Capability Disable for Port 0~2  Bit [7] : Disable Power Management Capability 8Ch (Port 0~2) 8Ch: Bit [5] O RDER RULE5 Enable for port 0~2  Bit [8]: Capability for Post packet Pass Non-Post packet CCh (Port 1~2) CCh: Bit [21] Link Bandwidth Notification Capability for port 1~2  Bit [9]: Link Bandwidth Notification Capability 8Ch (Port 0~2) 8Ch: Bit [6] O rde ring Frozen for Port 0~2  Bit [10]: Freeze the ordering feature 8Ch (Port 0~2) 8Ch: Bit [0] TX SO F Latency Mode for Port 0~2  Bit [11]: Set to zero to shorten latency CCh (Port 0~2) CCh: Bit [19] Surprise Down Capability Enable for Port 0~2  Bit [12]: Enable Surprise Down Capability 8Ch (Port 0~2) 8Ch: Bit [1] E4h (Port 0~2) E4h: Bit [12] Powe r Management’s Data Select Register R/W Capability for Port 0~2  Bit [13]: Enable Data Select Register R/W LTR Capability Enable for Port 0~2  Bit [14]: LTR capability enable 8Ch (Port 0~2) 8Ch: Bit [3] 4KB Boundary Check Enable for Port 0~2  Bit [15]: Enable 4KB Boundary Check Document Number DS40068 Rev 2-2 Page 29 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 0Eh 10h 12h 14h 16h 18h 1A 1C 1E 20h PI7C9X2G404SL PCI CFG O FFSET 94h (Port 0~2) 94h: Bit [4:0] 94h: Bit [9:5] 94h: Bit [14:10] DESCRIPTIO N E4h (Port 0~2) E4h: Bit [18] 74h (Port 0~2) 74h: Bit [20:16] 74h: Bit [25:21] 74h: Bit [30:26] O BFF Capability Enable for Port 0~2  Bit [15] : enable OBFF capability PHY Parameter 0 for Port 0~2  Bit [4:0]: C_DRV_LVL_3P5_NOM  Bit [9:5]: C_DRV_LVL_6P0_NOM  Bit [14:10]: C_DRV_LVL_HALF_NOM 8Ch (Port 0~2) 8Ch: Bit [31] 78h (Port 0~2) 78h: Bit [20:16] 78h: Bit [25:21] 78h: Bit [30:26] TL_CSR[31] for Port 0~2  Bit [15] : P35_GEN2_MODE PHY Parameter 1 for Port 0~2  Bit [4:0]: C_EMP_POST _GEN1_3P5_NOM  Bit [9:5]: C_EMP_POST _GEN2_3P5_NOM  Bit [14:10]: C_EMP_POST _GEN2_6P0_NOM 8Ch (Port 0~2) 8Ch: Bit [16] 7Ch (Port 0~2) 7Ch: Bit [3:0] 7Ch: Bit [6:4] XPIP_CSR6[0] for Port 0~2  Bit [15]: XPIP_CSR6[0] PHY Parameter 2 for Port 0~2  Bit [3:0]: C_TX_PHY_LATENCY  Bit [6:4]: C_REC_DETECT_USEC 90h (Port 0~2) 90h: Bit [19:15] PHY Parameter 3 for Port 0~2  Bit [11:7]: C_EMP_POST_HALF_DELTA 8Ch (Port 0~2) 8Ch: Bit [20:17] 84h (Port 0~2) 84h: Bit [15:0] 84h (Port 0~2) 84h: Bit [31:16] 88h (Port 0~2) 88h: Bit [15:0] 88h (Port 0~2) 88h: Bit [23:16] XPIP_CSR6[4:1] for Port 0~2  Bit [15:12]: XPIP_CSR6[4:1] XPIP_CSR4[15:0] for Port 0~2  Bit [15:0]: XPIP_CSR4[15:0] XPIP_CSR4[31:16] for Port 0~2  Bit [15:0]: XPIP_CSR4[31:16] XPIP_CSR5[15:0] for Port 0~2 Bit [15:0]: XPIP_CSR5[15:0] XPIP_CSR5[28:16] for Port 0~2  Bit [7:0]: XPIP_CSR5[23:16] 8Ch (Port 0~2) 8Ch: Bit [23:21] XPIP_CSR6[7:5] for Port 0~2  Bit [10:8]: XPIP_CSR6[7:5] 98h (Port 0~2) 98h: Bit [20:16] 90h (Port 0~2) 90h: Bit [21:20] 90h: Bit [23:22] 90h: Bit [25:24] 90h: Bit [27:26] 90h: Bit [29:28] 90h: Bit [31:30] BUFFER_CTRL[4:0] for Port 0~2  Bit [15:11]: Reference clock Buffer control PHY parameter 3 for Port 0~2  Bit [1:0]: C_DRV_LVL_3P5_DELTA  Bit [3:2]: C_DRV_LVL_6P0_DELTA  Bit [5:4]: C_DRV_LVL_HALF_DELTA  Bit [7:6]: C_EMP_POST _GEN1_3P5_DELTA  Bit [9:8]: C_EMP_POST _GEN2_3P5_DELTA  Bit [11:10]: C_EMP_POST _GEN2_6P0_DELTA 8Ch (Port 0~2) 8Ch: Bit [29:26] 78h (Port 0) 78h: Bit [7 :0] MAC control parameter for Port 0~2  Bit [15:12]: MAC_CTR FTS Number for Port 0  Bit [7:0]: FTS number at receiver side 68h (Port 0) 68h: Bit [14:13] De skew Mode Select for Port 0  Bit [9:8]: deskew mode select 78h (Port 0) 78h: Bit [9:8] 78h: Bit [10] Scrambler Control for Port 0  Bit [11:10]: scrambler control  Bit [12]: L0s 78h (Port 0) 78h: Bit [13:12] Change_Speed_Sel for Port 0  Bit [14:13]: Change Speed select Document Number DS40068 Rev 2-2 PHY TX Margin Parameter for Port 0~2  Bit [4:0]: C_DRV_LVL_3P5_MGN2  Bit [9:5]: C_DRV_LVL_6P0_MGN2  Bit [14:10]: C_DRV_LVL_HALF_MGN2 Page 30 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 22h 24h 26h 30h 32h 34h 36h 40h PI7C9X2G404SL PCI CFG O FFSET 78h (Port 0) 78h: Bit [14] 78h (Port 1) 78h: Bit [7 :0] DESCRIPTIO N 68h (Port 1) 68h: Bit [14:13] De skew Mode Select for Port 01Bit [9:8]: deskew mode select 78h (Port 1) 78h: Bit [9:8] 78h: Bit [10] Scrambler Control for Port 1  Bit [11:10]: scrambler control  Bit [12]: L0s 78h (Port 1) 78h: Bit [13:12] Change_Speed_Sel for Port 1  Bit[ 14:13]: Change Speed select 78h (Port 1) 78h: Bit [14] 78h (Port 2) 78h: Bit [7 :0] Change_Speed_En for Port 1  Bit [15]: Change Speed enable FTS Number for Port 2  Bit [7:0]: FTS number at receiver side 68h (Port 2) 68h: Bit [14:13] De skew Mode Select for Port 2  Bit [9:8]: deskew mode select 78h (Port 2) 78h: Bit [9:8] 78h: Bit [10] Scrambler Control for Port 2  Bit [11:10]: scrambler control  Bit [12]: L0s 78h (Port 2) 78h: Bit [13:12] Change_Speed_Sel for Port 2  Bit [14:13]: Change Speed select 78h (Port 2) 78h: Bit [14] 78h (Port 3) 78h: Bit [7 :0] Change_Speed_En for Port 2  Bit [15]: Change Speed enable FTS Number for Port 3  Bit [7:0]: FTS number at receiver side 68h (Port 3) 68h: Bit [14:13] De skew Mode Select for Port 3  Bit [9:8]: deskew mode select 78h (Port 3) 78h: Bit [9:8] 78h: Bit [10] Scrambler Control for Port 3  Bit [11:10]: scrambler control  Bit [12]: L0s 78h (Port 3) 78h: Bit [13:12] Change_Speed_Sel for Port 3  Bit [14:13]: Change Speed select 78h (Port 3) 78h: Bit [14] 7Ch (Port 0) 7Ch: Bit [30 :16] 7Ch (Port 1) 7Ch: Bit [30 :16] 7Ch (Port 2) 7Ch: Bit [30 :16] 7Ch (Port 3) 7Ch: Bit [30 :16] 7Ch (Port 0) 7Ch: Bit [12 :8] Change_Speed_En for Port 3  Bit [15]: Change Speed enable PHY Parameter2_1 for Port 0  Bit [14:0]: PHY parameter 2 PHY Parameter2_1 for Port 1  Bit [14:0]: PHY parameter 2 PHY Parameter2_1 for Port 2  Bit [14:0]: PHY parameter 2 PHY Parameter2_1 for Port 3  Bit [14:0]: PHY parameter 2 PHY Parameter 2_1 for Port 0  Bit [4:0]: PHY parameter 2 90h (Port 0) 90h: Bit [6 :0] PHY Parameter 3 for Port 0  Bit [11:5]: PHY parameter 3 F0h (Port 0) F0h: Bit [6] Se lectable De-emphasis for Port 0  Bit [12]: Selectable De-emphasis 78h (Port 0) 78h: Bit [11] Compliance to Detect for Port 0  Bit [13]: compliance to detect Document Number DS40068 Rev 2-2 Change_Speed_En for Port 0  Bit [15]: Change Speed enable FTS Number for Port 1  Bit [7:0]: FTS number at receiver side Page 31 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 42h 44h 46h 50h PCI CFG O FFSET 8Ch (Port 0) 8Ch: Bit [9:8] 7Ch (Port 1) 7Ch: Bit [12 :8] 90h (Port 1) 90h: Bit [6 :0] DO _CHG_DATA_CNT_SEL for Port 0  Bit [15:14] : DO_CHG_DATA_CNT_SEL PHY Parameter 2_1 for Port 1  Bit [4:0]: PHY parameter 2 PHY Parameter 3 for Port 1  Bit [11:5]: PHY parameter 3 F0h (Port 0) F0h: Bit [6] Se lectable De-emphasis for Port 1  Bit [12]: Selectable De-emphasis 78h (Port 1) 78h: Bit [11] Compliance to Detect for Port 1  Bit [13]: compliance to detect 8Ch (Port 1) 8Ch: Bit [9:8] 7Ch (Port 2) 7Ch: Bit [12 :8] DO _CHG_DATA_CNT_SEL for Port 1  Bit [15:14] : DO_CHG_DATA_CNT_SEL PHY Parameter 2_1 for Port 2  Bit [4:0]: PHY parameter 2 90h (Port 2) 90h: Bit [6 :0] PHY Parameter 3 for Port 2  Bit [11:5]: PHY parameter 3 F0h (Port 2) F0h: Bit [6] Se lectable De-emphasis for Port 2  Bit [12]: Selectable De-emphasis 78h (Port 2) 78h: Bit [11] Compliance to Detect for Port 2  Bit [13]: compliance to detect 8Ch (Port 2) 8Ch: Bit [9:8] 7Ch (Port 3) 7Ch: Bit [12 :8] DO _CHG_DATA_CNT_SEL for Port 2  Bit [15:14] : DO_CHG_DATA_CNT_SEL PHY Parameter 2_1 for Port 3  Bit [4:0]: PHY parameter 2 90h (Port 3) 90h: Bit [6 :0] PHY Parameter 3 for Port 3  Bit [11:5]: PHY parameter 3 F0h (Port 3) F0h: Bit [6] Se lectable De-emphasis for Port 3  Bit [12]: Selectable De-emphasis 78h (Port 3) 78h: Bit [11] Compliance to Detect for Port 3  Bit [13]: compliance to detect 8Ch (Port 3) 8Ch: Bit [9:8] 44h (Port 0) 44h: Bit [3] DO _CHG_DATA_CNT_SEL for Port 3  Bit [15:14] : DO_CHG_DATA_CNT_SEL No_Soft_Reset for Port 0  Bit [0]: No_Soft_Reset. 40h (Port 0) 40h: Bit [24:22] 40h: Bit [25] Powe r Management Capability for Port 0  Bit [3:1]: AUX Current.  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Powe r Management Data for Port 0  Bit [15:8]: read only as Data register No_Soft_Reset for Port 1  Bit [0]: No_Soft_Reset. 40h: Bit [26] 51h 52h 40h: Bit [29:28] 44h (Port 0) 44h: Bit [31:24] 44h (Port 1) 44h: Bit [3] 40h (Port 1) 40h: Bit [24:22] 40h: Bit [25] 40h: Bit [26] 53h PI7C9X2G404SL 40h: Bit [29:28] 44h (Port 1) 44h: Bit [31:24] Document Number DS40068 Rev 2-2 DESCRIPTIO N Powe r Management Capability for Port 1  Bit [3:1]: AUX Current.  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Powe r Management Data for Port 1  Bit [15:8]: read only as Data register Page 32 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 54h PCI CFG O FFSET 44h (Port 2) 44h: Bit [3] DESCRIPTIO N 40h (Port 2) 40h: Bit [24:22] 40h: Bit [25] Powe r Management Capability for Port 2  Bit [3:1]: AUX Current  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Powe r Management Data for Port 2  Bit [15:8]: read only as Data register No_Soft_Reset for Port 3  Bit [0]: No_Soft_Reset 40h: Bit [26] 55h 56h 40h: Bit [29:28] 44h (Port 2) 44h: Bit [31:24] 44h (Port 3) 44h: Bit [3] 40h (Port 3) 40h: Bit [24:22] 40h: Bit [25] 40h: Bit [26] 57h 60h 40h: Bit [29:28] 44h (Port 3) 44h: Bit [31:24] D0h (Port 0) D0h: Bit [28] De vice specific Initialization for Port 0  Bit [2]: When set, the DSI is required 144h (Port 0) 144h: Bit [4] LPVC Count for Port 0  Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 0 CCh (Port 0) CCh: Bit [26:24] Port Number for Port 0  Bit [6:4]: It represents the logic port numbering for physical port 0 VC0 TC/VC Map for Port 0  Bit [15:9]: When set, it indicates the corresponding T C is mapped into VC0 PCIe Capability Slot Implemented for Port 1  Bit [0]: When set, the slot is implemented for Port 1 C0h (Port 1) C0h: Bit [24] D0h (Port 1) D0h: Bit [28] Slot Clock Configuration for Port 1  Bit [1]: When set, the component uses the clock provided on the Connector 40h (Port 1) 40h: Bit [21] De vice specific Initialization for Port 1  Bit [2]: When set, the DSI is required 144h (Port 1) 144h: Bit [4] LPVC Count for Port 1  Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 1 CCh (Port 1) CCh: Bit [26:24] Port Number for Port 1  Bit [6:4]: It represents the logic port numbering for physical port 1 VC0 TC/VC Map for Port 1  Bit [15:9]: When set, it indicates the corresponding T C is mapped into VC0 154h (Port 1) 154h: Bit [7:1] PI7C9X2G404SL Powe r Management Capability for Port 3  Bit [3:1]: AUX Current  Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state  Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state  Bit [7:6]: PME Support for D2 and D1 states Powe r Management Data for Port 3  Bit [15:8]: read only as Data register Slot Clock Configuration for Port 0  Bit [1]: When set, the component uses the clock provided on the connector 40h (Port 0) 40h: Bit[21] 154h (Port 0) 154h: Bit [7:1] 62h No_Soft_Reset for Port 2  Bit [0]: No_Soft_Reset Document Number DS40068 Rev 2-2 Page 33 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 64h PCI CFG O FFSET C0h (Port 2) C0h: Bit [24] DESCRIPTIO N D0h (Port 2) D0h: Bit [28] Slot Clock Configuration for Port 2  Bit [1]: When set, the component uses the clock provided on the Connector 40h (Port 2) 40h: Bit [21] De vice specific Initialization for Port 2  Bit [2]: When set, the DSI is required 144h (Port 2) 144h: Bit [4] LPVC Count for Port 2  Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2 CCh (Port 2) CCh: Bit [26:24] Port Number for Port 2  Bit [6:4]: It represents the logic port numbering for physical port 2 VC0 TC/VC Map for Port 2  Bit [15:9]: When set, it indicates the corresponding T C is mapped into VC0 PCIe Capability Slot Implemented for Port 3  Bit [0]: When set, the slot is implemented for Port 2 154h (Port 2) 154h: Bit [7:1] 66h C0h (Port 3) C0h: Bit [24] D0h (Port 3) D0h: Bit [28] Slot Clock Configuration for Port 3  Bit [1]: When set, the component uses the clock provided on the Connector 40h (Port 3) 40h: Bit [21] De vice specific Initialization for Port 3  Bit [2]: When set, the DSI is required 144h (Port 3) 144h: Bit [4] LPVC Count for Port 3  Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2 CCh (Port 3) CCh: Bit [26:24] Port Number for Port 3  Bit [6:4]: It represents the logic port numbering for physical port 2 VC0 TC/VC Map for Port 2  Bit [15:9]: When set, it indicates the corresponding T C is mapped into VC0 Powe r Budget Register for Port 0  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Powe r Budget Register for Port 1  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Powe r Budget Register for Port 2  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated Powe r Budget Register for Port 3  Bit [7:0]: Base Power  Bit [9:8]: Data Scale  Bit [11:10]: PM State  Bit [15]: System Allocated 154h (Port 3) 154h: Bit [7:1] 70h 72h 74h 76h PI7C9X2G404SL PCIe Capability Slot Implemented for Port 2  Bit [0]: When set, the slot is implemented for Port 2 214h (Port 0) 214h: Bit [7:0] 214h: Bit [9:8] 214h: Bit [14:13] 218h: Bit [0] 214h (Port 1) 214h: Bit [7:0] 214h: Bit [9:8] 214h: Bit [14:13] 218h: Bit [0] 214h (Port 2) 214h: Bit [7:0] 214h: Bit [9:8] 214h: Bit [14:13] 218h: Bit [0] 214h (Port 3) 214h: Bit [7:0] 214h: Bit [9:8] 214h: Bit [14:13] 218h: Bit [0] Document Number DS40068 Rev 2-2 Page 34 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS 80h 82h 84h 86h 92h 94h 96h A2h A4h A6h B0h B2h B4h B6h C0h PI7C9X2G404SL PCI CFG O FFSET 74h (Port 0) 74h: Bit [13:8] DESCRIPTIO N 74h: Bit [14] PM Control Parameter for Port 0  Bit [1:0] : D3 enters L1  Bit [3:2] : L1 delay count select Bit [5:4] : L0s enable  Bit [6] : Disable Rx polarity capability 70h (Port 0) 70h: Bit [31] VGA De code Enable for Port 0  Bit [7]: Enable VGA decode 88h (Port 0) 88h: Bit [31:24] 74h (Port 1) 74h: Bit [13:8] 74h: Bit [14] XPIP_CSR5[31:24] for Port 0 Bit[15:8]: XPIP_CSR5[31:24] PM Control Parameter for Port 1  Bit [1:0] : D3 enters L1  Bit [3:2] : L1 delay count select Bit [5:4] : L0s enable  Bit [6] : Disable Rx polarity capability 70h (Port 1) 70h: Bit [31] VGA De code Enable for Port 1  Bit [7]: Enable VGA decode 88h (Port 1) 88h: Bit [31:24] 74h (Port 2) 74h: Bit [13:8] 74h: Bit [14] XPIP_CSR5[31:24] for Port 1  Bit[15:8]: XPIP_CSR5[31:24] PM Control Parameter for Port 2  Bit [1:0] : D3 enters L1  Bit [3:2] : L1 delay count select Bit [5:4] : L0s enable  Bit [6] : Disable Rx polarity capability 70h (Port 2) 70h: Bit [31] VGA De code Enable for Port 2  Bit [7]: Enable VGA decode 88h (Port 2) 88h: Bit [31:24] 74h (Port 3) 74h: Bit [13:8] 74h: Bit [14] XPIP_CSR5[31:24] for Port 2  Bit[15:8]: XPIP_CSR5[31:24] PM Control Parameter for Port 3  Bit [1:0] : D3 enters L1  Bit [3:2] : L1 delay count select Bit [5:4] : L0s enable  Bit [6] : Disable Rx polarity capability 70h (Port 3) 70h: Bit [31] VGA De code Enable for Port 3  Bit [7]: Enable VGA decode 88h (Port 3) 88h: Bit [31:24] D4h (Port 1) D4h: Bit [15:0] D4h (Port 2) D4h: Bit [15:0] D4h (Port 3) D4h: Bit [15:0] D4h (Port 1) D4h: Bit [31:16] D4h (Port 2) D4h: Bit [31:16] D4h (Port 3) D4h: Bit [31:16] 80h (Port 0) 80h: Bit [15:0] 80h (Port 1) 80h: Bit [15:0] 80h (Port 2) 80h: Bit [15:0] 80h (Port 3) 80h: Bit [15:0] 80h (Port 0) 80h: Bit [31:16] XPIP_CSR5[31:24] for Port 3  Bit[15:8]: XPIP_CSR5[31:24] Slot Capability 0 of Port 1  Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 0 of Port 2  Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 0 of Port 3  Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 1 of Port 1  Bit [15:0]: Mapping to the high word of slot capability register Slot Capability 1 of Port 2  Bit [15:0]: Mapping to the high word of slot capability register Slot Capability 1 of Port 3  Bit [15:0]: Mapping to the high word of slot capability register XPIP_CSR3_0 for Port 0  Bit [15:0]: XPIP_CSR3[15:0] XPIP_CSR3_0 for Port 1  Bit [15:0]: XPIP_CSR3[15:0] XPIP_CSR3_0 for Port 2  Bit [15:0]: XPIP_CSR3[15:0] XPIP_CSR3_0 for Port 3  Bit [15:0]: XPIP_CSR3[15:0] XPIP_CSR3_1 for Port 0  Bit [15:0]: XPIP_CSR3[31:16] Document Number DS40068 Rev 2-2 Page 35 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL ADDRESS C2h C4h C6h D0h D2h D4h D6h E0h E2h E4h E6h F0h F2h PCI CFG O FFSET 80h (Port 1) 80h: Bit [31:16] 80h (Port 2) 80h: Bit [31:16] 80h (Port 3) 80h: Bit [31:16] 70h (Port 0) 70h: Bit [12:0] XPIP_CSR3_1 for Port 1  Bit [15:0]: XPIP_CSR3[31:16] XPIP_CSR3_1 for Port 2  Bit [15:0]: XPIP_CSR3[31:16] XPIP_CSR3_1 for Port 3  Bit [15:0]: XPIP_CSR3[31:16] Re play Time-out Counter for Port 0  Bit [12:0]: Relay T ime-out Counter 8Ch (Port 0) 8Ch: Bit [25:24] 70h (Port 1) 70h: Bit [12:0] REV_TS_CTR for Port 0  Bit [14:13] REV_T S_CTR Re play Time-out Counter for Port 1  Bit [12:0]: Relay T ime-out Counter 8Ch (Port 1) 8Ch: Bit [25:24] 70h (Port 2) 70h: Bit [12:0] REV_TS_CTR for Port 1  Bit [14:13] REV_T S_CTR Re play Time-out Counter for Port 2  Bit [12:0]: Relay T ime-out Counter 8Ch (Port 2) 8Ch: Bit [25:24] 70h (Port 3) 70h: Bit [12:0] REV_TS_CTR for Port 2  Bit [14:13] REV_T S_CTR Re play Time-out Counter for Port 3  Bit [12:0]: Relay T ime-out Counter 8Ch (Port 3) 8Ch: Bit [25:24] 70h (Port 0) 70h: Bit [30:16] 70h (Port 1) 70h: Bit [30:16] 70h (Port 2) 70h: Bit [30:16] 70h (Port 3) 70h: Bit [30:16] 15Ch (Port 0) 15Ch: Bit [22:16] REV_TS_CTR for Port 3  Bit [14:13] REV_T S_CTR Acknowledge Latency Timer for Port 0  Bit [30:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 1  Bit [30:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 2  Bit [30:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 3  Bit [30:16]: Acknowledge Latency Timer VC1 MAX Time Slot and TC/VC Map for Port 0  Bit [6:0]: T he maximum time slot supported by VC1 160h (Port 0) 160h: Bit [7:0] TC/VC Map for Port 0  Bit [15:8]: When set, it indicates the corresponding T C is mapped into VC1 VC1 MAX Time Slot and TC/VC Map for Port 1  Bit [6:0]: T he maximum time slot supported by VC1 15Ch (Port 1) 15Ch: Bit [22:16] 160h (Port 1) 160h: Bit [7:0] F4h 15Ch (Port 2) 15Ch: Bit [22:16] 160h (Port 2) 160h: Bit [7:0] F6h 15Ch (Port 3) 15Ch: Bit [22:16] 160h (Port 3) 160h: Bit [7:0] PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N TC/VC Map for Port 1  Bit [15:8]: When set, it indicates the corresponding T C is mapped into VC1 VC1 MAX Time Slot and TC/VC Map for Port 2  Bit [6:0]: T he maximum time slot supported by VC1 TC/VC Map for Port 2  Bit [15:8]: When set, it indicates the corresponding T C is mapped into VC1 VC1 MAX Time Slot and TC/VC Map for Port 3  Bit [6:0]: T he maximum time slot supported by VC1 TC/VC Map for Port 3  Bit [15:8]: When set, it indicates the corresponding T C is mapped into VC1 Page 36 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 6.2 SMBus INTERFACE The PI7C9X2G404SL p rovides the System Management Bus (SMBus), a two-wire interface through which a simp le device can co mmunicate with the rest of the system. The SM Bus interface on the PI7C9X2G404SL is a bi-d irectional slave interface. It can receive data fro m the SMBus master or send data to the master. The interface allows full access to the configuration registers. A SMBus master, such as the processor or other SMBus devices, can read or write to every RW configuration register (read/write register). In addition, the RO and HwInt registers (read-only and hardware in itialized registers) that can be auto-loaded by the EEPROM interface can also be read and written by the SMBus interface. This feature allows increases in the system expandability and flexibility in system implementation. Figure 6-1 SMBus Architecture Implementati on on PI7C9X2G404SL Processor (SMBus Master) PI7C9X2G404SL Other SMBus Devices SMBCLK SMBDATA The SM Bus interface on the PI7C9X2G404SL consists of one SMBus clock pin (SMBCLK), a SM Bus data pin (SM BDATA), and 3 SM Bus address pins (GPIO[5:7]). The SM Bus clock pin provides or receives the clock signal. The SM Bus data pin facilitates the data transmission and reception. Both of the clock and data pins are b i-directional. The SMBus address pins determine the address to which the PI7C9X2G404SL responds to. The SMBus address pins generate addresses according to the following table: Table 6-1 SMBus Address Pin Configuration BIT 0 1 2 3 4 5 6 PI7C9X2G404SL SMBus Address GPIO[5] GPIO[6] GPIO[7] 1 0 1 1 Document Number DS40068 Rev 2-2 Page 37 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7 REGISTER DESCRIPTION 7.1 REGISTER TYPES REGISTER TYPE HwInt RO RW RWC RWCS RWS ROS 7.2 DEFINITIO N Hardware Initialization Read Only Read / Write Read / Write 1 to Clear Sticky – Read Only / Write 1 to Clear Sticky – Read / Write Sticky – Read Only TRANSPARENT MODE CONFIGURATION REGISTERS When the port of the Switch is set to operate at the transparent mode, it is represented by a logical PCI-to-PCI Bridge that imp lements type 1 configuration space header. The following table details the allocation of the register fields of the PCI 2.3 compatible type 1 configuration space header. 31 –24 23 – 16 Device ID Primary Status Class Code Reserved Header T ype 15 – 8 Vendor ID Command 7 –0 Revision ID Primary Latency Timer Cache Line Size Reserved Secondary Latency Subordinate Bus Secondary Bus Primary Bus Number T imer Number Number Secondary Status I/O Limit Address I/O Base Address Memory Limit Address Memory Base Address Prefetchable Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Base Address Upper 32-bit Prefetchable Memory Limit Address Upper 32-bit I/O Limit Address Upper 16-bit I/O Base Address Upper 16-bit Reserved Capability Pointer to 80h(40h) Reserved Bridge Control Interrupt Pin Interrupt Line Power Management Capabilities Next Item Pointer=4C Capability ID=01 (5C) PM Data PPB Support Power Management Data Extensions Message Control Next Item Pointer=: Capability ID=05 64 Message Address Message Upper Address Reserved Message Data VPD Register Next Item Pointer=64 Capability ID=03 VPD Data Register Length in Bytes (34h) Next Item Pointer=B0 Capability ID=09 XPIP_CSR0 XPIP_CSR1 ACK Latency T imer Replay T ime-out Counter PHY Parameter 0 Switch Modes PHY Parameter 1 XPIP_CSR2 PHY Parameter 2 XPIP_CSR3 XPIP_CSR4 XPIP_CSR5 XPIP_CSR7 XPIP_CSR6 T L_CSR PHY parameter 3 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 38 of 90 www.diodes.com BYTE O FFSET 00h 04h 08h 0Ch 10h – 17h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h September 2017 © Diodes Incorporated PI7C9X2G404SL 31 –24 Reserved Reserved 23 – 16 PHYL1 RXEQ Buffer Ctrl Reserved 15 – 8 7 –0 PHY T X Margin parameter OP Mode Reserved Next Item Pointer=C0 SSID SSID/SSVID Capability ID=0D SSVID GPIO Data and Control EEPROM Data EEPROM Address EEPROM Control PCI Express Capabilities Register Next Item Pointer=00 Capability ID=10 Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status Slot Control Reserved Reserved Device Capabilities 2 Device Status / Control 2 Link Capabilities 2 Link Status /Control 2 Slot Capabilities 2 Slot Status /Control 2 Reserved BYTE O FFSET 94h 98h (9Ch – ACh) B0h B4h B8h BCh C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh Other than the PCI 2.3 co mpatible configuration space header, the Switch also imp lements PCI exp ress extended configuration space header, wh ich includes advanced error reporting, v irtual channel, and power budgeting capability registers. The follo wing table details the allocation of the register fields of PCI express extended capability space header. The first extended capability always begins at offset 100h with a PCI Exp ress Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginning of PCI co mpatib le configuration space. 31 –24 23 – 16 15 - 8 7 –0 Next Capability Offset=140h Cap. PCI Express Extended Capability ID=0001h Version Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register Reserved Next Capability Offset=20Ch Cap. PCI Express Extended Capability ID=0002h Version Port VC Capability Register 1 VC Arbitration T able Port VC Capability Register 2 Offset=3 Port VC Status Register Port VC Control Register Port Arbitration Table VC Resource Capability Register (0) Offset=4 VC Resource Control Register (0) VC Resource Status Register (0) Reserved Port Arbitration Table VC Resource Capability Register (1) Offset=6 VC Resource Control Register (1) VC Resource Status Register (1) Reserved Reserved VC Arbitration T able with 32 Phases Port Arbitration T able with 128 Phases for VC0 Port Arbitration T able with 128 Phases for VC1 Reserved Next Capability Offset=220/230h Cap. PCI Express Extended Capability ID=0004h Version PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 39 of 90 www.diodes.com BYTE O FFSET 100h 104h 108h 10Ch 110h 114h 118h 11Ch – 128h 12Ch – 13Fh 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 16Ch – 168h 170h – 17Ch 180h – 1BCh 1C0h – 1FCh 200h – 20Bh 20Ch September 2017 © Diodes Incorporated PI7C9X2G404SL 31 –24 23 – 16 Reserved Reserved 15 - 8 Data Register 7 –0 Data Select Register Power Budget Capability Register Reserved Next Capability Offset=000h Cap PCI Express Extended Capability ID=000Dh version ACS Control ACS Capability Reserved Egress Control Vector Reserved Next Capability Offset=000h Cap PCI Express Extended Capability ID=0018h version Reserved Max NoMax No-Snoop Reserved Max Max Snoop Latency Snoop Latency Value Snoop Value Latency Latency Scale Scale 7.2.1 BYTE O FFSET 210h 214h 218h 21Ch 220h 224h 228h 22Ch 230h 234h VENDOR ID REGISTER – OFFSET 00h BIT 15:0 FUNCTIO N Vendor ID TYPE RO DESCRIPTIO N Identifies Pericom as the vendor of this device. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 12D8h. 7.2.2 DEVICE ID REGISTER – OFFSET 00h BIT FUNCTIO N 31:16 Device ID TYPE RO DESCRIPTIO N Identifies this device as the PI7C9X2G303EL. The default value may be changed by SMBus or auto-loading from EEPROM. Resets to 2404h. 7.2.3 COMMAND REGISTER – OFFSET 04h BIT FUNCTIO N 0 I/O Space Enable TYPE RW Memory Space Enable RW 2 Bus Master Enable RW 3 Special Cycle Enable Memory Write And Invalidate Enable VGA Palette Snoop Enable RO 1 4 5 6 PI7C9X2G404SL Parity Error Response Enable Document Number DS40068 Rev 2-2 RO RO RW DESCRIPTIO N 0b: Ignores I/O transactions on the primary interface 1b: Enables responses to I/O transactions on the primary interface Resets to 0b. 0b: Ignores memory transactions on the primary interface 1b: Enables responses to memory transactions on the primary interface Reset to 0b. 0b: Does not initiate memory or I/O transactions on the upstream port and handles as an Unsupported Request (UR) to memory and I/O transactions on the downstream port. For Non-Posted Requests, a completion with UR completion status must be returned 1b: Enables the Switch Port to forward memory and I/O Read/Write transactions in the upstream direction Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. 0b: Switch may ignore any parity errors that it detects and continue normal operation 1b: Switch must take its normal action when a parity error is detected Page 40 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.4 BIT FUNCTIO N TYPE 7 Wait Cycle Control RO 8 SERR# enable RW 9 Fast Back-to-Back Enable RO 10 Interrupt Disable RW 15:11 Reserved DESCRIPTIO N Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0. 0b: Disables the reporting of Non-fatal and Fatal errors detected by the Switch to the Root Complex b1: Enables the Non-fatal and Fatal error reporting to Root Complex Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Controls the ability of a PCI Express device to generate INTx Interrupt Messages. In the Switch, this bit does not affect the forwarding of INTx messages from the downstream ports. RsvdP Reset to 0b. Not Support. PRIMARY STATUS REGISTER – OFFSET 04h BIT 18:16 FUNCTIO N Reserved 19 Interrupt Status RO 20 Capabilities List RO 21 22 66MHz Capable Reserved Fast Back-to-Back Capable 23 TYPE RsvdP RO RsvdP RO Master Data Parity Error RWC 26:25 DEVSEL# timing RO 27 Signaled T arget Abort RO Received T arget Abort RO Received Master Abort RO Signaled System Error RWC Detected Parity Error RWC 29 30 31 Reset to 1b. Does not apply to PCI Express. Must be hardwired to 0b. Not Support. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the primary side of the port in a Switch. 24 28 DESCRIPTIO N Not Support. Indicates that an INTx Interrupt Message is pending internally to the device. In the Switch, the forwarding of INTx messages from the downstream device of the Switch port is not reflected in this bit. Must be hardwired to 0b. Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure). If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request on the primary side using the Completer Abort Completion Status. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status on the primary side. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status on primary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Command register is 1. Reset to 0b. Set to 1 whenever the primary side of the port in a Switch receives a Poisoned T LP. Reset to 0b. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 41 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.5 REVISION ID REGISTER – OFFSET 08h BIT 7:0 7.2.6 TYPE RO DESCRIPTIO N Indicates revision number of device. Hardwired to 05h. CLASS CODE REGISTER – OFFSET 08h BIT 15:8 23:16 31:24 7.2.7 FUNCTIO N Revision FUNCTIO N Programming Interface Sub-Class Code Base Class Code TYPE RO RO RO DESCRIPTIO N Read as 00h to indicate no programming interfaces have been defined for PCI-to-PCI Bridges. Read as 04h to indicate device is a PCI-to-PCI Bridge. Read as 06h to indicate device is a Bridge device. CACHE LINE REGISTER – OFFSET 0Ch BIT FUNCTIO N 7:0 Cache Line Size TYPE RW DESCRIPTIO N T he cache line size register is set by the system firmware and the operating system cache line size. This field is implemented by PCI Express devices as a RW field for legacy compatibility, but it has no impact on any PCI Express device functionality. Reset to 00h. 7.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch BIT 15:8 7.2.9 7.2.10 FUNCTIO N Primary Latency timer TYPE RO DESCRIPTIO N Does not apply to PCI Express. Must be hardwired to 00h. HEADER TYPE REGISTER – OFFSET 0Ch BIT FUNCTIO N TYPE 23:16 Header T ype RO DESCRIPTIO N Read as 01h to indicate that the register layout conforms to the standard PCIto-PCI Bridge layout. PRIMARY BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTIO N 7:0 Primary Bus Number TYPE RW DESCRIPTIO N Indicates the number of the PCI bus to which the primary interface is connected. T he value is set in software during configuration. Reset to 00h. 7.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTIO N TYPE 15:8 Secondary Bus Number RW PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N Indicates the number of the PCI bus to which the secondary interface is connected. T he value is set in software during configuration. Reset to 00h. Page 42 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.12 7.2.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h BIT FUNCTIO N 23:16 Subordinate Bus Number RW DESCRIPTIO N Indicates the number of the PCI bus with the highest number that is subordinate to the Bridge. T he value is set in software during configuration. Reset to 00h. SECONDARY LATENCY TIMER REGISTER – OFFSET 18h BIT 31:24 7.2.14 TYPE FUNCTIO N Secondary Latency T imer TYPE RO DESCRIPTIO N Does not apply to PCI Express. Must be hardwired to 00h. I/O BASE ADDRESS REGISTER – OFFSET 1Ch BIT 3:0 FUNCTIO N 32-bit Indicator TYPE RO 7:4 I/O Base Address [15:12] RW DESCRIPTIO N Read as 01h to indicate 32-bit I/O addressing. Defines the bottom address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. T he upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register. Reset to 0h. 7.2.15 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch BIT 11:8 FUNCTIO N 32-bit Indicator 15:12 I/O Limit Address [15:12] TYPE RO RW DESCRIPTIO N Read as 01h to indicate 32-bit I/O addressing. Defines the top address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. T he upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit address upper 16 bits address register. Reset to 0h. 7.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch BIT 20:16 21 22 23 24 26:25 27 PI7C9X2G404SL FUNCTIO N Reserved 66MHz Capable Reserved Fast Back-to-Back Capable Master Data Parity Error DEVSEL_L timing Signaled T arget Abort Document Number DS40068 Rev 2-2 TYPE RsvdP RO RsvdP RO DESCRIPTIO N Not Support. Does not apply to PCI Express. Must be hardwired to 0b. Not Support. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the secondary side of the port in a Switch. RWC RO RO If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request in the secondary side using Completer Abort Completion Status. Page 43 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 28 29 30 31 FUNCTIO N TYPE Received T arget Abort RO Received Master Abort RO Received System Error RWC Detected Parity Error RWC DESCRIPTIO N Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status in the secondary side. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status in secondary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Bridge Control register is 1. Reset to 0b. Set to 1 whenever the secondary side of the port in a Switch receives a Poisoned TLP. Reset to 0b. 7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h BIT 3:0 FUNCTIO N Reserved 15:4 Memory Base Address [15:4] TYPE RsvdP RW DESCRIPTIO N Not Support. Defines the bottom address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. T he upper 12 bits correspond to address bits [31:20] and are able to be written to. T he lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 000h. 7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h BIT 19:16 FUNCTIO N Reserved 31:20 Memory Limit Address [31:20] TYPE RsvdP RW DESCRIPTIO N Not Support. Defines the top address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. T he upper 12 bits correspond to address bits [31:20] and are writable. T he lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh. Reset to 000h. 7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h BIT 3:0 FUNCTIO N 64-bit addressing 15:4 Prefetchable Memory Base Address [31:20] TYPE RO RW DESCRIPTIO N Read as 0001b to indicate 64-bit addressing. Defines the bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. T he lower 20 bits are assumed to be 0. T he memory base register upper 32 bits contain the upper half of the base address. Reset to 000h. 7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h BIT 19:16 PI7C9X2G404SL FUNCTIO N 64-bit addressing Document Number DS40068 Rev 2-2 TYPE RO DESCRIPTIO N Read as 0001b to indicate 64-bit addressing. Page 44 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N 31:20 Prefetchable Memory Limit Address [31:20] TYPE RW DESCRIPTIO N Defines the top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. T he upper 12 bits correspond to address bits [31:20] and are writable. T he lower 20 bits are assumed to be FFFFFh. T he memory limit upper 32 bits register contains the upper half of the limit address. Reset to 000h. 7.2.21 7.2.22 7.2.23 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h BIT FUNCTIO N 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] TYPE RW DESCRIPTIO N Defines the upper 32-bits of a 64-bit bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0000_0000h. PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch BIT FUNCTIO N 31:0 Prefetchable Memory Limit Address, Upper 32-bits [63:32] TYPE RW DESCRIPTIO N Defines the upper 32-bits of a 64-bit top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0000_0000h. I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h BIT FUNCTIO N 15:0 I/O Base Address, Upper 16-bits [31:16] TYPE RW DESCRIPTIO N Defines the upper 16-bits of a 32-bit bottom address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. 7.2.24 7.2.25 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h BIT FUNCTIO N 31:16 I/O Limit Address, Upper 16-bits [31:16] TYPE RW DESCRIPTIO N Defines the upper 16-bits of a 32-bit top address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. CAPABILITY POINTER REGISTER – OFFSET 34h BIT FUNCTIO N 7:0 Capability Pointer PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RO DESCRIPTIO N Pointer points to the PCI power management registers. Reset to 40h. Page 45 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch BIT 7:0 7.2.27 FUNCTIO N Interrupt Line TYPE RW DESCRIPTIO N Reset to 00h. INTERRUPT PIN REGISTER – OFFSET 3Ch BIT FUNCTIO N TYPE 15:8 Interrupt Pin RO DESCRIPTIO N T he Switch implements INTA virtual wire interrupt signals to represent hotplug events at downstream ports. The default value on the downstream ports may be changed by SMBus or auto-loading from EEPROM. Reset to 00h. 7.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch BIT FUNCTIO N TYPE 16 Parity Error Response RW 17 18 S_SERR# enable ISA Enable RW RW DESCRIPTIO N 0b: Ignore Poisoned TLPs on the secondary interface 1b: Enable the Poisoned T LPs reporting and detection on the secondary interface Reset to 0b. 0b: Disables the forwarding of EER_COR, ERR_NONFATAL and ERR_FAT AL from secondary to primary interface 1b: Enables the forwarding of EER_COR, ERR_NONFATAL and ERR_FAT AL from secondary to primary interface Reset to 0b. 0b: Forwards downstream all I/O addresses in the address range defined by the I/O Base, I/O Base, and Limit registers 1b: Forwards upstream all I/O addresses in the address range defined by the I/O Base and Limit registers that are in the first 64KB of PCI I/O address space (top 768 bytes of each 1KB block) Reset to 0b. 0b: Ignores access to the VGA memory or IO address range 1b: Forwards transactions targeted at the VGA memory or IO address range 19 VGA Enable RW 20 VGA 16-bit decode RW 21 Master Abort Mode RO 22 Secondary Bus Reset RW 23 24 25 26 PI7C9X2G404SL Fast Back-to-Back Enable Primary Master T imeout Secondary Master T imeout Master T imeout Document Number DS40068 Rev 2-2 RO RO RO RO VGA memory range starts from 000A 0000h to 000B FFFFh VGA IO addresses are in the first 64KB of IO address space. AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh. Reset to 0b. 0b: Executes 10-bit address decoding on VGA I/O accesses 1b: Executes 16-bit address decoding on VGA I/O accesses Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. 0b: Does not trigger a hot reset on the corresponding PCI Express Port 1b: T riggers a hot reset on the corresponding PCI Express Port At the downstream port, it asserts PORT_RST# to the attached downstream device. At the upstream port, it asserts the PORT_RST # at all the downstream ports. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Page 46 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 27 31:28 7.2.29 TYPE DESCRIPTIO N Does not apply to PCI Express. Must be hardwired to 0b. RO RsvdP Not Support. POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h BIT 7:0 15:8 18:16 19 20 FUNCTIO N Enhanced Capabilities ID Next Item Pointer Power Management Revision PME# Clock Reserved TYPE RO RO RO RO RsvdP 21 Device Specific Initialization RO 24:22 AUX Current RO 25 26 31:27 7.2.30 FUNCTIO N Status Discard T imer SERR# enable Reserved D1 Power State Support D2 Power State Support PME# Support RO RO RO DESCRIPTIO N Read as 01h to indicate that these are power management enhanced capability registers. T he pointer points to the Vital Protocol Data (VPD) capability register/the Message capability register. Reset to 5Ch (Upstream port). Reset to 4Ch (Downstream ports). Read as 011b to indicate the device is compliant to Revision 1.2 of PCI Power Management Interface Specifications. Does not apply to PCI Express. Must be hardwired to 0b. Not Support. Read as 0b to indicate Switch does not have device specific initialization requirements. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 1b to indicate Switch supports the D1 power management state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 1b to indicate Switch supports the D2 power management state. The default value may be changed by SMBus or auto-loading from EEPROM. Read as 11111b to indicate Switch supports the forwarding of PME# message in all power states. The default value may be changed by SMBus or autoloading from EEPROM. POWER MANAGEMENT DATA REGISTER – OFFSET 44h BIT FUNCTIO N TYPE 1:0 Power State RW 2 Reserved 3 No_Soft_Reset 7:4 Reserved RsvdP 8 PME# Enable RWS 12:9 Data Select RW 14:13 Data Scale RO 15 PME status ROS PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N Indicates the current power state of the Switch. Writing a value of D0 when the previous state was D3 cause a hot reset without asserting DWNRST_L. 00b: D0 state 01b: D1 state 10b: D2 state 11b: D3 hot state RsvdP RO Reset to 00b. Not Support. When set, this bit indicates that device transitioning from D3hot to D0 does not perform an internal reset. When clear, an internal reset is performed when power state transits from D3hot to D0. This bit can be rewritten with EEPROM programming. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1b. Not Support. When asserted, the Switch will generate the PME# message. Reset to 0b. Select data registers. Reset to 0h. Reset to 00b. Read as 0b as the PME# message is not implemented. Page 47 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 7.2.31 TYPE DESCRIPTIO N Reset to 0b. PPB SUPPORT EXTENSIONS – OFFSET 44h BIT 21:16 22 23 7.2.32 FUNCTIO N FUNCTIO N Reserved B2_B3 Support for D3 HOT Bus Power / Clock Control Enable TYPE RsvdP RO DESCRIPTIO N Not Support. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. RO DATA REGISTER – OFFSET 44h BIT FUNCTIO N TYPE 31:24 Data Register RO DESCRIPTIO N Data Register. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00h. 7.2.33 MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only) BIT 7:0 15:8 7.2.34 Next Item Pointer TYPE RO RO DESCRIPTIO N Read as 05h to indicate that this is message signal interrupt capability register. Pointer points to the Vendor specific capability register. Reset to 64h. MESSAGE CONTROL REGISTER – OFFSET 4Ch (Downstream Port Only) BIT FUNCTIO N TYPE 16 MSI Enable RW 19:17 22:20 7.2.35 FUNCTIO N Enhanced Capabilities ID Multiple Message Capable Multiple Message Enable 23 64-bit address capable 31:24 Reserved DESCRIPTIO N 0b: T he function is prohibited from using MSI to request service 1b: T he function is permitted to use MSI to request service and is prohibited from using its INT x # pin Reset to 0b. Read as 000b. RO Reset to 000b. RW 0b: T he function is not capable of generating a 64-bit message address 1b: T he function is capable of generating a 64-bit message address RO Reset to 1b. Not Support. RsvdP MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) BIT 1:0 FUNCTIO N Reserved TYPE RsvdP 31:2 Message Address RW DESCRIPTIO N Not Support. If the message enable bit is set, the contents of this register specify the DWORD aligned address for MSI memory write transaction. Reset to 0000_0000h. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 48 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.36 7.2.37 MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) BIT FUNCTIO N 31:0 Message Upper Address Reset to 0000_0000h. FUNCTIO N Message Data Reserved TYPE RW RsvdP DESCRIPTIO N Reset to 0000h. Not Support. VPD CAPABILITY REGISTER – OFFSET 5Ch (Upstream Port Only) BIT 7:0 15:8 7.2.39 RW DESCRIPTIO N T his register is only effective if the device supports a 64-bit message address is set. MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) BIT 15:0 31:16 7.2.38 TYPE FUNCTIO N Enhanced Capabilities ID Next Item Pointer TYPE RO DESCRIPTIO N Read as 03h to indicate that these are VPD enhanced capability registers. Pointer points to the Vendor specific capability register. RO Reset to 64h. VPD REGISTER – OFFSET 5Ch (Upstream Port Only) BIT 17:16 FUNCTIO N Reserved TYPE RsvdP 23:18 VPD Address RW 30:24 Reserved 31 VPD operation DESCRIPTIO N Not Support. Contains DWORD address that is used to generate read or write cycle to the VPD table stored in EEPROM. Reset to 00_0000b. Not Support. 0b: Performs VPD read command to VPD table at the location as specified in VPD address. T his bit is kept ‘0’ and then set to ‘1’ automatically after EEPROM cycle is finished 1b: Performs VPD write command to VPD table at the location as specified in VPD address. T his bit is kept ‘1’ and then set to ‘0’ automatically after EEPROM cycle is finished. RsvdP RW Reset to 0b. 7.2.40 VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) BIT FUNCTIO N 31:0 VPD Data TYPE DESCRIPTIO N When read, it returns the last data read from VPD table at the location as specified in VPD Address. RW When written, it places the current data into VPD table at the location as specified in VPD Address. Reset to 0000_0000h. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 49 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.41 VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h BIT 7:0 FUNCTIO N Enhanced Capabilities ID TYPE RO 15:8 Next Item Pointer RO 31:16 Length Information RO DESCRIPTIO N Read as 09h to indicate that these are vendor specific capability registers. Pointer points to the SSID/SSVID capability register. Reset to B0h. T he length field provides the information for number of bytes in the capability structure (including the ID and Next pointer bytes). Reset to 0034h. 7.2.42 XPIP CSR0 – OFFSET 68h (Test Purpose Only) BIT 31:0 7.2.43 DESCRIPTIO N Reset to 0400_1060h. FUNCTIO N XPIP_CSR1 TYPE RW DESCRIPTIO N Reset to 0400_0800h. REPLAY TIME-OUT COUNTER – OFFSET 70h BIT FUNCTIO N 11:0 User Replay T imer TYPE RW Enable User Replay T imer RW 13 Power Management Capability Disable RO 14 MSI Capability Disable RO 15 Reserved 12 7.2.45 TYPE RW XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) BIT 31:0 7.2.44 FUNCTIO N XPIP_CSR0 DESCRIPTIO N A 12-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000h. When asserted, the user-defined replay time-out value is be employed. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Not Support. RsvdP ACKNOWLEDGE LATENCY TIMER – OFFSET 70h BIT FUNCTIO N 29:16 User ACK Latency T imer RW Enable User ACK Latency RW VGA decode enable RO 30 31 PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE DESCRIPTIO N A 14-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. When asserted, the user-defined ACK latency value is be employed. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Enable the VGA range decode. Reset to 1b. Page 50 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.46 SWITCH OPERATION MODE – OFFSET 74h (Upstream Port Only) BIT FUNCTIO N TYPE 0 Store-Forward RW DESCRIPTIO N When set, a store-forward mode is used. Otherwise, the chip is working under cut-through mode. The default value may be changed by SMBus or autoloading from EEPROM. Reset to 0b. Cut-through Threshold. When forwarding a packet from low-speed port to high-speed mode, the chip provides the capability to adjust the forwarding threshold. T he default value may be changed by SMBus or auto-loading from EEPROM. 2:1 3 4 Cut-through T hreshold Port Arbitration Mode Credit Update Mode 6 Ordering on Different T ag of Completion Mode RW 7 Reserved 13:8 Power management Control parameter RW 14 RX Polarity Inversion Disable RO 15 Compliance pattern Parity Control Disable RO C_DRV_LVL_3P5_ NOM RO C_DRV_LVL_6P0_ NOM RO 25:21 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Reset to 0b. When set, the frequency of releasing new credit to the link partner will be all types per update. When clear, the frequency of releasing new credit to the link partner will be type oriented per update. RW RW 20:16 Reset to 01b. When set, the round-robin arbitration will stay in the arbitrated port even if the credit is not enough but request is pending. When clear, the round-robin arbitration will always go to the requesting port, which the outgoing credit is enough for the packet queued in the port. T he default value may be changed by SMBus or auto-loading from EEPROM. RW Ordering on Different Egress Port Mode 5 00b: the threshold is set at the middle of forwarding packet 01b: the threshold is set ahead 1-cycle of middle point 10b: the threshold is set ahead 2-cycle of middle point 11b: the threshold is set ahead 3-cycle of middle point RW T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When set, there has ordering rule on packets for different egress port. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When set, there has ordering rule between completion packet with different tag. T he default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 0b. Not Support. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00_0001b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0011b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0011b. Page 51 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.47 BIT FUNCTIO N 30:26 C_DRV_LVL_HALF _NOM 31 Reserved RO RsvdP DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0_0010b. Not Support. SWITCH OPERATION MODE – OFFSET 74h (Downstream Port Only) BIT 7:0 FUNCTIO N Reserved 13:8 Power Management Control Parameter TYPE RsvdP RW 14 RX Polarity Inversion Disable 15 Compliance Pattern Parity Control Disable RO C_DRV_LVL_3P5_ NOM RO C_DRV_LVL_6P0_ NOM RO 30:26 C_DRV_LVL_6P0_ NOM RO 31 Reserved 20:16 25:21 7.2.48 TYPE HwInt RO DESCRIPTIO N Not Support. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00_0001b. T he default value may be changed by the status of strapped pin, SMBus or auto-loading from EEPROM. Reset to the status of RXPOLINV_DIS strapped pin. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0011b. .T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0011b. T he default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 0_0010b. Not Support. XPIP_CSR2 – OFFSET 78h BIT FUNCTIO N TYPE 15:0 XPIP_CSR2 RO DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0080h. 7.2.49 PHY PARAMETER 1 – OFFSET 78h BIT FUNCTIO N 20:16 C_EMP_POST _ GEN1_3P5_NOM RO C_EMP_POST _ GEN2_3P5_NOM RO 30:26 C_EMP_POST _ GEN2_6P0_NOM RO 31 Reserved 25:21 PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0101b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1_0101b. T he default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 1_1101b. Not Support. Page 52 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.50 PHY PARAMETER 2 – OFFSET 7Ch BIT FUNCTIO N TYPE 3:0 C_T X_PHY_ LAT ENCY RO 6:4 C_REC_DETECT_ USEC RO 7 Reserved 8 P_CDR_FREQLOOP _EN RO P_CDR_ T HRESHOLD RO 12:11 P_CDR_FREQLOOP _GAIN RO 15:13 Reserved 16 P_DRV_LVL_MGN_ DELAT A_EN RO P_DRV_LVL_NOM_ DELAT A_EN RO P_EMP_POST _MGN _DELATA_EN RO P_EMP_POST _NOM _DELATA_EN RO P_RX_SIGDET_LVL RO 10:9 17 18 19 21:20 25:22 29:26 P_RX_EQ_1 P_RX_EQ_2 30 P_T XSWING 31 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0111b. T he default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 010b. Not Support. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 10b. T he default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 11b. Not Support. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 01b. T he default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 0110b. T he default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 1000b. T he default value may be changed by SMBus or auto-loading from EEPROM. RO RsvdP Reset to 0b. Not Support. Page 53 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.51 XPIP_CSR3 – OFFSET 80h BIT FUNCTIO N TYPE 31:0 XPIP_CSR3 RW DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000F_0000h. 7.2.52 XPIP_CSR4 – OFFSET 84h BIT FUNCTIO N TYPE 31:0 XPIP_CSR4 RO DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000_0000h. 7.2.53 XPIP_CSR5 – OFFSET 88h BIT FUNCTIO N TYPE 29:0 XPIP_CSR5 RO 30 DO_CHG_DAT A_ RAT E_CTRL RO 31 Gen1_Cap_Only RO DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 7308_3333h (Upstream port). Reset to 3308_3333h (Downstream ports). T he default value may be changed by SMBus, I2C or auto-loading from EEPROM. Reset to 1b (Upstream port). Reset to 0b (Downstream ports). T he default value may be changed by SMBus, I2C or auto-loading from EEPROM. Reset to 0b. 7.2.54 TL_CSR – OFFSET 8Ch BIT FUNCTIO N 0 T X_SOF_FORM 1 2 3 4 TYPE RO PM Data Select Register R/W Capability RO FC_UPDATE_ MODE RO 4K Boundary Check Enable RO FIFOERR_FIX_SEL RO DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1b. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 54 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N TYPE 5 MW Overpass Disable RW Ordering Frozen Disable RW GNT _FAIL2IDLE RO 6 7 9:8 10 DO_CHG_DAT A_ CNT _SEL RO Port Disable RO 11 Reset Select 12 15:13 ARB_VCFLG_SEL Reserved 23:16 XPIP_CSR6 25:24 REV_T S_CT R 29:26 MAC Control Parameter 30 Reserved 31 P35_GEN2_MODE DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. Disable the RO ordering rule. T he default value may be changed by SMBus or auto-loading from EEPROM Reset to 0b. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. T he trying number for doing change data rate. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00b. Disable this port. The default value may be changed by SMBus or autoloading from EEPROM. Reset to 0b. Reset select (upstream port only). The default value may be changed by SMBus or auto-loading from EEPROM. RO RO RsvdP RO Reset to 0b. Reset to 0b. Not Support. XPIP_CSR6 Value. T he default value may be changed by SMBus or autoloading from EEPROM. Reset to 79h. T he default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 00b. T he default value may be changed by SMBus or auto-loading from EEPROM. RO RsvdP RO Reset to 0h. Not Support. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. 7.2.55 7.2.56 PHY PARAMETER 3 – OFFSET 90h BIT FUNCTIO N 6:0 PHY Parameter 3 (per lane) 14:7 Reserved 31:15 PHY Parameter 3 (global) TYPE RO DESCRIPTIO N PHY’s Lane mode. Reset to 00h. Not Support. PHY’s delta value setting. RsvdP RO Reset to 0_0001h. PHY PARAMETER 4 - OFFSET 94h BIT 15:0 FUNCTIO N PHY T X Margin TYPE RO 23:16 Multilane RXEQ RO 31:24 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 RsvdP DESCRIPTIO N Reset to 116Bh. Upstream p Port only. Reset to 86h. Reserved for Downstream Port. Reset to 00h. Not Support. Page 55 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.57 7.2.58 OPERATION MODE –OFFSET 98h BIT FUNCTIO N 15:0 Operation mode RO 20:16 Clock buffer control HwInt RO 31:21 Reserved RsvdP DESCRIPTIO N { 7'd0, SCAN_MODE, PKG_SEL[2:0], PHY_MODE, DEBUG_MODE, FAST _MODE, IDDQB, SROM_BYPASS} For Reference clock buffer control. The default value may be changed by the status of strapped pin, SMBus or auto-loading from EEPROM. Bit[20]: Reset to the status of CLKBUF_PD strapped pin. Bit[19:16]: Reset to Fh. Bit[20]: enable or disable reference clock outputs 0b: enable reference clock outputs 1b: disable reference clock outputs Bit[19:16]: enable or disable REFCLKO_P/N[3:0] 0b: disable 1b: enable Not Support. SSID/SSVID CAPABILITY REGISTER – OFFSET B0h BIT 7:0 15:8 7.2.59 TYPE FUNCTIO N SSID/SSVID Capabilities ID Next Item Pointer TYPE RO DESCRIPTIO N Read as 0Dh to indicate that these are SSID/SSVID capability registers. Pointer points to the PCI Express capability register. RO Reset to C0h. SUBSYSTEM VENDOR ID REGISTER – OFFSET B4h BIT 15:0 FUNCTIO N SSVID TYPE RO DESCRIPTIO N It indicates the sub-system vendor id. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. 7.2.60 SUBSYSTEM ID REGISTER – OFFSET B4h BIT 31:16 FUNCTIO N SSID TYPE RO DESCRIPTIO N It indicates the sub-system device id. T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. 7.2.61 GPIO CONTROL REGISTER – OFFSET B8h (Upstream Port Only) BIT 0 FUNCTIO N GPIO [0] Input 1 GPIO [0] Output Enable RW GPIO [0] Output Register RW 2 PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RO DESCRIPTIO N State of GPIO [0] pin 0b: GPIO [0] is an input pin 1b: GPIO [0] is an output pin Reset to 0b. Value of this bit will be output to GPIO [0] pin if GPIO [0] is configured as an output pin. Reset to 0b. Page 56 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 3 4 FUNCTIO N Reserved GPIO [1] Input 5 GPIO [1] Output Enable RW 6 GPIO [1] Output Register RW 7 8 Reserved GPIO [2] Input 9 GPIO [2] Output Enable RW 10 GPIO [2] Output Register RW 11 12 Reserved GPIO [3] Input 13 GPIO [3] Output Enable RW 14 GPIO [3] Output Register RW 15 16 Reserved GPIO [4] Input 17 GPIO [4] Output Enable RW 18 GPIO [4] Output Register RW 19 20 Reserved GPIO [5] Input 21 GPIO [5] Output Enable RW 22 GPIO [5] Output Register RW 23 24 Reserved GPIO [6] Input 25 GPIO [6] Output Enable RW 26 GPIO [6] Output Register RW 27 28 Reserved GPIO [7] Input 29 GPIO [7] Output Enable PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RsvdP RO Reset to 0b. Value of this bit will be output to GPIO [1] pin if GPIO [1] is configured as an output pin. RsvdP RO Reset to 0b. Not Support. State of GPIO [2] pin 0b: GPIO [2] is an input pin 1b: GPIO [2] is an output pin Reset to 0b. Value of this bit will be output to GPIO [2] pin if GPIO [2] is configured as an output pin. RsvdP RO Reset to 0b. Not Support. State of GPIO [3] pin. 0b: GPIO [3] is an input pin 1b: GPIO [3] is an output pin Reset to 0b. Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as an output pin. RsvdP RO Reset to 0b. Not Support. State of GPIO [4] pin. 0b: GPIO [4] is an input pin 1b: GPIO [4] is an output pin Reset to 0b. Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as an output pin. RsvdP RO Reset to 0b. Not Support. State of GPIO [5] pin. 0b: GPIO [5] is an input pin 1b: GPIO [5] is an output pin Reset to 0b. Value of this bit will be output to GPIO [5] pin if GPIO [5] is configured as an output pin. RsvdP RO Reset to 0b. Not Support. State of GPIO [6] pin. 0b: GPIO [6] is an input pin 1b: GPIO [6] is an output pin Reset to 0b. Value of this bit will be output to GPIO [6] pin if GPIO [6] is configured as an output pin. RsvdP RO RW DESCRIPTIO N Not Support. State of GPIO [1] pin. 0b: GPIO [1] is an input pin 1b: GPIO [1] is an output pin Reset to 0b. Not Support. State of GPIO [7] pin. 0b: GPIO [7] is an input pin 1b: GPIO [7] is an output pin Reset to 0b. Page 57 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.62 BIT FUNCTIO N 30 GPIO [7] Output Register 31 Reserved TYPE RW RsvdP DESCRIPTIO N Value of this bit will be output to GPIO [7] pin if GPIO [7] is configured as an output pin. Reset to 0b. Not Support. EEPROM CONTROL REGISTER – OFFSET BCh (Upstream Port Only) BIT FUNCTIO N 0 EEPROM Start RW 1 EEPROM Command RW 2 EEPROM Error Status RO 3 EEPROM Autoload Success RO Reset to 0b. 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autolad occurred successfully after RESET. Configuration registers were loaded with values in the EEPROM RO It will be cleared when read at this bit. 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autoload occurred successfully after PREST . Configuration registers were loaded with values stored in the EEPROM 4 5 7:6 EEPROM Autoload Status TYPE EEPROM Autoload Disable RW EEPROM Clock Rate RW DESCRIPTIO N Starts the EEPROM read or write cycle. Reset to 0b. Sends the command to the EEPROM. 0b: EEPROM read 1b: EEPROM write Reset to 0b. 1b: EEPROM acknowledge was not received during the EEPROM cycle. Reset to 0b. 0b: EEPROM autoload enabled 1b: EEPROM autoload disabled Reset to 1b. Determines the frequency of the EEPROM clock, which is derived from the primary clock. 00b: Reserved 01b: PEXCLK / 1024 (PEXCLK is 125MHz) 10b: Reserved 11b: T est Mode Reset to 01b. 7.2.63 7.2.64 EEPROM ADDRESS REGISTER – OFFSET BCh (Upstream Port Only) BIT 8 FUNCTIO N Reserved 15:9 EEPROM Address TYPE RsvdP RW DESCRIPTIO N Not Support. Contains the EEPROM address. Reset to 0000h. EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only) BIT FUNCTIO N 31:16 EEPROM Data TYPE RW DESCRIPTIO N Contains the data to be written to the EEPROM. After completion of a read cycle, this register will contain the data from the EEPROM. Reset to 0000h. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 58 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.65 PCI EXPRESS CAPABILITY REGISTER – OFFSET C0h BIT TYPE 15:8 FUNCTIO N Enhanced Capabilities ID Next Item Pointer 19:16 Capability Version RO 23:20 Device/Port Type RO 24 Slot Implemented HwInt RO 7:0 29:25 31:30 7.2.66 Interrupt Message Number Reserved RO RO DESCRIPTIO N Read as 10h to indicate that these are PCI express enhanced capability registers. Read as 00h. No other ECP registers. Read as 0010b to indicate the device is compliant to Revision .2.0a of PCI Express Base Specifications. Indicates the type of PCI Express logical device. Reset to 0101b (Upstream port). Reset to 0110b (Downstream ports). When set, indicates that the PCIe Link associated with this Port is connected to a slot. T his field is valid for downstream port of the Switch. The default value may be changed by the status of strapped pin, SMBus or auto-loading from EEPROM. Reset to the status of SLOT_IMP strapped pin. Read as 0b. No MSI messages are generated in the transparent mode. RO RsvdP Not Support. DEVICE CAPABILITIES REGISTER – OFFSET C4h BIT FUNCTIO N TYPE 2:0 Max_Payload_Size Supported HwInt RO Phantom Functions Supported RO Extended Tag Field Supported RO Endpoint L0s Acceptable Latency RO Reset to 0b. Acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. For Switch, the ASPM software would not check this value. RO Reset to 000b. Acceptable total latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. For Switch, the ASPM software would not check this value. 4:3 5 8:6 11:9 Endpoint L1 Acceptable Latency 14:12 Reserved 15 Role_Based Error Reporting 17:16 Reserved 25:18 Captured Slot Power Limit Value Reset to 001b when PL_512B strapped pin is set to 0. Reset to 010b when PL_512B strapped pin is set to 1. Indicates the support for use of unclaimed function numbers as Phantom functions. Read as 00b, since the Switch does not act as a requester. Reset to 00b. Indicates the maximum supported size of Tag field as a Requester. Read as 0, since the Switch does not act as a requester. RsvdP RO RsvdP RO DESCRIPTIO N Indicates the maximum payload size that the device can support for TLPs. T he default value may be changed by the status of strapped pin, SMBus or auto-loading from EEPROM. Reset to 000b. Not Support. When set, indicates that the device implements the functionality originally defined in the Error Reporting ECN. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 1b. Not Support. It applies to Upstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. T his value is set by the Set_Slot_Power_Limit message or hardwired to 00h. Reset to 00h. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 59 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.67 BIT FUNCTIO N 27:26 Captured Slot Power Limit Scale 31:28 Reserved TYPE RO DESCRIPTIO N It applies to Upstream Port only. Specifies the scale used for the Slot Power Limit Value. T his value is set by the Set_Slot_Power_Limit message or hardwired to 00b. RsvdP Reset to 00b. Not Support. DEVICE CONTROL REGISTER – OFFSET C8h BIT FUNCTIO N 0 Correctable Error Reporting Enable RW Non-Fatal Error Reporting Enable RW Fatal Error Reporting Enable RW Unsupported Request Reporting Enable RW Enable Relaxed Ordering RO 1 2 3 4 7:5 Max_Payload_Size TYPE DESCRIPTIO N 0b: Disable Correctable Error Reporting 1b: Enable Correctable Error Reporting Reset to 0b. 0b: Disable Non-Fatal Error Reporting 1b: Enable Non-Fatal Error Reporting Reset to 0b. 0b: Disable Fatal Error Reporting 1b: Enable Fatal Error Reporting Reset to 0b. 0b: Disable Unsupported Request Reporting 1b: Enable Unsupported Request Reporting Reset to 0b. When set, it permits the device to set the Relaxed Ordering bit in the attribute field of transaction. Since the Switch can not either act as a requester or alter the content of packet it forwards, this bit always returns ‘0’ when read. Reset to 0b. T his field sets maximum TLP payload size for the device. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported in the Device Capabilities register. Any value exceeding the Max_Payload_Size Supported written to this register results into clamping to the Max_Payload_Size Supported value. RW Reset to 000b. Does not apply to PCI Express Switch. Returns ‘0’ when read. 8 Extended Tag Field Enable RW 9 Phantom Function Enable RW 10 Auxiliary (AUX) Power PM Enable RWS Enable No Snoop RO Reset to 0b. When set, it permits to set the No Snoop bit in the attribute field of transaction. Since the Switch can not either act as a requester or alter the content of packet it forwards, this bit always returns ‘0’ when read. RO Reset to 0b. T his field sets the maximum Read Request size for the device as a Requester. Since the Switch does not generate read request by itself, these bits are hardwired to 000b. 11 14:12 Max_Read_ Request_Size 15 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 Reset to 0b. Does not apply to PCI Express Switch. Returns ‘0’ when read. Reset to 0b. When set, indicates that a device is enabled to draw AUX power independent of PME AUX power. RsvdP Reset to 000b. Not Support. Page 60 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.68 DEVICE STATUS REGISTER – OFFSET C8h BIT FUNCTIO N TYPE 16 Correctable Error Detected RW1C DESCRIPTIO N Asserted when correctable error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when non-fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when unsupported request is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 17 18 7.2.69 Non-Fatal Error Detected Fatal Error Detected 19 Unsupported Request Detected 20 AUX Power Detected RO 21 T ransactions Pending RO 31:22 Reserved Reset to 0b. Asserted when the AUX power is detected by the Switch Reset to 1b. Each port of Switch does not issue Non-posted Requests on its own behalf, so this bit is hardwired to 0b. RsvdP Reset to 0b. Not Support. LINK CAPABILITIES REGISTER – OFFSET CCh BIT FUNCTIO N 3:0 Maximum Link Speed RO 9:4 Maximum Link Width RO 11:10 Active State Power Management (ASPM) Support RO L0s Exit Latency RO 14:12 TYPE Reset to 0010b (5 G b/s). Indicates the maximum width of the given PCIe Link. Reset to 00_0001b (x1). Indicates the level of ASPM supported on the given PCIe Link. Each port of Switch supports L0s and L1 entry. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00b. Indicates the L0s exit latency for the given PCIe Link. T he length of time this port requires to complete transition from L0s to L0 is in the range of 256ns to less than 512ns. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 011b. Indicates the L1 exit latency for the given PCIe Link. T he length of time this port requires to complete transition from L1 to L0 is in the range of 16us to less than 32us. The default value may be changed by SMBus or auto-loading from EEPROM. 17:15 L1 Exit Latency RO 19:18 Reserved RsvdP PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N Indicates the maximum speed of the Express link. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 000b. Not Support. Page 61 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.70 BIT FUNCTIO N TYPE 20 Data Link Layer Active Reporting Capable RO 21 Link bw notify cap RO 23:21 Reserved 31:24 Port Number DESCRIPTIO N For a Downstream Port, this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port, this bit must be set to 1b. For Upstream Port, this bit must be hardwired to 0b. RsvdP RO Reset to 0b. Reset to 0b (Upstream port). Reset to 1b (Downstream ports). Not Support. Indicates the PCIe Port Number for the given PCIe Link. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00h for Port 0. Reset to 01h for Port 1. Reset to 02h for Port 2. Reset to 03h for Port 3. LINK CONTROL REGISTER – OFFSET D0h BIT FUNCTIO N 1:0 Active State Power Management (ASPM) Control 2 Reserved 3 Read Completion Boundary (RCB) RO 4 Link Disable RW 5 6 Retrain Link Common Clock Configuration TYPE RW Note that the receiver must be capable of entering L0s even when the field is disabled. RsvdP Reset to 0b. At upstream port, it is not allowed to retrain the link, so this bit is hardwired to 0b. For downstream ports, it initiates Link Retraining when this bit is set. RW T his bit always returns 0b when read. 0b: T he components at both ends of a link are operating with asynchronous reference clock 1b: T he components at both ends of a link are operating with a distributed common reference clock RW Reset to 0b. When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0 state and transmits 1024 T S1 ordered sets in the L1 state for entering L0 state. Extended Synch RW 8 Reserved HW Autonomous width Disable RsvdP RW Link Bandwidth Management Interrupt Enable RO/RW 11 Link Autonomous Bandwidth Interrupt Enable RO/RW 15:12 Reserved RsvdP 10 PI7C9X2G404SL Document Number DS40068 Rev 2-2 Reset to 00b. Not Support. Does not apply to PCI Express Switch. Returns ‘0’ when read. Reset to 0b. At upstream port, it is not allowed to disable the link, so this bit is hardwired to ‘0’. For downstream ports, it disables the link when this bit is set. 7 9 DESCRIPTIO N 00b: ASPM is Disabled 01b: L0s Entry Enabled 10b: L1 Entry Enabled 11b: L0s and L1 Entry Enabled Reset to 0b. Not Support. Reset to 0b. For upstream Port is RO. For downstream Port is RW. Reset to 0b. For upstream Port is RO. For downstream Port is RW. Reset to 0b. Not Support. Page 62 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.71 LINK STATUS REGISTER – OFFSET D0h BIT FUNCTIO N 19:16 Link Speed Negotiated Link Width RO 26 T raining Error RO 28 Link T raining Slot Clock Configuration 29 Data Link Layer Link Active 31:30 Reserved DESCRIPTIO N Indicate the negotiated speed of the Express link. 0001b: 2.5 Gb/s. 0010b: 5 Gb/s. RO 25:20 27 7.2.72 TYPE Reset to 0010b. Indicates the negotiated width of the given PCIe link. Reset to 00_0001b (x1). When set, indicates a Link training error occurred. T his bit is cleared by hardware upon successful training of the link to the L0 link state. Reset to 0b. When set, indicates the link training is in progress. Hardware clears this bit once link training is complete. RO Reset to 0b. 0b: the Switch uses an independent clock irrespective of the presence of a reference on the connector 1b: the Switch uses the same reference clock that the platform provides on the connector HwInt RO T he default value may be changed by the status of strapped pin, SMBus or auto-loading from EEPROM. Reset to the status of SLOTCLK strapped pin. Indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. RO Reset to 0b. Not Support. RsvdP SLOT CAPABILITIES REGISTER – OFFSET D4h (Downstream Port Only) BIT FUNCTIO N 0 Attention Button Present 1 Power Controller Present 2 Reserved 3 Attention Indicator Present 4 Power Indicator Present TYPE RO RO DESCRIPTIO N When set, it indicates that an Attention Button is implemented on the chassis for this slot. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. When set, it indicates that a Power Controller is implemented for this slot. T he default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 0b. Not Support. When set, it indicates that an Attention Indicator is implemented on the chassis for this slot. The default value may be changed by SMBus or autoloading from EEPROM. RO Reset to 0b. When set, it indicates that a Power Indicator is implemented on the chassis for this slot. The default value may be changed by SMBus or auto-loading from EEPROM. RsvdP Reset to 0b. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 63 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N 5 Hot-Plug Surprise 6 14:7 7.2.73 Hot-Plug Capable Slot Power Limit Value 16:15 Slot Power Limit Scale 18:17 Reserved 31:19 Physical Slot Number TYPE RO DESCRIPTIO N When set, it indicates that a device present in this slot might be removed from the system without any prior notification. The default value may be changed by SMBus or auto-loading from EEPROM. RO Reset to 0b. When set, it indicates that this slot is capable of supporting Hot-Plug operation. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. It applies to Downstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. The default value may be changed by SMBus or auto-loading from EEPROM. RW Reset to 00h. It applies to Downstream Port only. Specifies the scale used for the Slot Power Limit Value. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. T he default value may be changed by SMBus or auto-loading from EEPROM. RW Reset to 00b. Not Support. It indicates the physical slot number attached to this Port. The default value may be changed by SMBus or auto-loading from EEPROM. RsvdP RO Reset to 0000h. SLOT CONTROL REGISTER – OFFSET D8h (Downstream Port Only) BIT FUNCTIO N 0 Attention Button Pressed Enable RW 1 Power Fault Detected Enable RW 2 Reserved 3 Presence Detect Changed Enable RW 4 Command Completed Interrupt Enable RW Hot-Plug Interrupt Enable RW 5 7:6 Attention Indicator Control TYPE DESCRIPTIO N When set, it enables the generation of Hot-Plug interrupt or wakeup event on an attention button pressed event. Reset to 0b. When set, it enables the generation of Hot-Plug interrupt or wakeup event on a power fault event. RsvdP Reset to 0b. Not Support. When set, it enables the generation of Hot-Plug interrupt or wakeup event on a presence detect changed event. Reset to 0b. When set, it enables the generation of Hot-Plug interrupt when the Hot-Plug Controller completes a command. Reset to 0b. When set, it enables generation of Hot-Plug interrupt on enabled Hot-Plug events. Reset to 0b. Controls the display of Attention Indicator. RW 00b: Reserved 01b: On 10b: Blink 11b: Off Writes to this register also cause the Port to send the AT T ENTION_INDICATOR_* Messages. Reset to 11b. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 64 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 9:8 FUNCTIO N Power Indicator Control TYPE DESCRIPTIO N Controls the display of Power Indicator. 00b: Reserved 01b: On 10b: Blink 11b: Off RW Writes to this register also cause the Port to send the POWER_INDICATOR_* Messages. 7.2.74 10 Power Controller Control 11 Reserved 12 Data Link Layer State Changed Enable 15:13 Reserved Reset to 11b. 0b: reset the power state of the slot (Power On) 1b: set the power state of the slot (Power Off) RW RsvdP RW RsvdP Reset to 0b. Not Support. If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed. Reset to 0b. Not Support. SLOT STATUS REGISTER OFFSET D8h (Downstream Port Only) BIT FUNCTIO N TYPE 16 Attention Button Pressed RW1C 17 Power Fault Detected RW1C 18 MRL Sensor Changed RO 19 Presence Detect Changed RW1C 20 Command Completed RW1C 21 MRL Sensor State DESCRIPTIO N When set, it indicates the Attention Button is pressed. Reset to 0b. When set, it indicates a Power Fault is detected. Reset to 0b. When set, it indicates a MRL Sensor Changed is detected. Reset to 0b. When set, it indicates a Presence Detect Changed is detected. Reset to 0b. When set, it indicates the Hot-Plug Controller completes an issued command. Reset to 0b. Reflects the status of MRL Sensor. 0b: MRL Closed 1b: MRL Opened RO Reset to 0b. Indicates the presence of a card in the slot. 0b: Slot Empty 1b: Card Present in slot 22 Presence Detect State HwInt RO T his register is implemented on all Downstream Ports that implement slots. For Downstream Ports not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities register is 0b), this bit returns 1b. 23 Reserved RsvdP 24 Data Link Layer State Changed RW1C 31:25 Reserved RsvdP PI7C9X2G404SL Document Number DS40068 Rev 2-2 Reset to 1b when PRSNT strapped pin is set to 0. Reset to 0b when PRSNT strapped pin is set to 1. Not Support. T his bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed. Reset to 0b. Not Support. Page 65 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.75 7.2.76 7.2.77 DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h BIT 10:0 FUNCTIO N Device Capabilities 2 11 LT R Mechanism Supported RO 17:12 Device Capabilities 2 RO 19:18 OBFF Supported RO 31:20 Device Capabilities 2 RO Reset to 1b. Reset to 00h. T his field indicates if OBFF is supported. Reset to 01b. Reset to 000h. BIT 9:0 FUNCTIO N Device Control 2 TYPE RO 10 LT R Mechanism Enable RW 12:11 Device Control 2 RO 14:13 OBFF enable RW 15 Device Control 2 RO DESCRIPTIO N Reset to 000h. Enable LT R Mechanism. Reset to 0b. Reset to 00b. Enable OBFF Mechanism and select the signaling method. Reset to 00b. Reset to 0b. DEVIDE STATUS REGISTER 2 – OFFSET E8h FUNCTIO N Device status 2 TYPE RO DESCRIPTIO N Reset to 0000h. LINK CAPABILITIES REGISTER 2 – OFFSET ECh BIT 31:0 7.2.79 DESCRIPTIO N Reset to 000h. A value of 1b indicates support for the optional Latency Tolerance Reporting (LT R) mechanism. DEVICE CONTROL REGISTER 2 – OFFSET E8h BIT 31:16 7.2.78 TYPE RO FUNCTIO N Link Capabilities 2 TYPE RO DESCRIPTIO N Reset to 0000_0000h. LINK CONTROL REGISTER 2 – OFFSET F0h BIT 3:0 4 5 FUNCTIO N T arget Link Speed Enter Compliance HW_AutoSpeed_Dis 6 Select_Deemp 9:7 T ran_Margin Enter Modify Compliance Compliance SOS Compliance_Deemp Reserved 10 11 12 15:13 PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RWS RWS RW RO RWS RWS RWS RWS RsvdP DESCRIPTIO N Reset to 0010b. Reset to 0b. Reset to 0b. Reset to 0b (Upstream port). Reset to 1b (Downstream ports). Reset to 000b. Reset to 0b. Reset to 0b. Reset to 0b. Not Support. Page 66 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.80 LINK STATUS REGISTER 2 – OFFSET F0h BIT 16 31:17 7.2.81 FUNCTIO N Slot Capabilities 2 TYPE RO DESCRIPTIO N Reset to 0000_0000h. FUNCTIO N Slot Control 2 TYPE RO DESCRIPTIO N Reset to 0000h. FUNCTIO N Slot Status 2 TYPE RO DESCRIPTIO N Reset to 0000h. PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h BIT 15:0 7.2.85 RO SLOT STATUS REGISTER 2 – OFFSET F8h BIT 31:16 7.2.84 DESCRIPTIO N Reset to 0b (Upstream port). Reset to 1b (Downstream ports). Reset to 0000h. RO SLOT CONTORL REGISTER 2 – OFFSET F8h BIT 15:0 7.2.83 TYPE SLOT CAPABILITIES REGISTER 2 – OFFSET F4h BIT 31:0 7.2.82 FUNCTIO N Current Deemphasis Level Link Status 2 FUNCTIO N Extended Capabilities ID TYPE DESCRIPTIO N Read as 0001h to indicate that these are PCI express extended capability registers for advance error reporting. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. Pointer points to the PCI Express Extended VC capability register. RO 19:16 Capability Version RO 31:20 Next Capability Offset RO Reset to 140h. UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h BIT FUNCTIO N 0 T raining Error Status 3:1 Reserved 4 Data Link Protocol Error Status 11:5 Reserved 12 Poisoned TLP Status RW1CS 13 Flow Control Protocol Error Status RW1CS 14 Completion T imeout Status RW1CS PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RW1CS RsvdP RW1CS RsvdP DESCRIPTIO N When set, indicates that the Training Error event has occurred. Reset to 0b. Not Support. When set, indicates that the Data Link Protocol Error event has occurred. Reset to 0b. Not Support. When set, indicates that a Poisoned TLP has been received or generated. Reset to 0b. When set, indicates that the Flow Control Protocol Error event has occurred. Reset to 0b. When set, indicates that the Completion Timeout event has occurred. Reset to 0b. Page 67 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.86 BIT FUNCTIO N 15 Completer Abort Status TYPE RW1CS 16 Unexpected Completion Status RW1CS 17 Receiver Overflow Status RW1CS 18 Malformed TLP Status RW1CS 19 ECRC Error Status RW1CS 20 Unsupported Request Error Status RW1CS 21 ACS Violation Status RW1CS 31:21 Reserved RsvdP DESCRIPTIO N When set, indicates that the Completer Abort event has occurred. Reset to 0b. When set, indicates that the Unexpected Completion event has occurred. Reset to 0b. When set, indicates that the Receiver Overflow event has occurred. Reset to 0b. When set, indicates that a Malformed TLP has been received. Reset to 0b. When set, indicates that an ECRC Error has been detected. Reset to 0b. When set, indicates that an Unsupported Request event has occurred. Reset to 0b. When set, indicates that an ACS Violation event has occurred Reset to 0b. Not Support. UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h BIT FUNCTIO N TYPE 0 T raining Error Mask RWS 3:1 Reserved RsvdP 4 Data Link Protocol Error Mask RWS 11:5 Reserved RsvdP 12 Poisoned TLP Mask RWS 13 14 15 16 17 18 PI7C9X2G404SL Flow Control Protocol Error Mask RWS Completion T imeout Mask RWS Completer Abort Mask RWS Unexpected Completion Mask RWS Receiver Overflow Mask RWS Malformed TLP Mask RWS Document Number DS40068 Rev 2-2 DESCRIPTIO N When set, the T raining Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Not Support. When set, the Data Link Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Not Support. When set, an event of Poisoned T LP has been received or generated is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Flow Control Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completion T imeout event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completer Abort event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unexpected Completion event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Receiver Overflow event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, an event of Malformed T LP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Page 68 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.87 BIT FUNCTIO N TYPE 19 ECRC Error Mask RWS DESCRIPTIO N When set, an event of ECRC Error has been detected is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unsupported Request event is not logged in the Header Log register and not issued as an Error Message to RC either. 20 Unsupported Request Error Mask RWS 21 31:22 ACS violation mask Reserved RWS RsvdP Reset to 0b. Reset to 0b Not Support. UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch BIT FUNCTIO N TYPE 0 T raining Error Severity RWS 3:1 Reserved RsvdP 4 Data Link Protocol Error Severity RWS 11:5 Reserved RsvdP 12 Poisoned TLP Severity RWS Flow Control Protocol Error Severity RWS Completion T imeout Error Severity RWS Completer Abort Severity RWS Unexpected Completion Severity RWS Receiver Overflow Severity RWS Malformed TLP Severity RWS ECRC Error Severity RWS 13 14 15 16 17 18 19 Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 1b. 0b: Non-Fatal 1b: Fatal Reset to 1b. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal 21 ACS violation severity RWS 31:21 Reserved RsvdP PI7C9X2G404SL Reset to 1b. Not Support. 0b: Non-Fatal 1b: Fatal Reset to 1b. 0b: Non-Fatal 1b: Fatal RWS Document Number DS40068 Rev 2-2 Reset to 1b. Not Support. 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Unsupported Request Error Severity 20 DESCRIPTIO N 0b: Non-Fatal 1b: Fatal Reset to 0b. 0b: Non-Fatal 1b: Fatal Reset to 0b. Not Support. Page 69 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.88 7.2.89 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h BIT FUNCTIO N TYPE 0 Receiver Error Status RW1CS 5:1 Reserved RsvdP 6 Bad T LP Status RW1CS 7 Bad DLLP Status RW1CS 8 REPLAY_NUM Rollover status RW1CS 11:9 Reserved RsvdP 12 Replay T imer T imeout status RW1CS 13 Advisory Non-Fatal Error status RW1CS 31:14 Reserved RsvdP DESCRIPTIO N When set, the Receiver Error event is detected. Reset to 0b. Not Support. When set, the event of Bad T LP has been received is detected. Reset to 0b. When set, the event of Bad DLLP has been received is detected. Reset to 0b. When set, the REPLAY_NUM Rollover event is detected. Reset to 0b. Not Support. When set, the Replay Timer Timeout event is detected. Reset to 0b. When set, the Advisory Non-Fatal Error event is detected. Reset to 0b. Not Support. CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h BIT FUNCTIO N TYPE 0 Receiver Error Mask RWS 5:1 Reserved RsvdP 6 Bad T LP Mask RWS 7 Bad DLLP Mask RWS 8 REPLAY_NUM Rollover Mask RWS 11:9 Reserved RsvdP 12 Replay T imer T imeout Mask RWS 13 Advisory Non-Fatal Error Mask RWS 31:14 Reserved RsvdP PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N When set, the Receiver Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Not Support. When set, the event of Bad T LP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the event of Bad DLLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the REPLAY_NUM Rollover event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Not Support. When set, the Replay Timer Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Advisory Non-Fatal Error event is not logged in the Header Long register and not issued as an Error Message to RC either. Reset to 1b. Not Support. Page 70 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.90 7.2.91 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h BIT FUNCTIO N 4:0 First Error Pointer DESCRIPTIO N It indicates the bit position of the first error reported in the Uncorrectable Error Status register. Reset to 0_0000b. When set, it indicates the Switch has the capability to generate ECRC. ECRC Generation Capable RO 6 ECRC Generation Enable RWS 7 ECRC Check Capable 8 ECRC Check Enable RWS 31:9 Reserved RsvdP Reset to 1b. When set, it enables the generation of ECRC when needed. Reset to 0b. When set, it indicates the Switch has the capability to check ECRC. RO Reset to 1b. When set, the function of checking ECRC is enabled. Reset to 0b. Not Support. HEADER LOG REGISTER – OFFSET From 11Ch to 128h FUNCTIO N 1 st DWORD 2 nd DWORD 3 rd DWORD 4 th DWORD TYPE ROS ROS ROS ROS DESCRIPTIO N Hold the 1st DWORD of TLP Header. T he Head byte is in big endian. Hold the 2nd DWORD of TLP Header. The Head byte is in big endian. Hold the 3rd DWORD of T LP Header. The Head byte is in big endian. Hold the 4th DWORD of TLP Header. The Head byte is in big endian. PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h BIT 15:0 7.2.93 ROS 5 BIT 31:0 63:32 95:64 127:96 7.2.92 TYPE FUNCTIO N Extended Capabilities ID TYPE RO 19:16 Capability Version RO 31:20 Next Capability Offset RO DESCRIPTIO N Read as 0002h to indicate that these are PCI express extended capability registers for virtual channel. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. Pointer points to the PCI Express Power Budgeting Capability register. Reset to 20Ch. PORT VC CAPABILITY REGISTER 1 – OFFSET 144h BIT FUNCTIO N TYPE 2:0 Extended VC Count HwInt RO 3 Reserved 6:4 Low Priority Extended VC Count 7 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 RsvdP RO RsvdP DESCRIPTIO N It indicates the number of extended Virtual Channels in addition to the default VC supported by the Switch. The default value may be changed by the status of strapped pin, or auto-loading from EEPROM. Bit[2:1]: Reset to 00b. Bit[0]: Reset to the status of VC1_EN strapped pin. Not Support. It indicates the number of extended Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group. The default value may be changed by auto-loading from EEPROM. Reset to 000b. Not Support. Page 71 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.94 7.2.95 7.2.96 BIT FUNCTIO N 9:8 Reference Clock 11:10 Port Arbitration T able Entry Size 31:12 Reserved TYPE RO DESCRIPTIO N It indicates the reference clock for Virtual Channels that support time-based WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock. Reset to 00b. Read as 10b to indicate the size of Port Arbitration table entry in the device is 4 bits. RO RsvdP Reset to 10b. Not Support. PORT VC CAPABILITY REGISTER 2 – OFFSET 148h BIT FUNCTIO N 7:0 VC Arbitration Capability 23:8 Reserved 31:24 VC Arbitration T able Offset TYPE RO DESCRIPTIO N It indicates the types of VC Arbitration supported by the device for the LPVC group. T his field is valid when LPVC is greater than 0. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round Robin arbitration with 32 phases in LPVC. Reset to 03h if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. Not Support. It indicates the location of the VC Arbitration Table as an offset from the base address of the Virtual Channel Capability register in the unit of DQWD (16 bytes). RsvdP RO Reset to 03h if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. PORT VC CONTROL REGISTER – OFFSET 14Ch BIT FUNCTIO N TYPE 0 Load VC Arbitration T able RW 3:1 VC Arbitration Select RW 15:4 Reserved DESCRIPTIO N When set, the programmed VC Arbitration Table is applied to the hardware. T his bit always returns 0b when read. Reset to 0b. T his field is used to configure the VC Arbitration by selecting one of the supported VC Arbitration schemes. The valid values for the schemes supported by Switch are 0b and 1b. Other value than these written into this register will be treated as default. Reset to 000b. Not Support. RsvdP PORT VC STATUS REGISTER – OFFSET 14Ch BIT FUNCTIO N 16 VC Arbitration T able Status 31:17 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE RO RsvdP DESCRIPTIO N When set, it indicates that any entry of the VC Arbitration Table is written by software. T his bit is cleared when hardware finishes loading values stored in the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set. Reset to 0b. Not Support. Page 72 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.97 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h BIT FUNCTIO N TYPE 7:0 Port Arbitration Capability 13:8 Reserved 14 Advanced Packet Switching RO 15 Reject Snoop T ransactions RO 22:16 Maximum T ime Slots RO 23 Reserved 31:24 Port Arbitration T able Offset RO RsvdP DESCRIPTIO N It indicates the types of Port Arbitration supported by the VC resource. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin, Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports) and T ime-based WRR with 128 phases (3~4 enabled ports). Note that the T ime-based WRR is only valid in VC1. Reset to 19h. Not Support. When set, it indicates the VC resource only supports transaction optimized for Advanced Packet Switching (AS). Reset to 0b. T his bit is not applied to PCIe Switch. Reset to 0b. It indicates the maximum numbers of time slots (minus one) are allocated for Isochronous traffic. The default value may be changed by auto-loading from EEPROM. RsvdP RO Reset to 7Fh. Not Support. It indicates the location of the Port Arbitration Table (n) as an offset from the base address of the Virtual Channel Capability register in the unit of DQWD (16 bytes). Reset to 04h for Port Arbitration Table (0). 7.2.98 VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h BIT FUNCTIO N TYPE 7:0 T C/VC Map RW 15:8 Reserved 16 Load Port Arbitration T able RW 19:17 Port Arbitration Select RW 23:20 Reserved 26:24 VC ID 30:27 Reserved RsvdP 31 VC Enable RW RsvdP RsvdP RO DESCRIPTIO N T his field indicates the TCs that are mapped to the VC resource. Bit locations within this field correspond to TC values. When the bits in this field are set, it means that the corresponding T Cs are mapped to the VC resource. The default value may be changed by auto-loading from EEPROM. Reset to FFh. Not Support. When set, the programmed Port Arbitration Table is applied to the hardware. T his bit always returns 0b when read. Reset to 0b. T his field is used to configure the Port Arbitration by selecting one of the supported Port Arbitration schemes. The permissible values for the schemes supported by Switch are 000b and 011b at VC0, other value than these written into this register will be treated as default. Reset to 000b. Not Support. T his field assigns a VC ID to the VC resource. Reset to 000b. Not Support. 0b: disables this Virtual Channel 1b: enables this Virtual Channel Reset to 1b. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 73 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 7.2.99 7.2.100 7.2.101 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h BIT 15:0 FUNCTIO N Reserved 16 Port Arbitration T able Status 17 VC Negotiation Pending 31:18 Reserved TYPE RsvdP DESCRIPTIO N Not Support. When set, it indicates that any entry of the Port Arbitration Table is written by software. T his bit is cleared when hardware finishes loading values stored in the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set. RO Reset to 0b. When set, it indicates that the VC resource is still in the process of negotiation. This bit is cleared after the VC negotiation is complete. RO Reset to 0b. Not Support. RsvdP VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch BIT FUNCTIO N 7:0 Port Arbitration Capability TYPE RO 13:8 Reserved 14 Advanced Packet Switching RO 15 Reject Snoop T ransactions RO 22:16 Maximum T ime Slots RO 23 Reserved 31:24 Port Arbitration T able Offset DESCRIPTIO N It indicates the types of Port Arbitration supported by the VC resource. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin, Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports) and T ime-based WRR with 128 phases (3~4 enabled ports). Note that the T ime-based WRR is only valid in VC1. Reset to 19h if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. Not Support. When set, it indicates the VC resource only supports transaction optimized for Advanced Packet Switching (AS). RsvdP Reset to 0b. T his bit is not applied to PCIe Switch. Reset to 0b. It indicates the maximum numbers of time slots (minus one) are allocated for Isochronous traffic. The default value may be changed by auto-loading from EEPROM. Reset to 7Fh if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. Not Support. It indicates the location of the Port Arbitration Table (n) as an offset from the base address of the Virtual Channel Capability register in the unit of DQWD (16 bytes). RsvdP RO Reset to 08h for Port Arbitration Table (1) if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h BIT FUNCTIO N TYPE 7:0 T C/VC Map RW (Exception for bit0) 15:8 Reserved 16 Load Port Arbitration T able PI7C9X2G404SL Document Number DS40068 Rev 2-2 RsvdP RW DESCRIPTIO N T his field indicates the TCs that are mapped to the VC resource. Bit locations within this field correspond to TC values. When the bits in this field are set, it means that the corresponding T Cs are mapped to the VC resource. Bit 0 of this filed is read-only and must be set to “0” for the VC1. T he default value may be changed by auto-loading from EEPROM. Reset to 00h. Not Support. When set, the programmed Port Arbitration Table is applied to the hardware. T his bit always returns 0b when read. Reset to 0b. Page 74 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N TYPE 19:17 Port Arbitration Select 23:20 Reserved 26:24 VC ID 30:27 Reserved RsvdP 31 VC Enable RW DESCRIPTIO N T his field is used to configure the Port Arbitration by selecting one of the supported Port Arbitration schemes. The permissible values for the schemes supported by Switch are 000b, 011b and 100b at VC1, other value than these written into this register will be treated as default. RW Reset to 000b. Not Support. T his field assigns a VC ID to the VC resource. RsvdP RW Reset to 001b if offset 144h.bit[0]=1. Reset to 000b if offset 144h.bit[0]=0. Not Support. 0b: disables this Virtual Channel 1b: enables this Virtual Channel Reset to 0b. 7.2.102 7.2.103 VC RESOURCE STATUS REGISTER (1) – OFFSET 164h BIT 15:0 FUNCTIO N Reserved 16 Port Arbitration T able Status 17 VC Negotiation Pending 31:18 Reserved TYPE RsvdP RO DESCRIPTIO N Not Support. When set, it indicates that any entry of the Port Arbitration Table is written by software. T his bit is cleared when hardware finishes loading values stored in the Port Arbitration Table after the bit of “Load Port Arbitration T able” is set. Reset to 0b. When set, it indicates that the VC resource is still in the process of negotiation. This bit is cleared after the VC negotiation is complete. RO RsvdP Reset to 0b. Not Support. VC ARBITRATION TABLE REGISTER – OFFSET 170h The VC arb itration table is a read-write register array that contains a table for VC arb itration. Each table entry allocates four bits, of which three bits are used to represent VC ID and one bit is reserved. A total of 32 entries are used to construct the VC arbitration table. The layout for this register array is shown below. Table 7-1 Register Array Layout for VC Arbitration 31 - 28 Phase [7] Phase [15] Phase [23] Phase [31] 7.2.104 27 - 24 Phase [6] Phase [14] Phase [22] Phase [30] 23 - 20 Phase [5] Phase [13] Phase [21] Phase [29] 19 - 16 Phase [4] Phase [12] Phase [20] Phase [28] 15 - 12 Phase [3] Phase [11] Phase [19] Phase [27] 11 - 8 Phase [2] Phase [10] Phase [18] Phase [26] 7-4 Phase [1] Phase [9] Phase [17] Phase [25] 3-0 Phase [0] Phase [8] Phase [16] Phase [24] Byte Location 00h 04h 08h 0Ch PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h The Port arb itration table is a read-write register array that contains a table for Port arb itration. Each table entry allocates two bits to represent Port Nu mber. The table entry size is dependent on the number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arb itration table contains 128 entries if three or four ports are to be enabled. The following table shows the register array layout for the size of entry equal to two. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 75 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL Table 7-2 Table Entry Size in 4 Bits 63 - 56 Phase [15:14] Phase [31:30] Phase [47:46] Phase [63:62] Phase [79:78] Phase [95:94] Phase [111:110] Phase [127:126] 7.2.105 15:0 7.2.107 47 - 40 Phase [11:10] Phase [27:26] Phase [43:42] Phase [59:58] Phase [75:74] Phase [91:90] Phase [107:106] Phase [123:122] 39 - 32 Phase [9:8] Phase [25:24] Phase [41:40] Phase [57:56] Phase [73:72] Phase [89:88] Phase [105:104] Phase [121:120] 31 - 24 Phase [7:6] Phase [23:22] Phase [39:38] Phase [55:54] Phase [71:70] Phase [87:86] Phase [103:102] Phase [119:118] 23 - 16 Phase [5:4] Phase [21:20] Phase [37:36] Phase [53:52] Phase [69:68] Phase [85:84] Phase [101:100] Phase [117:116] 15 - 8 Phase [3:2] Phase [19:18] Phase [35:34] Phase [51:50] Phase [67:66] Phase [83:82] Phase [99:98] Phase [115:114] 7-0 Phase [1:0] Phase [17:16] Phase [33:32] Phase [49:48] Phase [65:64] Phase [81:80] Phase [97:96] Phase [113:112] Byte Location 00h 08h 10h 18h 20h 28h 30h 38h PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch BIT 7.2.106 55 - 48 Phase [13:12] Phase [29:28] Phase [45:44] Phase [61:60] Phase [77:76] Phase [93:92] Phase [109:108] Phase [125:124] FUNCTIO N Extended Capabilities ID TYPE RO 19:16 Capability Version RO 31:20 Next Capability Offset RO DESCRIPTIO N Read as 0004h to indicate that these are PCI express extended capability registers for power budgeting. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. Pointer points to the PCI Express Extended ACS capability register/LTR capability register. Reset to 230h (Upstream port). Reset to 220h (Downstream ports). DATA SELECT REGISTER – OFFSET 210h BIT FUNCTIO N TYPE 7:0 Data Selection RW 31:8 Reserved DESCRIPTIO N It indexes the power budgeting data reported through the data register. When 00h, it selects D0 Max power budget When 01h, it selects D0 Sustained power budget Other values would return zero power budgets, which means not supported Reset to 00h. Not Support. RsvdP POWER BUDGETING DATA REGISTER – OFFSET 214h BIT FUNCTIO N 7:0 Base Power 9:8 PI7C9X2G404SL Data Scale Document Number DS40068 Rev 2-2 TYPE RO RO DESCRIPTIO N It specifies the base power value in watts. This value represents the required power budget in the given operation condition. T he default value may be changed by auto-loading from EEPROM. Reset to 04h. It specifies the scale to apply to the base power value. Reset to 00b. Page 76 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N TYPE 12:10 PM Sub State RO 14:13 17:15 7.2.108 7.2.109 T ype 20:18 Power Rail 31:21 Reserved Reset to 000b. It specifies the power management state of the given operation condition. It defaults to the D0 power state. RO Reset to 00b. It specifies the type of the given operation condition. It defaults to the Maximum power state. RO Reset to 111b. It specifies the power rail of the given operation condition. RO RsvdP Reset to 010b. Not Support. POWER BUDGET CAPABILITY REGISTER – OFFSET 218h BIT FUNCTIO N 0 System Allocated 31:1 Reserved TYPE RO RsvdP DESCRIPTIO N When set, it indicates that the power budget for the device is included within the system power budget. The default value may be changed by auto-loading from EEPROM. Reset to 0b. Not Support. ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only) BIT 15:0 7.2.110 PM State DESCRIPTIO N It specifies the power management sub state of the given operation condition. It is initialized to the default sub state. FUNCTIO N PCI Express Extended Capability ID TYPE RO 19:16 Capability Version RO 31:20 Next Capability ID RO DESCRIPTIO N Read as 000Dh to indicate PCI Express Extended Capability ID for ACS Extended Capability. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. Read as 000h. No other ECP registers. ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only) BIT FUNCTIO N TYPE 0 ACS Source Validation RO 1 ACS T ranslation Blocking RO 2 ACS P2P Request Redirect RO 3 ACS P2P Completion Redirect RO 4 ACS Upstream Forwarding RO 5 ACS P2P Egress control RO PI7C9X2G404SL Document Number DS40068 Rev 2-2 DESCRIPTIO N Indicated the implements of ACS Source Validation. Reset to 1b. Indicated the implements of ACS T ranslation Blocking. Reset to 1b. Indicated the implements of ACS P2P Request Redirect. Reset to 1b. Indicated the implements of ACS P2P Completion Redirect. Reset to 1b. Indicated the implements of ACS Upstream Forwarding. Reset to 1b. Indicated the implements of ACS P2P Egress control. Reset to 1 b. Page 77 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT FUNCTIO N 6 ACS Direct T ranslated P2P 7 Reserved 15:8 Egress Control Vector Size RO 16 ACS Source Validation Enable RW 17 ACS T ranslation Blocking Enable RW 18 ACS P2P Request Redirect RW 19 ACS P2P Completion Redirect Enable RW 20 ACS Upstream Forwarding Enable RW 21 ACS P2P Egress control Enable RW 22 31:23 7.2.111 7.2.112 RO RsvdP DESCRIPTIO N Indicated the implements of ACS Direct Translated P2P. Reset to 1b. Not Support. Encodings 01h –FFh directly indicate the number of applicable bits in the Egress Control Vector. Reset to 08h. Enable the source validation. Reset to 0b. Enable ACS T ranslation Blocking. Reset to 0b. Enable ACS P2P Request Redirect. Reset to 0b. Enable ACS P2P Completion Redirect Reset to 0b. Enable ACS Upstream Forwarding. Reset to 0b. Enable ACS P2P Egress control. Reset to 0b. Enable ACS Direct T ranslated P2P. RW RsvdP Reset to 0b. Not Support. EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port Only) BIT FUNCTIO N 7:0 Egress Control Vector 31:8 Reserved TYPE RW RsvdP DESCRIPTIO N When a given bit is set, peer-to-peer requests targeting the associated Port are blocked or redirected. Reset to 00h. Not Support. LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only) BIT 15:0 7.2.113 ACS Direct T ranslated P2P Enable Reserved TYPE FUNCTIO N PCI Express Extended Capability ID TYPE RO 19:16 Capability Version RO 31:20 Next Capability ID RO DESCRIPTIO N Read as 0018h to indicate PCI Express Extended Capability ID for LTR Extended Capability. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number. Read as 000h. No other ECP registers. MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) BIT FUNCTIO N 9:0 Max Snoop Latency Value RW 12:10 Max Snoop Latency Scale RW PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE DESCRIPTIO N .Specifies the maximum snoop latency that a device is permitted to request Reset to 000h. T his register provides a scale for the value contained within the Maximum Snoop Latency Value field Reset to 000b Page 78 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL BIT 15:13 7.2.114 FUNCTIO N Reserved TYPE RsvdP DESCRIPTIO N Not Support. MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) BIT FUNCTIO N 25:16 Max No-Snoop Latency Value RW 28:26 Max No-Snoop Latency Scale RW 31:29 Reserved PI7C9X2G404SL Document Number DS40068 Rev 2-2 TYPE DESCRIPTIO N .Specifies the maximum no-snoop latency that a device is permitted to request Reset to 000h. T his register provides a scale for the value contained within the Maximum No-Snoop Latency Value field RsvdP Reset to 000b Not Support. Page 79 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 8 CLOCK SCHEME The built-in Integrated Reference Clock Buffer of the PI7C9X2G404SL supports three reference clock outputs. The clock buffer feature can be enabled and disabled by strapping the CLKBUF_PD pin. When CLKBUF_PD p in is asserted low, the clock buffer is enabled. The clock buffer distributes a single 100M Hz reference clock input to three Reference Clock Output Pairs, REFCLKO_P[3:0] and REFCLKO_N[3:0]. The clock buffer requires 100MHz differential clock inputs through REFCLKI_P and REFCLKI_N Pins as show in the following table. When CLKBUF_PD p in is asserted high, the clock buffer is in power down mode and disabled. The 100M Hz Reference Clock Output Pairs are disabled, and The PI7C9X2G404SL requires 100M Hz d ifferential clock inputs through REFCLKP and REFCLKN Pins as shown in the following table. Table 8-1 AC Switching Characteristics Symbol Parameters Min. Typ. Max. Unit FIN Reference Clock Frequency 100 MHz T rise/ T fall 1 Rise and Fall T ime in 20-80% 175 700 ps DT rise/ DT fall 1 Rise and Fall T ime Variation 125 ps T pd Propagation Delay 2.5 6.5 ns Vswing 1 Voltage including overshoot 550 1150 mV 2 T DC Duty Cycle 45 55 % Note : 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3.In general rule, use ac-coupling when differential input >500mV; use dc-coupling when differential input 1.5 MHz T X RMS jitter < 1.5 MHz Symbol VTX-DE-RATIO-3.5dB VTX-DE-RATIO-6dB T TX-EYE T TX-HF-DJ-DD T TX-LF-RMS Min -3.0 -5.5 0.75 - Typ - Max -4.0 -6.5 0.15 3.0 T ransmitter rise and fall time T X rise/fall mismatch Maximum T X PLL Bandwidth Minimum T X PLL BW for 3dB peaking T X PLL peaking with 8 MHz min BW DC Differential TX Impedance T ransmitter Short-Circuit Current Limit T X DC Common Mode Voltage Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle Absolute Delta of DC Common Mode Voltage between D+ and D– Electrical Idle Differential Peak Output Voltage DC Electrical Idle Differential Output Voltage T he Amount of Voltage Change Allowed During Receiver Detection Lane-to-Lane Output Skew T TX-RISE-FALL T RF-MISMATCH BW TX-PLL BW TX-PLL-LO-3DB PKGTX-PLL1 ZTX-DIFF-DC I TX-SHORT VTX-DC-CM VTX-CM-DC-ACTIVE-IDLE- 0.15 8 80 0 0 - 0.1 16 3.0 120 90 3.6 100 Unit dB dB UI UI Ps RMS UI UI MHz MHz dB Ω mA V mV VTX-CM-DC-LINE-DELTA 0 - 25 mV VTX-IDLE-DIFF-AC-p 0 - 20 mV VTX-IDLE-DIFF-DC 0 - 5 mV VTX-RCV-DETECT - - 600 mV LTX-SKEW - - 500 ps + 4 UI ps DELTA Table 12-4 PCI Express Interface - Differential Transmitter (TX) Output (2.5 Gbps) Characteristics Parameter Unit Interval Differential p-p TX voltage swing Symbol UI VTX-DIFF-P-P Min 399.88 800 Typ 400.0 - Max 400.12 - Low power differential p-p TX voltage swing T X de-emphasis level ratio Minimum T X eye width Maximum time between the jitter median and max deviation from the median T ransmitter rise and fall time Maximum T X PLL Bandwidth Maximum T X PLL BW for 3dB peaking Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle Absolute Delta of DC Common Mode Voltage between D+ and D– Electrical Idle Differential Peak Output Voltage T he Amount of Voltage Change Allowed During Receiver Detection T ransmitter DC Common Mode Voltage T ransmitter Short-Circuit Current Limit DC Differential TX Impedance Lane-to-Lane Output Skew VTX-DIFF-P-P-LOW 400 - - VTX-DE-RATIO T TX-EYE T TX-EYE-MEDIAN-to-MAX- -3.0 0.75 - - -4.0 0.125 Unit ps mV ppd mV ppd dB UI UI 0.125 1.5 0 - 22 100 UI MHz MHz mV VTX-CM-DC-LINE-DELTA 0 - 25 mV VTX-IDLE-DIFF-AC-p 0 - 20 mV VTX-RCV-DETECT - - 600 mV VTX-DC-CM I TX-SHORT ZTX-DIFF-DC LTX-SKEW 0 80 - 100 - 3.6 90 120 500 ps + 2 UI V mA Ω ps JITTER T TX-RISE-FALL BW TX-PLL BW TX-PLL-LO-3DB VTX-CM-DC-ACTIVE-IDLEDELTA Table 12-5 PCI Express Interface - Differential Receiver (RX) Input (5.0 Gbps) Characteristics Parameter Unit Interval Differential RX Peak-to-Peak Voltage T otal jitter tolerance Receiver DC common mode impedance RX AC Common Mode Voltage Electrical Idle Detect Threshold PI7C9X2G404SL Document Number DS40068 Rev 2-2 Symbol UI VRX-DIFF-PP-CC T JRX ZRX-DC VRX-CM-AC-P VRX-IDLE-DET-DIFFp-p Page 87 of 90 Min 199.94 120 0.68 40 65 www.diodes.com Typ 200.0 - Max 200.06 1200 60 150 175 Unit ps mV UI Ω mV mV September 2017 © Diodes Incorporated PI7C9X2G404SL Table 12-6 PCI Express Interface - Differential Receiver (RX) Input (2.5 Gbps) Characteristics Parameter Unit Interval Differential RX Peak-to-Peak Voltage Receiver eye time opening Maximum time delta between median and deviation from median Receiver DC common mode impedance DC differential impedance RX AC Common Mode Voltage DC input CM input impedance during reset or power down Electrical Idle Detect Threshold Lane to Lane skew Symbol UI VRX-DIFF-PP-CC T RX-EYE T RX-EYE-MEDIAN-to-MAX- Min 399.88 175 0.4 - Typ 400.0 - Max 400.12 1200 0.3 Unit ps mV UI UI ZRX-DC ZRX-DIFF-DC VRX-CM-AC-P ZRX-HIGH-IMP-DC 40 80 200 - 60 120 150 - Ω Ω mV kΩ VRX-IDLE-DET-DIFFp-p LRX-SKEW 65 - - 175 20 mV ns JITTER 12.4 OPERATING AMBIENT TEMPERATURE Table 12-7 Operating Ambient Temperature (Above which the useful life may be impaired.) Ite m Min. Max. Ambient T emperature with power applied -40 85 Note : Exposure to high temperature conditions for extended periods of time may affect reliability. Units o C 12.5 POWER CONSUMPTION Table 12-8 Power Consumption Active Lane pe r Port 1.0VDDC Typ 3.3AVDDH Max 123.20 327.91 2.20 2.42 144.10 346.06 35.31 1/1/1/1, ec 123.20 327.91 2.20 2.42 144.10 346.06 35.31 1 Max 1.0AVDD Typ 1/1/1/1 Typ 1.0VAUX Max Typ Max 3.3VDDR Typ Total Max 38.84 319.44 351.38 0.03 0.03 624.28 1,066.65 mW 38.84 0.03 0.03 311.44 722.52 7.26 Typ Max Unit Typ 6.60 Max 3.3VAUX mW Note : 1 : Use external clock buffer, Disable internal clock buffer. T est Conditions: - T ypical power measured under the conditions of 1.0V/ 3.3V power rail without device usage on all downstream ports. - Maximum power measured under the conditions of 1.1V/ 3.63V with PCIe2 devices usage on all downstream ports. - Ambient T emperature at 25o C - Power consumption in the table is a reference, be affected by various environments, bus traffic and power supply etc. PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 88 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 13 PACKAGE INFORMATION The package of PI7C9X2G404SL is a 14mm x 14mm LQFP (128 Pin) package. The fo llowing are the package information and mechanical dimension: Figure 13-1 Package outline drawing PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 89 of 90 www.diodes.com September 2017 © Diodes Incorporated PI7C9X2G404SL 14 ORDERING INFORMATION Part Number PI7C9X2G404SL□FDEX Temperature Range -40o to 85o C (Industrial Temperature) PI 7C 9X2G404SL Package 128-pin LQFP 14mm x 14mm Pb-Free & Green Yes FD E X Tape & Reel Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family Pericom PI7C9X2G404SL Document Number DS40068 Rev 2-2 Page 90 of 90 www.diodes.com September 2017 © Diodes Incorporated