PI7C9X2G606PR
PCI EXPRESS GEN 2 PACKET SWITCH
6Port-6Lane PCI Express Gen 2 Switch
Green Package Family
DATASHEET
REVISION 8
August 2022
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet: http://www.pericom.com
Document Number DS40209 Rev 8-2
PI7C9X2G606PR
IMPORTANT NOTICE
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WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
2.
The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products
described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any
product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’
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products
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DIODES is a trademark of Diodes Incorporated in the United States and other countries.
The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries.
© 2022 Diodes Incorporated. All Rights Reserved.
www.diodes.com
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 2 of 112
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PI7C9X2G606PR
REVISION HISTORY
Date
12/31/2013
Revision Number
0.1
07/21/2014
0.2
07/29/2014
0.3
09/26/2014
0.4
10/15/2014
1.0
10/21/2014
1.1
11/13/2014
1.2
12/10/2014
1.3
8/24/2015
1.3
09/15/2015
1.4
12/18/2015
1.5
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Description
Preliminary Datasheet
Updated Section 3 Pin Description
Updated Section 4 Pin Assignments
Updated Section 6.1.3 EEPROM Space Address Map
Updated Section 6.1.4 Mapping EEPROM Contents to Configuration Registers
Updated Section 7.2 Transparent Mode Configuration Registers
Updated Section 1 Features
Update Section 5.1 Physical Layer Circuit
Added Section 6.2.1 SMBus Operation
Added Section 6.2.2 SMBus Commands Supported
Added Section 6.3 I2C Slave Interface
Added Section 8 Clock Sheme
Updated Section 1 Feature
Updated Section 3.4 Miscellaneous Signals
Updated Section 4.1 Pin List of 196-Pin LBGA
Updated Section 6 EEPROM Interface & System Management BUS/ I2C BUS
Updated Section 6.1.4 Mapping EEPROM Contents to Configuration Registers
Updated Section 6.2 SMBus Interface
Updated Section 7 Register Description
Remove “Preliminary”
Updated Section 6.2 SMBUS Interface
Updated Section 6.3 I2C Slave Interface
Updated Section 7.2 Transparent Mode Configuration Registers
Updated Section 3.4 Miscellaneous Signals
Updated Section 6.1 EEPROM Interface
Updated Section 6.2 SMBUS Interface
Updated Section 6.3 I2C Slave Interface
Updated Section 7.2 Transparent Mode Configuration Registers
Updated Section 8 Clock Scheme
Added Section 5 Mode Selection and Port-lane Mapping
Updated Section 1 Features
Updated Section 3.1 PCI Express Interface Signals (31 BALLS)
Updated Section 3.2 Port Specific Signals (10 BALLS)
Updated Section 3.4 Miscellaneous Signals (71 BALLS)
Updated Section 4.1 PIN LIST of 196-Pin LBGA
Updated Figure 4 1 PI7C9X2G606PR Ball Assignment
Updated Section 7.1 EEPROM Interface
Updated Section 7.2 SMBus Interface
Updated Section 8.2 Transparent Mode Configuration Registers
Updated Section 9 Clock Scheme
Updated Section 3.2 Port Specific Signals (10 Balls)
Update Section 5.1 Physical Layer Circuit
Updated Section 6.1 EEPROM Interface
Updated Section 7.2.5 REVISION ID REGISTER
Updated Section 8 Clock Scheme
Updated Section 10.2 DC Specifications
Updated Table 11-1 Absolute Maximum Ratings
Updated Section 3 Pin Description
Updated Table 7-5 SMBUS Block Write Portion
Updated Figurate 7-11/7-13 I2C Read Command Packet
Updated Section 8.2.48 XPIP_CSR0 Register
Updated Section 8.2.59 XPIP_CSR5 Register
Updated Section 8.2.60 TL_CSR Register
Updated Section 8.2.77 PCI Express Capabilities Register
Updated Section 8.2.84 Slot Capabilities Register
Updated Section 8.2.109 Port VC Capability Register 1
Updated Section 8.2.144 Power Saving Disable Register
Updated Table 11-1 Absolution Maximum Ratings
Page 3 of 112
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August 2022
© 2022 Copyright Diodes Incorporated. All Rights Reserved.
PI7C9X2G606PR
Date
Revision Number
03/03/2016
04/07/2016
1.6
1.7
08/25/2016
1.8
09/19/2017
2-2
01/12/2018
3
08/14/2019
4
10/25/2019
5
03/26/2020
6
12/11/2020
7
08/17/2022
8
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Description
Updated Table 11-2 DC Electrical Characteristics
Added Section 11 Power Sequence
Updated Section 3.4 MISCELLANEOUS SIGNALS (71 BALLS)
Updated Section 1 Features
Updated Section 3-2 Port Specific Signals (19 balls)
Updated Section 5-3 Port-Lane Mapping
Updated Section 8.2.17 Memory Base Address Register – OFFSET 20h
Updated Section 8.2.59 XPIP_CSR5 – OFFSET 88h
Updated Section 8.2.63 Operation Mode – OFFSET 98h
Updated Section 8.2.81 Link Capabilities Register – OFFSET CCh
Updated Section 8.2.83 Link Status Register – OFFSET D0h
Updated Section 8.2.140 SMBUS Control Register – OFFSET 344h (Upstream Port Only)
Updated Section 3.2 Port Specific Signals (10 Balls)
Updated Section 3.3 EEPROM and SMBUS/I2C Signals (6 balls)
Updated Section 7.1.4 Mapping EEPROM Contents to Configuration Registers
U[dated Section 8.2 Transparent Mode Configuration Registers
Updated Section 12.1 Absolute Maximum Ratings
Updated Table 12 2 DC Electrical Characteristics
Added Section 12.4 Operating Ambient Temperature
Added Table 12.8 Power Consumption
Added Section 13 Thermal Data
Updated Section 14 Package Information
Updated Section 15 Ordering Information
Revision numbering system changed to whole number
Updated Section 6.7 Transaction Ordering
Updated Section 7 EEPROM Interface and System Management/I2C Bus
Updated Section 8.2 TRANSPARENT MODE CONFIGURATION REGISTERS
Updated Section Table 9-1 DC Electrical Characteristics
Updated Section Table 12-1 Absolute Maximum Ratings
Updated Section 15 Ordering Information
Added Figure 14-2 Part Marking
Updated Section 1 Features
Updated Section 7.1.1 Auto Mode EEPROM Access
Updated Section 7.1.2 EEPROM Normal Mode At Reset
Updated Section 10 POWER MANAGEMENT
Updated Section 12.1 Absolute Maximum Ratings
Updated Section 1 Features
Updated Section 15 Ordering Information
Updated Figure 14-2 Part Marking
Updated Section 15 Ordering Information
Updated Section 6.1 Physical Layer Circuit
For Datasheet Status Change
Updated Section 8.2.57 OPERATION MODE – OFFSET 98h
Updated Section 9 Clock Scheme
Updated Section 15 Ordering Information
Updated Section 8.2.54 TL_CSR – OFFSET 8Ch
Page 4 of 112
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PI7C9X2G606PR
TABLE OF CONTENTS
1
FEATURES .................................................................................................................................................................... 11
2
GENERAL DESCRIPTION ......................................................................................................................................... 12
3
PIN DESCRIPTION...................................................................................................................................................... 13
3.1
3.2
3.3
3.4
3.5
4
PIN ASSIGNMENTS .................................................................................................................................................... 17
4.1
5
PIN LIST OF 196-PIN LBGA ..................................................................................................................................... 17
MODE SELECTION AND PORT-LANE MAPPING............................................................................................... 19
5.1
5.2
5.3
6
PCI EXPRESS INTERFACE SIGNALS (31 BALLS) .............................................................................................. 13
PORT SPECIFIC SIGNALS (10 BALLS) ................................................................................................................. 13
EEPROM AND SMBUS/I2C SIGNALS (9 BALLS) .................................................................................................. 14
MISCELLANEOUS SIGNALS (71 BALLS) ............................................................................................................ 14
POWER PINS (75 BALLS) ....................................................................................................................................... 15
MODE SELECTION ................................................................................................................................................. 19
LANE MAPPING ...................................................................................................................................................... 19
PORT-LANE MAPPING........................................................................................................................................... 19
FUNCTIONAL DESCRIPTION .................................................................................................................................. 20
6.1
PHYSICAL LAYER CIRCUIT ................................................................................................................................. 20
6.1.1
RECEIVER DETECTION ............................................................................................................................... 20
6.1.2
RECEIVER SIGNAL DETECTION ................................................................................................................. 20
6.1.3
RECEIVER EQUALIZATION ......................................................................................................................... 21
6.1.4
TRANSMITTER SWING.................................................................................................................................. 21
6.1.5
DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS ................................................................................ 21
6.1.5.1
6.1.5.2
DRIVE AMPLITUDE ..................................................................................................................................................... 22
DRIVE DE-EMPHASIS .................................................................................................................................................. 23
6.1.6
TRANSMITTER ELECTRICAL IDLE LATENCY ........................................................................................... 23
6.2
DATA LINK LAYER (DLL) ..................................................................................................................................... 23
6.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ............................................................. 24
6.4
ROUTING ................................................................................................................................................................. 24
6.5
TC/VC MAPPING ..................................................................................................................................................... 24
6.6
QUEUE ...................................................................................................................................................................... 24
6.6.1
PH ................................................................................................................................................................... 25
6.6.2
PD ................................................................................................................................................................... 25
6.6.3
NPHD ............................................................................................................................................................. 25
6.6.4
CPLH .............................................................................................................................................................. 25
6.6.5
CPLD .............................................................................................................................................................. 25
6.7
TRANSACTION ORDERING .................................................................................................................................. 25
6.8
PORT ARBITRATION ............................................................................................................................................. 26
6.9
VC ARBITRATION .................................................................................................................................................. 26
6.10 FLOW CONTROL .................................................................................................................................................... 26
6.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................................ 27
7
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS/I2C BUS ............................................................ 28
7.1
EEPROM INTERFACE............................................................................................................................................. 28
7.1.1
AUTO MODE EEPROM ACCESS.................................................................................................................. 28
7.1.2
EEPROM NORMAL MODE AT RESET ......................................................................................................... 28
7.1.3
EEPROM SPACE ADDRESS MAP ................................................................................................................ 28
7.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ...................................................... 31
7.2
SMBUS INTERFACE ............................................................................................................................................... 44
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 5 of 112
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PI7C9X2G606PR
7.2.1
SMBUS BLOCK WRITE ................................................................................................................................. 46
7.2.2
SMBUS BLOCK READ ................................................................................................................................... 48
7.2.3
CSR READ, USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL ........................................ 50
7.3
I2C SLAVE INTERFACE .......................................................................................................................................... 51
7.3.1
I2C REGISTER WRITE ACCESS .................................................................................................................... 51
7.3.2
I2C REGISTER READ ACCESS ...................................................................................................................... 54
8
REGISTER DESCRIPTION ........................................................................................................................................ 57
8.1
REGISTER TYPES ................................................................................................................................................... 57
8.2
TRANSPARENT MODE CONFIGURATION REGISTERS ................................................................................... 57
8.2.1
VENDOR ID REGISTER – OFFSET 00h ....................................................................................................... 59
8.2.2
DEVICE ID REGISTER – OFFSET 00h......................................................................................................... 59
8.2.3
COMMAND REGISTER – OFFSET 04h ........................................................................................................ 59
8.2.4
PRIMARY STATUS REGISTER – OFFSET 04h ............................................................................................. 60
8.2.5
REVISION ID REGISTER – OFFSET 08h ..................................................................................................... 61
8.2.6
CLASS CODE REGISTER – OFFSET 08h ..................................................................................................... 61
8.2.7
CACHE LINE REGISTER – OFFSET 0Ch ..................................................................................................... 61
8.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ............................................................................ 61
8.2.9
HEADER TYPE REGISTER – OFFSET 0Ch.................................................................................................. 61
8.2.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h .................................................................................. 62
8.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ............................................................................ 62
8.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 62
8.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ....................................................................... 62
8.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch .......................................................................................... 62
8.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ......................................................................................... 62
8.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch ...................................................................................... 63
8.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ............................................................................... 63
8.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .............................................................................. 63
8.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ................................................. 64
8.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ................................................ 64
8.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ..................... 64
8.2.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ................... 64
8.2.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ............................................................... 64
8.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.............................................................. 65
8.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h ..................................................................................... 65
8.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch ............................................................................................. 65
8.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch ............................................................................................... 65
8.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch .......................................................................................... 65
8.2.29
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ............................................................ 66
8.2.30
POWER MANAGEMENT DATA REGISTER – OFFSET 44h ........................................................................ 66
8.2.31
PPB SUPPORT EXTENSIONS – OFFSET 44h.............................................................................................. 67
8.2.32
DATA REGISTER – OFFSET 44h .................................................................................................................. 67
8.2.33
MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only) ..................................................... 67
8.2.34
MESSAGE CONTROL REGISTER – OFFSET 4Ch (Downstream Port Only) .............................................. 67
8.2.35
MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) ................................................ 68
8.2.36
MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) .................................. 68
8.2.37
MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ....................................................... 68
8.2.38
VPD CAPABILITY ID REGISTER – OFFSET 5Ch (Upstream Port Only) .................................................... 68
8.2.39
VPD REGISTER – OFFSET 5Ch (Upstream Port Only)................................................................................ 68
8.2.40
VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ..................................................................... 69
8.2.41
VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h.................................................................... 69
8.2.42
XPIP_CSR0 – OFFSET 68h (Test Purpose Only) .......................................................................................... 69
8.2.43
XPIP_CSR1 – OFFSET 6Ch (Test Purpose Only).......................................................................................... 69
8.2.44
REPLAY TIME-OUT COUNTER – OFFSET 70h .......................................................................................... 70
8.2.45
ACKNOWLEDGE LATENCY TIMER – OFFSET 70h ................................................................................... 70
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 6 of 112
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PI7C9X2G606PR
8.2.46
8.2.47
8.2.48
8.2.49
8.2.50
8.2.51
8.2.52
8.2.53
8.2.54
8.2.55
8.2.56
8.2.57
8.2.58
8.2.59
8.2.60
8.2.61
8.2.62
8.2.63
8.2.64
8.2.65
8.2.66
8.2.67
8.2.68
8.2.69
8.2.70
8.2.71
8.2.72
8.2.73
8.2.74
8.2.75
8.2.76
8.2.77
8.2.78
8.2.79
8.2.80
8.2.81
8.2.82
8.2.83
8.2.84
8.2.85
8.2.86
8.2.87
8.2.88
8.2.89
8.2.90
8.2.91
8.2.92
8.2.93
8.2.94
8.2.95
8.2.96
8.2.97
8.2.98
8.2.99
8.2.100
SWITCH OPERATION MODE – OFFSET 74h (Upstream Port Only).......................................................... 70
SWITCH OPERATION MODE – OFFSET 74h (Downstream Port Only) ..................................................... 71
XPIP_CSR2 – OFFSET 78h ........................................................................................................................... 71
PHY PARAMETER 1 – OFFSET 78h (Upstream Port Only) ......................................................................... 72
PHY PARAMETER 2 – OFFSET 7Ch ............................................................................................................ 72
XPIP_CSR3 – OFFSET 80h ........................................................................................................................... 73
XPIP_CSR4 – OFFSET 84h (Upstream Port Only) ....................................................................................... 73
XPIP_CSR5 – OFFSET 88h ........................................................................................................................... 73
TL_CSR – OFFSET 8Ch ................................................................................................................................. 74
PHY PARAMETER 3 – OFFSET 90h ............................................................................................................. 75
PHY PARAMETER 4 - OFFSET 94h (Upstream Port Only) .......................................................................... 75
OPERATION MODE – OFFSET 98h ............................................................................................................. 75
DEVICE SPECIFIC POWER MANAGEMENT EVENT– OFFSET 9Ch (Downstream Port Only) ............... 76
EEPROM CONTROL REGISTER – OFFSET A0h (Upstream Port Only) ..................................................... 76
EEPROM ADDRESS REGISTER – OFFSET A4h (Upstream Port Only) ...................................................... 77
EEPROM DATA REGISTER – OFFSET A4h (Upstream Port Only) ............................................................. 77
DEBUGOUT CONTROL REGISTER – OFFSET A8h (Upstream Port Only) ............................................... 77
DEBUGOUT DATA REGISTER – OFFSET ACh (Upstream Port Only)....................................................... 78
SSID/SSVID CAPABILITY REGISTER – OFFSET B0h ................................................................................. 78
SUBSYSTEM VENDOR ID REGISTER – OFFSET B4h ................................................................................ 78
SUBSYSTEM ID REGISTER – OFFSET B4h ................................................................................................. 78
GPIO CONTROL REGISTER – OFFSET B8h (Upstream Port Only) ........................................................... 78
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET C0h ........................................................................ 80
DEVICE CAPABILITIES REGISTER – OFFSET C4h ................................................................................... 80
DEVICE CONTROL REGISTER – OFFSET C8h .......................................................................................... 81
DEVICE STATUS REGISTER – OFFSET C8h............................................................................................... 82
LINK CAPABILITIES REGISTER – OFFSET CCh ........................................................................................ 82
LINK CONTROL REGISTER – OFFSET D0h ............................................................................................... 84
LINK STATUS REGISTER – OFFSET D0h.................................................................................................... 84
SLOT CAPABILITIES REGISTER – OFFSET D4h (Downstream Port Only) ............................................... 85
SLOT CONTROL REGISTER – OFFSET D8h (Downstream Port Only) ...................................................... 86
SLOT STATUS REGISTER – OFFSET D8h (Downstream Port Only) .......................................................... 87
DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h ................................................................................ 87
DEVICE CONTROL REGISTER 2 – OFFSET E8h........................................................................................ 88
DEVIDE STATUS REGISTER 2 – OFFSET E8h............................................................................................ 88
LINK CAPABILITIES REGISTER 2 – OFFSET ECh ..................................................................................... 88
LINK CONTROL REGISTER 2 – OFFSET F0h ............................................................................................. 88
LINK STATUS REGISTER 2 – OFFSET F0h ................................................................................................. 88
SLOT CAPABILITIES REGISTER 2 – OFFSET F4h ..................................................................................... 89
SLOT CONTORL REGISTER 2 – OFFSET F8h ............................................................................................ 89
SLOT STATUS REGISTER 2 – OFFSET F8h................................................................................................. 89
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h .................. 89
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ............................................................. 89
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ................................................................ 90
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ......................................................... 91
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h.................................................................. 92
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ..................................................................... 92
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h..................................... 93
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .......................................................................... 93
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h ........................................ 93
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h ................................................................................ 93
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h ................................................................................ 94
PORT VC CONTROL REGISTER – OFFSET 14Ch ...................................................................................... 94
PORT VC STATUS REGISTER – OFFSET 14Ch ........................................................................................... 94
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h .................................................................... 94
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 7 of 112
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PI7C9X2G606PR
8.2.101
8.2.102
8.2.103
8.2.104
8.2.105
8.2.106
8.2.107
8.2.108
8.2.109
8.2.110
8.2.111
8.2.112
8.2.113
8.2.114
8.2.115
8.2.116
8.2.117
8.2.118
8.2.119
8.2.120
8.2.121
8.2.122
8.2.123
8.2.124
8.2.125
8.2.126
8.2.127
8.2.128
8.2.129
8.2.130
9
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h ....................................................................... 95
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h............................................................................ 95
VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch ................................................................... 96
VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h ....................................................................... 96
VC RESOURCE STATUS REGISTER (1) – OFFSET 164h............................................................................ 97
VC ARBITRATION TABLE REGISTER – OFFSET 170h............................................................................... 97
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ....................................... 97
PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch ..................................... 98
DATA SELECT REGISTER – OFFSET 210h ................................................................................................. 98
POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................................... 98
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................................... 99
ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only) ................................. 99
ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only) .................................................... 99
EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port Only) ................................................. 100
LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only) .................................... 100
MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) ............................................ 100
MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) ..................................... 100
LI PM SUBSTATES EXTENDED CAPABILITY HEADER – OFFSET 240h ............................................... 101
L1 PM SUBSTATES CAPABILITY REGISTER – OFFSET 244h ................................................................. 101
L1 PM SUBSTATES CONTROL 1 REGISTER – OFFSET 248h .................................................................. 101
L1 PM SUBSTATES CONTROL 2 REGISTER – OFFSET 24Ch ................................................................. 101
LTSSM_CSR REGISTER – OFFSET 33Ch................................................................................................... 102
HOTPLUG_CSR REGISTER – OFFSET 340h ............................................................................................. 102
MAC_CSR1 REGISTER – OFFSET 340h..................................................................................................... 102
SMBUS CONTROL REGISTER – OFFSET 344h (Upstream Port Only)..................................................... 102
CPLD FLOW CONTRL ENABLE REGISTER– OFFSET 350h (Upstream Port Only) ............................... 102
CPLD FLOW CONTROL THRESHOLD RGISTER – OFFSET 354h (Upstream Port Only) ...................... 103
CPLD FLOW CONTROL THRESHOLD RGISTER – OFFSET 358h (Upstream Port Only) ...................... 103
POWER DAVING DISABLE RGISTER – OFFSET 360h ............................................................................. 103
LED DISPLAY CSR 364h (Upstream Port Only) ......................................................................................... 103
CLOCK SCHEME ...................................................................................................................................................... 104
10 POWER MANAGEMENT ......................................................................................................................................... 105
11 POWER SEQUENCE ................................................................................................................................................. 106
12 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................................................ 107
12.1
12.2
12.3
12.4
12.5
ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 107
DC SPECIFICATIONS ........................................................................................................................................... 107
AC SPECIFICATIONS ........................................................................................................................................... 107
OPERATING AMBIENT TEMPERATURE .......................................................................................................... 109
POWER CONSUMPTION ...................................................................................................................................... 109
13 THERMAL DATA ...................................................................................................................................................... 110
14 PACKAGE INFORMATION..................................................................................................................................... 111
15 ORDERING INFORMATION................................................................................................................................... 112
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 8 of 112
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PI7C9X2G606PR
LIST OF FIGURES
FIGURE 4-1 PI7C9X2G606PR BALL ASSIGNMENT (TRANSPARENT TOP VIEW)......................................................................... 18
FIGURE 6-1 DRIVER OUTPUT WAVEFORM .................................................................................................................................. 22
FIGURE 7-1 SMBUS ARCHITECTURE IMPLEMENTATION ............................................................................................................. 45
FIGURE 7-2 SMBUS BLOCK WRITE COMMAND FORMAT, TO WRITE TO A PI7C9X2G606PR REGISTER WITHOUT PEC ............ 46
FIGURE 7-3 SMBUS BLOCK WRITE COMMAND FORMAT, TO WRITE TO A PI7C9X2G606PR REGISTER WITH PEC ................... 46
FIGURE 7-4 SMBUS BLOCK WRITE TO SET UP READ, AND RESULTING READ THAT RETURNS CFG REGISTER VALUE .............. 48
FIGURE 7-5 CSR READ OPERATION USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL .......................................... 50
FIGURE 7-6 CSR READ OPERATION USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL WITH PEC ......................... 50
FIGURE 7-7 STANDARD DEVICES TO I2C BUS CONNECTION BLOCK DIAGRAM .......................................................................... 51
FIGURE 7-8 I2C WRITE PACKET .................................................................................................................................................. 52
FIGURE 7-9 I2C REGISTER WRITE ACCESS EXAMPLE ................................................................................................................. 53
FIGURE 7-10 I2C WRITE COMMAND PACKET EXAMPLE ............................................................................................................. 53
FIGURE 7-11 I2C READ COMMAND PACKET ............................................................................................................................... 55
FIGURE 7-12 I2C REGISTER READ ACCESS EXAMPLE ................................................................................................................. 55
FIGURE 7-13 I2C READ COMMAND PACKET ............................................................................................................................... 56
FIGURE 11-1 INITIAL POWER-UP SEQUENCE ............................................................................................................................ 106
FIGURE 14-1 PACKAGE OUTLINE DRAWING ............................................................................................................................. 111
FIGURE 14-2 PART MARKING ................................................................................................................................................... 111
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 9 of 112
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PI7C9X2G606PR
LIST OF TABLES
TABLE 6-1 RECEIVER DETECTION THRESHOLD SETTINGS .......................................................................................................... 20
TABLE 6-2 RECEIVER SIGNAL DETECT THRESHOLD ................................................................................................................... 21
TABLE 6-3 RECEIVER EQUALIZATION SETTINGS ........................................................................................................................ 21
TABLE 6-4 TRANSMITTER SWING SETTINGS ............................................................................................................................... 21
TABLE 6-5 DRIVE AMPLITUDE BASE LEVEL REGISTERS ............................................................................................................ 22
TABLE 6-6 DRIVE AMPLITUDE BASE LEVEL SETTINGS............................................................................................................... 22
TABLE 6-7 DRIVE DE-EMPHASIS BASE LEVEL REGISTER ........................................................................................................... 23
TABLE 6-8 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ........................................................................................................... 23
TABLE 6-9 SUMMARY OF PCI EXPRESS ORDERING RULES ......................................................................................................... 25
TABLE 7-1 SMBUS ADDRESS PIN CONFIGURATION ................................................................................................................... 45
TABLE 7-2 BYTES FOR SMBUS BLOCK WRITE ........................................................................................................................... 47
TABLE 7-3 SAMPLE SMBUS BLOCK WRITE BYTE SEQUENCE .................................................................................................... 47
TABLE 7-4 BYTES FOR SMBUS BLOCK READ ............................................................................................................................. 48
TABLE 7-5 SMBUS BLOCK WRITE PORTION .............................................................................................................................. 49
TABLE 7-6 SMBUS BLOCK READ PORTION ................................................................................................................................ 49
TABLE 7-7 SMBUS READ COMMAND FOLLOWING REPEAT START FROM MASTER .................................................................. 49
TABLE 7-8 SMBUS RETURN BYTES ............................................................................................................................................ 50
TABLE 7-9 COMMAND FORMAT FOR SMBUS BLOCK READ ....................................................................................................... 50
TABLE 7-10 I2C ADDRESS PIN CONFIGURATION ......................................................................................................................... 51
TABLE 7-11 I2C REGISTER WRITE ACCESS ................................................................................................................................. 52
TABLE 7-12 I2C COMMAND FORMAT FOR WRITE ACCESS.......................................................................................................... 52
TABLE 7-13 I2C COMMAND FORMAT FOR READ ACCESS ........................................................................................................... 54
TABLE 8-1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION ................................................................................................... 97
TABLE 8-2 TABLE ENTRY SIZE IN 4 BITS .................................................................................................................................... 97
TABLE 9-1 DC ELECTRICAL CHARACTERISTICS ....................................................................................................................... 104
TABLE 12-1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 107
TABLE 12-2 DC ELECTRICAL CHARACTERISTICS ..................................................................................................................... 107
TABLE 12-3 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (5.0 GBPS) CHARACTERISTICS .............. 107
TABLE 12-4 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (2.5 GBPS) CHARACTERISTICS .............. 108
TABLE 12-5 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (5.0 GBPS) CHARACTERISTICS ........................ 108
TABLE 12-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (2.5 GBPS) CHARACTERISTICS ........................ 109
TABLE 12-7 OPERATING AMBIENT TEMPERATURE ................................................................................................................... 109
TABLE 12-8 POWER CONSUMPTION .......................................................................................................................................... 109
TABLE 13-1 THERMAL DATA.................................................................................................................................................... 110
PI7C9X2G606PR
Document Number DS40209 Rev 8-2
Page 10 of 112
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© 2022 Copyright Diodes Incorporated. All Rights Reserved.
PI7C9X2G606PR
1 Features
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6-lane PCI Express® Gen 2 Switch with 6 PCI Express ports
Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching
Peer-to-peer switching between any two downstream ports
150 ns typical latency for packet routed through Switch without blocking
Strapped pins configurable with optional EEPROM, SMBus or I2C Bus
SMBus interface support
I2C Slave interface support
Compliant with System Management (SM) Bus, Version 2.0
Compliant with I2C Bus Specification, Version 2.1
Compliant with PCI Express Base Specification Revision 2.1
Compliant with PCI Express CEM Specification Revision 2.0
Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
Compliant with Advanced Configuration Power Interface (ACPI) Specification
Reliability, Availability and Serviceability
Supports Data Poisoning and End-to-End CRC
Advanced Error Reporting and Logging
Advanced Power Saving
Empty downstream ports are set to idle state to minimize power consumption
Link Power Management
Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states
Active state power management for L0s and L1 states
Device State Power Management
Supports D0, D3Hot and D3Cold device power states
Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR
Extended Virtual Channel capability
Two Virtual Channels (VC) and Eight Traffic Class (TC) support
Disabled VCs’ buffer is assigned to enabled VCs for resource sharing
Independent TC/VC mapping for each port
Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted RR
Supports Isochronous Traffic
Isochronous traffic class mapped to VC1 only
Strict time based credit policing
Supports up to 512-byte maximum payload size
Programmable driver current and de-emphasis level at each individual port
Support Address Translation (AT) and Access Control Service (ACS)
Support OBFF and LTR
Support Serial Hot Plug Controller
Low Power Dissipation: 0.6 W typical in L0 normal mode
Industrial Temperature Range -40o to 85oC
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable,
and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative.
https://www.diodes.com/quality/product-definitions/
196-pin LBGA 15mm x 15mm package
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain
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