PI7C9X7958
PCI Express® Octal UART
Datasheet
Revision 2
October 2018
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-435-1100
Internet: http://www.diodes.com
Document Number DS40139 Rev 2-2
PI7C9X7958
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Copyright © 2016, Diodes Incorporated
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Document Number DS40139 Rev 2-2
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PI7C9X7958
REVISION HISTORY
Date
09/05/07
10/31/07
Revision Number
0.1
0.2
04/22/08
0.3
08/13/08
0.4
11/25/08
1.0
03/06/09
1.1
04/20/09
1.2
09/24/09
1.3
03/18/11
06/04/14
1.4
1.5
05/11/15
1.6
08/30/17
1.7
10/16/18
2
Description
Preliminary Datasheet
Fixed the diagrams
Corrected Chapter 4.2 Pin Description (RREF, GPIO[7] EEPROM Organization Pin, RTS[0] EEPROM Bypass Pin)
Updated Chapter 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver Setting, 6.2.41 GPIO Control Register )
Revised Chapter 7.1 Registers in I/O Mode
Updated Chapter 11 Ordering Info
Updated Chapter 8 EEPROM
Updated 1 Features (Clock prescaler, Data frame size, Power Dissipation)
Corrected 3 General Description
Updated 4 Pin Assignment (description for shared pins added, MODE_SEL changed to DRIVER_SEL, VAUX changed
to VDDCAUX, WAKEUP_L, CLKINP, CLKINN)
Added 5.2.4 Mode Selection, 5.2.5 450/550 Mode, 5.2.6 Enhanced 550 Mode, 5.2.7 Enhanced 950 Mode
Corrected 5.2.8 Transmit and Receive FIFOs, 5.2.9 Automated Flow Control
Modified 5.2.12 Baud Rate Generation
Updated 6 PCI Express Register Description (6.2.36, 6.2.42)
Updated Format (6.2.20, 6.2.36, 6.2.54, 6.2.55, 6.2.57)
Updated Chapter 7 UART Register Description (7.1.6 LCR Bit[5:0], 7.1.7 MCR Bit[5] and Bit[7], 7.1.9 MSR Bit[3:0],
7.2.6 LCR Bit[5:0], 7.2.7 MCR Bit[5] and Bit[7], 7.2.9 MSR Bit[3:0], 7.2.11 DLL, 7.2.12 DLH, 7.2.13 EFR, 7.2.18
ACR Bit[7:2], 7.2.23 CPRM)
Updated Chapter 8.3 EEPROM Space Address Map And Description (00h, 0Ah, 40h)
Added Chapter 9 Electrical Specification
Corrected 9.2 DC Specification
Updated 9.3 AC Specification
Added 10 Clock Scheme
Updated Chapter 1 Features (added Industrial Temperature Range)
Updated 9.1 Absolute Maximum Ratings: Ambient Temperature with power applied
Updated 7.1.13 Sample Clock Register and 7.2.27 Sample Clock Register
Updated Chapter 12 Ordering Information
Removed “Preliminary” and “Confidential” references
Corrected Figure 3-1 PI7C9X7958 Block Diagram (SYN_UART_CLK removed)
Corrected Section 4.2.1 UART Interface (SYNCLK_IN_EN and SYN_UART_CLK removed)
Corrected Figure 5-2 Internal Loopback in PI7C7958
Corrected Figure 5-3 Crystal Oscillator as the Clock Source (14.7456 MHz)
Corrected Section 7.1.7 Modem Control Register (Bit[5]), 7.1.10 Special Function Register (Bit[4]), 7.2.7 Modem
Control Register (Bit[5]), 7.2.10 Special Function Register (Bit[4]), 7.2.29 Receive FIFO Data Registers, 7.2.30
Transmit FIFO Data Register, 7.2.31
Added internal pull-up and pull-down information to UART Interface, System Interface, Test Signal, and EEPROM pins
in Section 4.
Updated Figure 5-3 Crystal Oscillator as the Clock Source
Updated Section 6.2.24 Message Signaled Interrupt (MSI) Next Item Pointer 8Ch
Added Section 6.2.25 Message Address Register – Offset 90h
Added Section 6.2.26 Message Upper Address Register – Offset 94h
Added Section 6.2.27 Message Data Register – Offset 98h
Updated Section 11 Package Information
Updated Section 4.1 Pin List (SR_DO and SR_DI)
Updated Section 4.2.5 EEPROM Interface (SR_DO and SR_DI)
Created for IC Revision B
Updated Chapter 12 Ordering Information
Added Section 6.2.25 Message Control Register – OFFSET 8Ch
Updated Table 5-2 Baud Rate Generator Setting
Updated Section 7.2.23 CLOCK PRESCALE REGISTER – OFFSET 14h
Update Logo
Updated Section 4.1 PIN LIST of 160-PIN LFBGA
Updated Section 4.2.1 UART INTERFACE
Updated Table 9.1 Absolute Maximum Ratings
Updated Table 9.2 DC Electrical Characteristics
Updated Section 12 Ordering Information
Revision become whole number
Updated Section 1 Features
Updated Section 12 Ordering Information
Added Figure 11-2 Part Marking
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Document Number DS40139 Rev 2-2
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PI7C9X7958
Table of Contents
1.
FEATURES ............................................................................................................................................9
2.
APPLICATIONS ...................................................................................................................................9
3.
GENERAL DESCRIPTION ...............................................................................................................10
4.
PIN ASSIGNMENT ............................................................................................................................. 11
4.1. PIN LIST OF 160-PIN LFBGA ..................................................................................................... 11
4.2. PIN DESCRIPTION ......................................................................................................................12
4.2.1.
UART INTERFACE ................................................................................................................12
4.2.2.
PCI EXPRESS INTERFACE ..................................................................................................13
4.2.3.
SYSTEM INTERFACE............................................................................................................14
4.2.4.
TEST SIGNALS ......................................................................................................................14
4.2.5.
EEPROM INTERFACE ..........................................................................................................14
4.2.6.
POWER PINS ........................................................................................................................15
5.
FUNCTIONAL DESCRIPTION ........................................................................................................16
5.1. CONFIGURATION SPACE ..........................................................................................................16
5.1.1.
PCI Express Configuration Space .........................................................................................16
5.1.2.
UART Configuration Space ...................................................................................................16
5.2. DEVICE OPERATION..................................................................................................................17
5.2.1.
Configuration Access .............................................................................................................17
5.2.2.
I/O Reads/Writes ....................................................................................................................17
5.2.3.
Memory Reads/Writes ............................................................................................................17
5.2.4.
Mode Selection ......................................................................................................................18
5.2.5.
450/550 Mode ........................................................................................................................18
5.2.6.
Enhanced 550 Mode ..............................................................................................................18
5.2.7.
Enhanced 950 Mode ..............................................................................................................18
5.2.8.
Transmit and Receive FIFOs .................................................................................................18
5.2.9.
Automated Flow Control........................................................................................................20
5.2.10. Internal Loopback..................................................................................................................21
5.2.11. Crystal Oscillator ..................................................................................................................22
5.2.12. Baud Rate Generation ...........................................................................................................23
5.2.13. Power Management ...............................................................................................................23
6.
PCI EXPRESS REGISTER DESCRIPTION ...................................................................................24
6.1. REGISTER TYPES .......................................................................................................................24
6.2. CONFIGURATION REGISTERS .................................................................................................24
6.2.1.
VENDOR ID REGISTER – OFFSET 00h ..............................................................................25
6.2.2.
DEVICE ID REGISTER – OFFSET 00h................................................................................25
6.2.3.
COMMAND REGISTER – OFFSET 04h ...............................................................................25
6.2.4.
STATUS REGISTER – OFFSET 04h......................................................................................26
6.2.5.
REVISION ID REGISTER – OFFSET 08h ............................................................................26
6.2.6.
CLASS CODE REGISTER – OFFSET 08h ............................................................................27
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch............................................................................27
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .....................................................27
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch.........................................................................27
6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h .....................................................................27
6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h .....................................................................27
6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................27
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6.2.13.
6.2.14.
6.2.15.
6.2.16.
6.2.17.
6.2.18.
6.2.19.
6.2.20.
6.2.21.
6.2.22.
6.2.23.
6.2.24.
6.2.25.
6.2.26.
6.2.27.
6.2.28.
6.2.29.
6.2.30.
6.2.31.
6.2.32.
6.2.33.
6.2.34.
6.2.35.
6.2.36.
6.2.37.
6.2.38.
6.2.39.
6.2.40.
6.2.41.
6.2.42.
6.2.43.
6.2.44.
6.2.45.
6.2.46.
6.2.47.
6.2.48.
6.2.49.
6.2.50.
6.2.51.
6.2.52.
6.2.53.
6.2.54.
6.2.55.
6.2.56.
6.2.57.
100h
6.2.58.
6.2.59.
6.2.60.
6.2.61.
6.2.62.
6.2.63.
SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................28
CAPABILITIES POINTER REGISTER – OFFSET 34h .........................................................28
INTERRUPT LINE REGISTER – OFFSET 3Ch ....................................................................28
INTERRUPT PIN REGISTER – OFFSET 3Ch ......................................................................28
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ...............................28
NEXT ITEM POINTER REGISTER – OFFSET 80h..............................................................28
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ................................28
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ...............................................29
PPB SUPPORT EXTENSIONS – OFFSET 84h.....................................................................29
PM DATA REGISTER – OFFSET 84h ...................................................................................29
MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch ...........................30
MESSAGE SIGNALED INTERRUPTS (MSI) NEXT ITEM POINTER 8Ch ..........................30
MESSAGE CONTROL REGISTER – OFFSET 8Ch ..............................................................30
MESSAGE ADDRESS REGISTER – OFFSET 90h ...............................................................30
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h ..................................................30
MESSAGE DATA REGISTER – OFFSET 98h .......................................................................30
VPD CAPABILITY ID REGISTER – OFFSET 9Ch ...............................................................30
NEXT ITEM POINTER REGISTER – OFFSET 9Ch .............................................................31
VPD REGISTER – OFFSET 9Ch ..........................................................................................31
VPD DATA REGISTER – OFFSET A0h ................................................................................31
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .....................................31
NEXT ITEM POINTER REGISTER – OFFSET A4h .............................................................31
LENGTH REGISTER – OFFSET A4h ...................................................................................31
XPIP CSR0 – OFFSET A8h (Test Purpose Only) ..................................................................32
XPIP CSR1 – OFFSET ACh (Test Purpose Only)..................................................................32
REPLAY TIME-OUT COUNTER – OFFSET B0h .................................................................32
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h ..........................................................32
UART DRIVER SETTING – OFFSET B4h ............................................................................32
POWER MANAGEMENT CONTROL PARAMENT – OFFSET B8h .....................................33
DEBUG REGISTER 1 – OFFSET BCh (Test Purpose Only) ................................................34
DEBUG REGISTER 2 – OFFSET C0h (Test Purpose Only) .................................................34
DEBUG REGISTER 3 – OFFSET C4h (Test Purpose Only) .................................................34
DEBUG REGISTER 4 – OFFSET C8h (Test Purpose Only) .................................................34
GPIO CONTROL REGISTER – OFFSET D8h ......................................................................34
EEPROM CONTROL REGISTER – OFFSET DCh ...............................................................35
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ................................................35
NEXT ITEM POINTER REGISTER – OFFSET E0h .............................................................35
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .................................................35
DEVICE CAPABILITIES REGISTER – OFFSET E4h ...........................................................35
DEVICE CONTROL REGISTER – OFFSET E8h .................................................................36
DEVICE STATUS REGISTER – OFFSET E8h ......................................................................37
LINK CAPABILITIES REGISTER – OFFSET ECh ...............................................................37
LINK CONTROL REGISTER – OFFSET F0h .......................................................................38
LINK STATUS REGISTER – OFFSET F0h ...........................................................................38
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET
39
CAPABILITY VERSION – OFFSET 100h ..............................................................................39
NEXT ITEM POINTER REGISTER – OFFSET 100h............................................................39
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .....................................39
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h........................................40
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ................................41
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h...........................................42
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6.2.64.
6.2.65.
6.2.66.
7.
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .............................................42
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h .............43
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .................................................43
UART REGISTER DESCRIPTION ..................................................................................................44
7.1. REGISTERS IN I/O MODE ..........................................................................................................44
7.1.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................45
7.1.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h ..............................................................45
7.1.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................45
7.1.4.
INTERRUPT STATUS REGISTER – OFFSET 02h ................................................................46
7.1.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................46
7.1.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................47
7.1.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................47
7.1.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................48
7.1.9.
MODEM STATUS REGISTER – OFFSET 06h ......................................................................49
7.1.10. SPECIAL FUNCTION REGISTER – OFFSET 07h ...............................................................49
7.1.11. DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ........................................50
7.1.12. DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1.......................................50
7.1.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 .................................................50
7.2. REGISTERS IN MEMORY-MAPPING MODE ...........................................................................51
7.2.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................52
7.2.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h ..............................................................53
7.2.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................53
7.2.4.
INTERRUPT STATUS REGISTER – OFFSET 02h ................................................................53
7.2.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................54
7.2.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................54
7.2.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................55
7.2.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................56
7.2.9.
MODEM STATUS REGISTER – OFFSET 06h ......................................................................56
7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h ...............................................................57
7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h .............................................................57
7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h............................................................57
7.2.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah .........................................................58
7.2.14. XON SPECIAL CHARACTER 1 – OFFSET 0Bh ...................................................................59
7.2.15. XON SPECIAL CHARACTER 2 – OFFSET 0Ch ..................................................................59
7.2.16. XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ................................................................59
7.2.17. XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh.................................................................59
7.2.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh ..............................................................59
7.2.19. TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h ...............................................60
7.2.20. RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ..................................................60
7.2.21. FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h .................................................60
7.2.22. FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h ...............................................60
7.2.23. CLOCK PRESCALE REGISTER – OFFSET 14h ..................................................................60
7.2.24. RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0 ..........................................60
7.2.25. LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ....................................61
7.2.26. TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .......................................61
7.2.27. SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 .................................................61
7.2.28. GLOBAL LINE STATUS REGISTER – OFFSET 17h ............................................................61
7.2.29. RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ..............................................62
7.2.30. TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ...........................................62
7.2.31. LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................62
8.
EEPROM INTERFACE .....................................................................................................................63
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8.1.
8.2.
8.3.
9.
AUTO MODE EERPOM ACCESS ...............................................................................................63
EEPROM MODE AT RESET ........................................................................................................63
EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................63
ELECTRICAL SPECIFICATION .....................................................................................................65
9.1.
9.2.
9.3.
ABSOLUTE MAXIMUM RATINGS ...........................................................................................65
DC SPECIFICATIONS..................................................................................................................65
AC SPECIFICATIONS..................................................................................................................65
10.
CLOCK SCHEME ..........................................................................................................................68
11.
PACKAGE INFORMATION .........................................................................................................69
12.
ORDER INFORMATION ..............................................................................................................70
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Table of Tables
TABLE 4-1 PIN-LIST OF 160-PIN LFBGA ....................................................................................................... 11
TABLE 5-1 MODE SELECTION .........................................................................................................................18
TABLE 5-2 BAUD RATE GENERATOR SETTING ................................................................................................23
TABLE 5-3 SAMPLE BAUD RATE SETTING.......................................................................................................23
TABLE 7-1 UART BASE ADDRESS IN I/O MODE .............................................................................................44
TABLE 7-2 REGISTERS IN I/O MODE ...............................................................................................................45
TABLE 7-3 UART BASE ADDRESS IN MEMORY MODE....................................................................................51
TABLE 7-4 MEMORY-MAP MODE ....................................................................................................................52
TABLE 9-1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................65
TABLE 9-2 DC ELECTRICAL CHARACTERISTICS .............................................................................................65
TABLE 9-3 TRANSMITTER CHARACTERISTICS .................................................................................................65
TABLE 9-4 RECEIVER CHARACTERISTICS .......................................................................................................66
TABLE 10-1 INPUT CLOCK REQUIREMENTS ....................................................................................................68
List of Figures
FIGURE 3-1 PI7C9X7958 BLOCK DIAGRAM...................................................................................................10
FIGURE 5-1 TRANSMIT AND RECEIVE FIFOS ..................................................................................................19
FIGURE 5-2 INTERNAL LOOPBACK IN PI7C9X7958 ........................................................................................21
FIGURE 5-3 CRYSTAL OSCILLATOR AS THE CLOCK SOURCE ...........................................................................22
FIGURE 5-4 EXTERNAL CLOCK SOURCE AS THE CLOCK SOURCE....................................................................22
FIGURE 7-1 UART REGISTER BLOCK ARRANGEMENT IN I/O MODE ..............................................................44
FIGURE 7-2 UART REGISTER BLOCK ARRANGEMENT IN MEMORY MODE .....................................................51
FIGURE 11-1 PACKAGE OUTLINE DRAWING....................................................................................................69
FIGURE 11-2 PART MARKING..........................................................................................................................69
Page 8 of 70
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PI7C9X7958
1. FEATURES
x1 PCI Express link host interface
Eight high performance 950-class UARTs
Compliant with PCI Express Base Specification 1.1
Compliant with PCI Express CEM Specification 1.1
Compliant with PCI Power Management 1.2
Fully 16C550 software compatible UARTs
128-byte FIFO for each transmitter and receiver
Baud rate up to 15 Mbps in asynchronous mode
Flexible clock prescaler from 4 to 46
Automated in-band flow control using programmable Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and
out-of-band flow control
Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device
drivers
Detection of bad data in the receiver FIFO
Data framing size including 5, 6, 7, 8 and 9 bits
Hardware reconfiguration through Microwire compatible EEPROM
Operations via I/O or memory mapping
Dual power operation (1.8V for PCIe I/O and core, 3.3V for UART I/O)
Power dissipation: 0.9 W typical in normal mode
Industrial Temperature Range -40o to 85o
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
160-pin LFBGA package
2. APPLICATIONS
Remote Access Servers
Network / Storage Management
Factory Automation and Process Control
Instrumentation
Multi-port RS-232/ RS-422/ RS-485 Cards
Point-of-Sale Systems (PoS)
Industrial PC (IPC)
Industrial Control
Gaming Machines
Building Automation
Embedded Systems
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain
