PT7C433833
Real-time Clock Module (I2C Bus)
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Product Features
Product Description
Using external 32.768kHz quartz crystal
The PT7C4338 serial real-time clock is a low-power
Supports I2C-Bus's high speed mode (400 kHz)
clock/calendar with a programmable square-wave output
Includes time (Hour/Minute/Second) and calendar
and 56 bytes of nonvolatile RAM.
(Year/Month/Date/Day) counter functions (BCD
code)
Address and data are transferred serially via a 2-wire,
Programmable square wave output signal
bidirectional bus. The clock/calendar provides seconds,
56-byte, battery-backed, nonvolatile (NV) RAM for
minutes, hours, day, date, month, and year information.
data storage
The date at the end of the month is automatically
Automatic power-fail detect and switch circuitry of
adjusted for months with fewer than 31 days, including
battery backup
corrections for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator.
UL Recognized: E348121
The PT7C4338 series have a built-in power sense circuit
that detects power failures and automatically switches to
the battery supply.
Table 1 shows the basic functions of PT7C4338. More
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4338
Item
1
Function
Oscillator
PT7C4338
Source: Crystal: 32.768kHz
Oscillator enable/disable
Oscillator fail detect
12-hour
24-hour
Time display
2
Time
Century bit
3
Alarm interrupt
4
Programmable square wave output (Hz)
5
RAM
6
Battery backup
1, 4.096k, 8.192k, 32.768k
568
12-07-0001
PT0321-6
1
07/04/12
PT7C433833
Real-time Clock Module (I2C Bus)
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Pin Assignment
PT7C4338
1
X1
VCC
8
2
X2
SQW/OUT
7
3
VBAT
SCL
6
4
GND
SDA
5
SOIC-8
MSOP-8
Pin Description
Pin no.
Pin
Type
1
X1
I
2
X2
O
6
SCL
I
5
SDA
I/O
7
SQW/OUT
O
8
VCC
P
3
VBAT
P
4
GND
P
Description
32.768kHz Crystal Connections. The internal oscillator circuitry is designed for operation with
a crystal having a specified load capacitance (CL) of 12.5pF. Pin X1 is the input to the oscillator
and can optionally be connected to an external 32.768kHz oscillator. The output of the internal
oscillator, pin X2, is floated if an external oscillator is connected to pin X1. An external
32.768kHz oscillator can also drive the PT7C4338. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is floated.
Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface.
Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open-drain output and requires an external pull-up resistor.
Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is open drain and
requires an external pull up resistor. Operates with either VCC or VBAT applied.
Supply Voltage. When voltage is applied within normal limits, the device is fully accessible and
data can be written and read. When a backup supply is connected to the device and VCC is
below VPF, reads and writes are inhibited. However, the timekeeping function continues
unaffected by the lower input voltage.
+3V Battery Input. Backup supply input for any standard 3V lithium cell or other energy
source. Battery voltage must be held between the minimum and maximum limits for proper
operation. If a backup supply is not required, VBAT must be grounded. UL recognized to ensure
against reverse charging when used with a lithium battery.
Ground. DC power is provided to the device on these pins. VCC is the primary power input.
When voltage is applied within normal limits, the device is fully accessible and data can be
written and read. When a backup supply is connected to the device and VCC is below VPF, reads
and writes are inhibited. However, the timekeeping function continues unaffected by the lower
input voltage.
12-07-0001
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PT7C433833
Real-time Clock Module (I2C Bus)
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Function Block
Maximum Ratings
Storage Temperature ...............................................................................................................-55oCto +125oC
Ambient Temperature with Power Applied ......................................................................-40oCto +85oC
Supply Voltage to Ground Potential (Vcc to GND) ..................................................... -0.3V to +6.5V
DC Input (All Other Inputs except Vcc & GND)........................................................... -0.3V to +6.5V
DC Output Voltage (SDA, /INTA, /INTB pins) ..............................................................-0.3V to +6.5V
DC Output Current (FOUT)..................................................................................................-0.3V to (Vcc+0.3V)
Power Dissipation ....................................................................................................................320mW (depend on package)
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
(VCC = VCC(MIN) to VCC(MAX), TA = -40℃ to +85℃.) (Note 1)
Parameter
Symbol
Conditions
Min.
Supply Voltage
VCC
PT7C433833
2.7
Logic 1
VIH
Note 2
0.7 * VCC
Logic 0
VIL
Note 2
-0.3
Power-Fail Voltage
VPF
PT7C433833
VBAT Battery Voltage
VBAT
Note 2
1.5
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
12-07-0001
Typ.
3.3
2.59
3.0
Max.
5.5
VCC + 0.3
+0.3 * VCC
3.7
PT0321-6
3
07/04/12
Unit
V
PT7C433833
Real-time Clock Module (I2C Bus)
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DC Electrical Characteristics
(VCC = VCC(MIN) to VCC(MAX), TA = -40℃ to +85℃.) (Note 1)
Parameter
VBAT Battery Voltage
Input Leakage
I/O Leakage
Symbol
VBAT
ILI
ILO
SDA Logic 0 Output
IOLSDA
SQW/OUT Logic 0 Output
IOLSQW
Active Supply Current (Note 5)
Standby Current (Note 6)
VBAT Leakage Current (VCC
Active)
Min.
1.5
3.0
3.0
3.0
3.0
250
-
Typ.
120
85
Max.
3.7
1
1
200
125
Unit
V
μA
μA
ICCA
ICCS
Conditions
Note 2
Note 3
Note 4
VCC > 2V; VOL = 0.4V
VCC < 2V; VOL = 0.2 VCC
VCC > 2V; VOL = 0.4V
1.71V < VCC < 2V; VOL = 0.2 VCC
1.5V < VCC < 1.71V; VOL = 0.2 VCC
PT7C433833
PT7C433833
IBATLKG
-
-
25
100
nA
Typ.
400
570
-
Max.
1200
1400
300
Unit
nA
nA
nA
mA
mA
μA
μA
μA
(VCC = 0V, TA = -40℃ to +85℃.) (Note 1)
Parameter
VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT OFF (Note 7)
VBAT Current (OSC ON); VBAT =3.7V, SQW/OUT ON (32kHz) (Note 7)
VBAT Data-Retention Current (OSC OFF); VBAT =3.7V (Note 7)
Symbol
IBATOSC1
IBATOSC2
IBATDAT
Min.
-
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: SCL only.
Note 4: SDA and SQW/OUT.
Note 5: ICCA------SCL clocking at max frequency = 400kHz.
Note 6: Specified with the I2C bus inactive.
Note 7: Measured with a 32.768kHz crystal attached to X1 and X2.
AC Electrical Characteristics
Sym
VHM
VHL
Description
Rising and falling threshold voltage high
Rising and falling threshold voltage low
Value
0.7 VCC
0.3 VCC
Unit
V
V
Measurement level
Signal
VHM
VLM
tr
tf
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PT7C433833
Real-time Clock Module (I2C Bus)
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(TA = -40℃ to +85℃) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Fast mode
100
400
SCL Clock Frequency
fSCL
kHz
Standard mode
100
Fast mode
1.3
Bus Free Time Between STOP and
tBUF
μs
START condition
Standard mode
4.7
Fast mode
0.6
Hold Time (Repeated) START Condition
tHD:STA
μs
(Note 2)
Standard mode
4.0
Fast mode
1.3
LOW Period of SCL Clock
tLOW
μs
Standard mode
4.7
Fast mode
0.6
HIGH Period of SCL Clock
tHIGH
μs
Standard mode
4.0
Fast mode
0.6
Setup Time of Repeated START
tSU:STA
μs
Condition
Standard mode
4.7
Fast mode
0
0.9
Data Hold Time (Note 3, 4)
tHD:STA
μs
Standard mode
0
Fast mode
100
Data Setup Time (Note 5)
ns
tSU:STA
Standard mode
250
Fast mode
20+0.1CB
300
Rise Time of Both SDA and SCL Signals
tr
ns
(Note 6)
Standard mode
20+0.1CB
1000
Fast mode
20+0.1CB
300
Fall Time of Both SDA and SCL Signals
tf
ns
(Note 6)
Standard mode
20+0.1CB
300
Fast mode
0.6
Setup Time for STOP Condition
μs
tSU:STO
Standard mode
4.0
Capacitance Load for Each Bus Line
Note 6
400
pF
CB
I/O Capacitance (SDA, SCL)
Note 1
10
pF
CI/O
Oscillator Stop Flag (OSF) Delay
Note
7
100
ms
tOSF
Note 1: Limits of full temperature are guaranteed by design not production test.
Note 2: After this period, the first clock pulse is generated.
Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 4: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (t LOW) of the SCL signal.
Note 5: A fast-mode device can be used in a standard-mode system, but the requirement t SU:DAT ≥ to 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t r MAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
Note 6: CB------total capacitance of one bus line in pF.
Note 7: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBAT ≤ 3.7V.
12-07-0001
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PT7C433833
Real-time Clock Module (I2C Bus)
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Timing Diagram
Power-Up/Power-Down Characteristics
(TA = -40℃ to +85℃) (Note 1, Fig 3)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Recovery at Power-Up (Note 2)
tREC
2
ms
VCC Fall Time: VPF(MAX) to VPF(MIN)
tVCCF
300
μs
VCC Rise Time: VPF(MIN) to VPF(MAX)
tVCCR
0
μs
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
Fig 3. Power-Up/Power-Down Timing
12-07-0001
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07/04/12
PT7C433833
Real-time Clock Module (I2C Bus)
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Recommended Layout for Crystal
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
Typ
Unit
X1 to GND
CG
20
pF
Build-in capacitors
X2 to GND
CD
20
pF
X1 to GND
C1
4
pF
Recommended External
capacitors
X2 to GND
C2
4
pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768KHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Nominal Frequency
Series Resistance
Load Capacitance
Symbol
fO
ESR
CL
Min
-
Typ
32.768
12.5
12-07-0001
Max
70
-
PT0321-6
7
Unit
kHz
k
pF
07/04/12
PT7C433833
Real-time Clock Module (I2C Bus)
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Function Description
Overview of Functions
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 4.096k, 8.192k, 32.768k Hz.
Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is
also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I 2C bus's high-speed mode.
Oscillator enable/disable
Oscillator can be enabled or disabled by /EOSC bit.
Registers
Allocation of registers
Addr.
Function
(hex)*1
00
01
Seconds (00-59)
Minutes (00-59)
02
Hours (00-23 / 01-12)
03
04
05
06
07
08~3F
Days of the week (01-07)
Dates (01-31)
Months (01-12)
Years (00-99)
Control*3
RAM*7
Bit 7
*2
/EOSC
0
Bit 6
Bit 5
S40
M40
S20
M20
H20 or
P, /A
0
D20
0
Y20
OSF
-
0
12, /24
0
0
0
Y80
OUT*4
-
0
0
0
Y40
0
-
Register definition
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S10
M10
S8
M8
S4
M4
S2
M2
S1
M1
H10
H8
H4
H2
H1
0
D10
MO10
Y10
SQWE*5
-
0
D8
MO8
Y8
0
-
W4
D4
MO4
Y4
0
-
W2
D2
MO2
Y2
RS1*6
-
W1
D1
MO1
Y1
RS0*6
-
Caution points:
*1. PT7C4338 uses 6 bits for address. That is if write data to 41H, the data will be written to 01H address register.
*2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active.
*3. Control register was used to select SQW/OUT pin output square wave with one of 4 kinds of frequency or DC level.
*4. Control SQW/OUT pin output DC level when square wave is disabled.
*5. Square wave outputs enable at SQW/OUT pin.
*6. Square wave output frequency select.
*7. PT7C4338 has 568 static RAM for customer use. It is volatile RAM.
*8. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer using
space.
12-07-0001
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07/04/12
PT7C433833
Real-time Clock Module (I2C Bus)
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Control and status register
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
07
Control
(default)
OUT
1
0
0
OSF
1
SQWE
1
0
0
0
0
RS1
1
RS0
1
OUT
It controls the output level of the SQW/OUT pin when the square wave output is disabled.
OUT
Data
Description
0
When SQWE = 0, SQW/OUT pin output low.
1
When SQWE = 0, SQW/OUT pin output high.
Read / Write
Default
SQWE (Square Wave Enable)
This bit, when set to logic 1, will enable the oscillator output. The frequency of the square wave output depends upon the value of
the RS0 and RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling edge of the square wave.
RS (Rate Select)
These bits control the frequency of the square wave output when the square wave output has been enabled.
RS1, RS0
Data
SQW output freq. (Hz)
00
1
01
4.096k
10
8.192k
11
32.768k
Read / Write
Default
OSF(Oscillator Stop Flag)
Logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge
the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of
conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC and VBAT is insufficient to support oscillation.
3) The /EOSC bit is set to 1, disabling the oscillator.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF bit to logic 1
leaves the value unchanged.
12-07-0001
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07/04/12
PT7C433833
Real-time Clock Module (I2C Bus)
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Time Counter
Time digit display (in BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
(hex)
Description
D7
00
Seconds
(default)
/EOSC
0
S40
S20
S10
S8
S4
Undefined Undefined Undefined Undefined Undefined
S2
S1
Undefined Undefined
01
Minutes
(default)
0
0
M40
M20
M10
M8
M4
Undefined Undefined Undefined Undefined Undefined
M2
M1
Undefined Undefined
02
Hours
(default)
0
0
12, /24 H20 or P,/A
H10
H8
H4
Undefined Undefined Undefined Undefined Undefined
H2
H1
Undefined Undefined
D6
D5
D4
D3
D2
D1
D0
12, /24 bit
This bit is used to select between 12-hour clock system and 24-hour clock system.
12, /24
Data
Description
0
24-hour system
1
12-hour system
Read / Write
This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12, /24
Description
Hours register
0
24-hour time display
1
12-hour time display
24-hour clock
00
01
02
03
04
05
06
07
08
09
10
11
12-hour clock
52 ( AM 12 )
41 ( AM 01 )
42 ( AM 02 )
43 ( AM 03 )
44 ( AM 04 )
45 ( AM 05 )
46 ( AM 06 )
47 ( AM 07 )
48 ( AM 08 )
49 ( AM 09 )
50 ( AM 10 )
51 ( AM 11 )
24-hour clock
12
13
14
15
16
17
18
19
20
21
22
23
12-hour clock
72 ( PM 12)
61 ( PM 01 )
62 ( PM 02 )
63 ( PM 03 )
64 ( PM 04 )
65 ( PM 05 )
66 ( PM 06 )
67 ( PM 07 )
68 ( PM 08 )
69 ( PM 09 )
70 ( PM 10 )
71 ( PM 11 )
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
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Real-time Clock Module (I2C Bus)
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Days of the week Counter
The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond
to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
03
Days of the week
(default)
0
0
0
0
0
0
0
0
0
0
W4
W2
W1
Undefined Undefined Undefined
Calendar Counter
The data format is BCD format.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
(hex)
Description
D7
D6
D5
04
Dates
(default)
0
0
0
0
D20
Undefined
D10
D8
D4
D2
Undefined Undefined Undefined Undefined
D1
Undefined
05
Months
(default)
0
0
0
0
0
0
M10
M8
M4
M2
Undefined Undefined Undefined Undefined
M1
Undefined
06
Years
(default)
Y80
Undefined
Y10
Y8
Y4
Y2
Undefined Undefined Undefined Undefined
Y1
Undefined
D4
Y40
Y20
Undefined Undefined
D3
D2
D1
D0
Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
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I2C Bus Interface
Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Fig 1. System configuration
Vcc
RP
RP
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When there is only one master, the MCU is ready for driving SCL to "H" and R P of SCL may not required.
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Real-time Clock Module (I2C Bus)
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Starting and Stopping I2C Bus Communications
Fig 2. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which
case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Data Transfers and Acknowledge Responses during I2C-BUS Communication
a) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes)
of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
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b) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
8
2
SDA from transmitter
(sending side)
9
Release SDA
Low active
SDA from receiver
(receiving side)
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Table
Slave address
R / W bit
Operation
Transfer data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
D1 h
1 (= Read)
1
1
0
1
0
0
0
Write
D0 h
0 (= Write)
I2C Bus’s Basic Transfer Format
S
Start indication
Sr
Restart indication
P
Stop indication
12-07-0001
A
RTC Acknowledge
A
Master Acknowledge
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1) Write via I2C bus
Slave address (7 bits)
S
1
Start
1
0
1
0
write
0
0
Addr. setting
A
A
0
A
C
K
Slave address + write specification
A
C
K
Address
Specifies the write start address.
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Write data
A
P
A
C
K
Stop
2) Read via I2C bus
a)
Standard read
Slave address (7 bits)
S
1
Start
1
0
1
0
0
write
0
Slave address (7 bits)
1
1
0
1
0
0
A
C
K
Read
0
A
1
A
C
K
Restart
Slave address + read specification
b)
A
0
Slave address + write specification
Sr
Addr. setting
A
A
C
K
Address
Specifies the read start address.
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (1)
Data is read from the specified start
address and address auto increment.
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (2)
Address auto increment to set the
address for the next data to be read.
/A
P
N
O
Stop
A
C
K
Simplified read
Slave address (7 bits)
S
1
Start
1
0
1
0
0
Read
0
Slave address + read specification
A
1
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (1)
Data is read from the address pointed
by the internal address register and
address auto increment.
A
A
C
K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
Data read (2)
Address register auto increment to set
the address for the next data to be
read.
/A
P
N
O
Stop
A
C
K
Note:
1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications.
2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
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Mechanical Information
WE (Lead free and Green SOIC-8)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
Note:
1) Controlling dimensions in millimeters.
2) Ref : JEDEC MS-012E/AA
12-07-0001
Dimensions In Millimeters
Min
Max
1.350
1.750
0.100
0.250
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.800
4.000
5.800
6.200
1.27 BSC
0.400
1.270
0°
8°
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Real-time Clock Module (I2C Bus)
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UE(Lead free and Green MSOP-8)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
Note:
1) Controlling dimensions in millimeters.
2) Ref : JEDEC MO-187E/BA
Dimensions In Millimeters
Min
Max
0.82
1.10
0.02
0.15
0.75
0.95
0.25
0.38
0.09
0.23
2.90
3.10
2.90
3.10
4.75
5.05
0.65 BSC
0.40
0.80
0°
6°
Ordering Information
Part Number
PT7C433833WE
Package Code
W
Package
Lead free and Green 8-Pin SOIC
PT7C433833UE
U
Lead free and Green 8-Pin MSOP
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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