PT7C4512WE

PT7C4512 PLL Clock Multiplier Features Description  Zero ppm multiplication error This Clock Multiplier is the most cost-effective way to  Input crystal frequency of 5 - 40 MHz generate a high quality, high frequency clock outputs from  Input clock frequency of 4 - 50 MHz lower frequency crystal or clock input. It is designed to  Output clock frequencies up to 200 MHz replace crystal oscillators in most electronic systems, clock  Low period jitter 80ps (100~200MHz) multipliers and frequency translation devices with low output  Duty cycle of 45/55% of output clock up to 160MHz jitter. The device implements a standard fundamental mode  9 selectable frequencies controlled by S0, S1 pins using PLL techniques and inexpensive crystal to produce  Operating voltages of 3.0 to 5.5V output clocks up to 200 MHz.  Lead free SOIC-8 package The internal Logic divider is to generate nine different popular multiplication factors, allowing one chip to output many common frequencies. Pin Configuration Pin Description Clock Output Table S1 S0 CLK Crystal connection or clock input 0 0 X41 P Connect to +3.3V or +5V 0 M2 X(16/3) GND P Connect to ground 0 1 X5 4 REF O Buffered crystal oscillator output clock M 0 X2.5 5 CLK O Clock output per Clock Output Table M M X2 6 S0 T1 M 1 X(10/3) 7 S1 T1 Multiplier select pin 0, connect to GND or VCC or floating (no connection) Multiplier select pin 1, connect to GND or Vcc or floating (no connection) Crystal connection. Leave unconnected for clock input 1 0 X6 1 M X3 1 1 X8 Pin# Name 1 X1/ICLK 2 VCC 3 8 X2 Type X1 ZO PT7C4512 Document Number DS40692 Rev 2-2 Description www.diodes.com 1 Note: 1. CLK output frequency = ICLK X 4 2. M = Leave unconnected (self-biases to VCC/2) February 2018 © Diodes Incorporated PT7C4512 Block Diagram External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the PT7C4512 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01μF or 0.1uF must be connected between VCC and the GND. It must be connected close to the PT7C4512 to minimize lead inductance. No external power supply filtering is required for the PT7C4512. Series Termination Resistor A 33Ω terminating resistor can be used next to the CLK pin for trace lengths over one inch. Crystal Load Capacitors There is no on-chip capacitance build-in chip. A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal CL*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 15 pF load capacitance, each crystal capacitor would be 30pF. PT7C4512 Document Number DS40692 Rev 2-2 www.diodes.com 2 February 2018 © Diodes Incorporated PT7C4512 Maximum Rating Storage Temperature………………………………….-60oC to +150oC Junction Temperature………………………………...……+125oC Max Supply Voltage to Ground Potential (VCC)……………..-0.3V to +7.0V Inputs (Referenced to GND) ………………………-0.5V to VCC+0.5V Clock Output (Referenced to GND)… …………… -0.5V to VCC+0.5V Soldering Temperature (Max of 10 seconds)… …….260oC (Max. 10s) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Sym Parameter Condition VCC Supply Voltage TA Operating Temperature Min Typ Max Unit 3.0 5.5 V -40 +85 o C DC Electrical Characteristics (VCC = 3.3±0.3V, TA = -40~85oC, unless otherwise noted) Sym Parameter Test Condition VCC Supply Voltage ICC Supply Current VIH Input Logic High ICLK VIL Input Logic Low ICLK VIH Input Logic High S0, S1 VIM Input Mid-level S0, S1 VIL Input Logic Low S0, S1 VOH High-level Output Voltage IOH = -12mA CLK VOL Low-level Output Voltage IOL = 12 mA CLK IS Short Circuit Current No load, 20MHz crystal, 100MHz output Pin Min. Typ. Max. Unit VCC 3 3.3 3.6 V 12 20 mA VCC (VCC/2)+1 VCC/2 VCC/2 V (VCC/2)-1 VCC-0.5 V V VCC/2 V 0.5 2.4 V V 0.4 ±30 CLK mA o (VCC = 5.0±0.5V, TA = -40~85 C, unless otherwise noted) Sym Parameter VCC Supply Voltage ICC Supply Current VIH Input Logic High ICLK VIL Input Logic Low ICLK VIH Input Logic High S0, S1 VIM Input Mid-level S0, S1 VIL Input Logic Low S0, S1 VOH High-level Output Voltage IOH = -12mA CLK VOL Low-level Output Voltage IOL = 12 mA CLK IS Short Circuit Current PT7C4512 Document Number DS40692 Rev 2-2 Test Condition No load, 20MHz crystal, 100MHz output Pin Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V 20 30 mA VCC CLK www.diodes.com 3 (VCC/2)+1 VCC/2 VCC/2 V (VCC/2)-1 VCC-0.4 V V VCC/2 V 0.4 VCC-0.5 V V 0.4 ±70 mA February 2018 © Diodes Incorporated PT7C4512 Test Circuits 1>Load circuit for output clock duty cycle, rise and fall time Measurement 2> Timing Definitions for output clock rise and fall time Measurement PT7C4512 Document Number DS40692 Rev 2-2 www.diodes.com 4 February 2018 © Diodes Incorporated PT7C4512 AC Electrical Characteristics (VCC = 3.3±0.3V, TA = -40~85oC, unless otherwise noted) Sym Parameter Test Condition FIN Input Frequency (2) Pin Min. Crystal ICLK Clock Typ. Max. Unit 5 40 MHz ICLK 4 50 MHz VCC: 3.0 to 3.6V CLK 20 180 MHz FOUT Output Frequency tR Output Clock Rise Time 0.8 to 2.0V, with 15pF load CLK 1 Ns tF Output Clock Fall Time 2.0 to 0.8V, with 15pF load CLK 1 Ns Duty Output Clock Duty Cycle At VCC/2, below 160MHz CLK 45 At VCC/2, 160MHz to 180MHz CLK 40 PLL Bandwidth (1) Period Jitter 50 55 % 60 % 10 70MHz~160MHz, 25C kHz CLK 120 ps Max. Unit Note: 1. Only reference for design 2. The phase relationship between input and output clocks can change at power up (VCC = 5.0±0.5V, TA = -40~85oC, unless otherwise noted) Sym Parameter Test Condition Pin Min. FIN Input Frequency Typ. Crystal ICLK 5 40 MHz Clock ICLK 4 50 MHz 20 200 MHz FOUT Output Frequency (2) VCC: 4.5 to 5.5V CLK tR Output Clock Rise Time CLK 1.2 Ns tF Output Clock Fall Time 20%VCC to 80%VCC, with 15pF load 80%VCC to 20%VCC, with 15pF load CLK 1.2 Ns Duty Output Clock Duty Cycle At VCC/2, below 160MHz CLK 45 At VCC/2, 160MHz to 200MHz CLK 40 PLL Bandwidth (1) Period Jitter 50 55 % 60 % 10 70MHz~160MHz, 25C CLK kHz 120 ps Note: 1. Only reference for design 2. The phase relationship between input and output clocks can change at power up Part Marking W Package PT7C4512 Document Number DS40692 Rev 2-2 www.diodes.com 5 February 2018 © Diodes Incorporated PT7C4512 Packaging Mechanical 8-SOIC (W) For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/ Ordering Information Part Number PT7C4512WEX Package Code W Description 8-Pin, 150mil-Wide (SOIC) Notes: PT7C4512 Document Number DS40692 Rev 2-2 www.diodes.com 6 February 2018 © Diodes Incorporated PT7C4512 1. 2. 3. 4. 5. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied. See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, “Green” and Lead-free. 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Copyright © 2016, Diodes Incorporated www.diodes.com PT7C4512 Document Number DS40692 Rev 2-2 www.diodes.com 7 February 2018 © Diodes Incorporated