Bel Power Solutions DP8110G is an intelligent, fully
programmable step-down point-of-load DC-DC converter
integrating digital power conversion and intelligent power
management.
It works with the DM7300 Series Digital Power Managers
(DPM) which provides for synchronizing all system PowerOn-Load regulators, for an elegant, flexible, low noise
power system solution.
All key parameters, sequencing, tracking, fault protection,
and compensation parameters of the DP8110G are
programmable via Bel Power Solutions I2C based GUI. All
settings can be changed by a user at any time during
product development and service. Once programmed, the
DPM remembers all settings and configures the DP8110G
through a self-clocking single wire communication bus.
FLASH memory in the DPM allows changes to be made
without the need to solder or rewire the regulator.
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Output voltage range: 0.7 V–5.5 V at 0 – 10 A.
Programmable dynamic output voltage positioning for
better load transient response
Choice of 500 kHz switching for highest efficiency or 1
MHz for lowest ripple noise.
Flexible Fault Response features
Multiple turn-on/off slew rates and delays
Digital Filter Compensation
Synchronous operation with other supplies
Real time performance monitoring
GUI based configuration for short development time.
Industry standard size through-hole single-in-line package:
30.7 x 25.3 x 6.00 mm (1.2 x 1.0 x 0.24 in)
Approved to the latest edition and amendment of ITE
Safety standards, UL/CSA 60950-1 and IEC60950-1
DP8110G
2
1.
ABSOLUTE MAXIMUM RATINGS
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect longterm reliability and cause permanent damage to the converter.
PARAMETER
CONDITIONS / DESCRIPTION
MIN
MAX
UNITS
Inductor Temperature
Input Voltage applied
-40
125
C
Input Voltage
250 ms Transient
Output Current
(See Output Current De-rating Curves)
2.
-8
15
VDC
10
ADC
ELECTRICAL SPECIFICATIONS
Specifications apply at the input voltage from 8 V to 14 V, output load from 0 to 5 A, ambient temperature from
-40°C to 85°C. Test conditions include an output filter with 2 x 330F 20mΩ solid electrolytic plus 1 x 22F X7R
ceramic output capacitors, unless otherwise noted.
2.1.
INPUT SPECIFICATIONS
PARAMETER
CONDITIONS / DESCRIPTION
MIN
Input Voltage (VIN)
Input Current (at no load)
Undervoltage Lockout
VLDO Input Current
2.2.
NOM
8
VIN = 14.0 V, VOUT = 3.3 V
MAX
UNITS
14
VDC
50
Ramping Up
Ramping Down
Current drawn from the external low voltage
supply at VLDO = 8 V
mADC
7.5
5
50
VDC
VDC
mADC
OUTPUT SPECIFICATIONS
PARAMETER
DESCRIPTION / CONDITION
Output Voltage Range (VOUT)
MIN
0.7
Output Voltage Setpoint Resolution
Output Voltage Setpoint Accuracy
NOM
MAX
UNIT
5.5
VDC
2.5 mV (1LSB)
2nd Vo Loop Enabled
±(0.6% + 5 mV)
Output Current (IOUT)
VIN MIN to VIN MAX
Line Regulation
VIN MIN to VIN MAX
±0.3
%VOUT
Load Regulation
0 to IOUT MAX
±0.2
%VOUT
Dynamic Regulation
Peak Deviation
Settling Time
Slew rate 1 A/s, 50 -75% load step
FSW = 500 kHz to 10% of peak deviation
See Output Load Transient Section
50
mV
60
10
20
40
18
35
50
20
500
500/1000
90.5
s
mV
mV
mV
mV
mV
mV
ppm/°C
kHz
kHz
%
%
Output Voltage Peak-to-Peak
Ripple and Noise
Scope BW = 20 MHz
Full Load
Temperature Coefficient
Switching Frequency
Duty Cycle Limit
VIN = 8.0 V, VOUT = 0.7 V
VIN = 8.0 V, VOUT = 2.5 V
VIN = 8.0 V, VOUT = 5.5 V
VIN = 14 V, VOUT = 0.7 V
VIN = 14 V, VOUT = 2.5 V
VIN = 14 V, VOUT = 5.5 V
VIN = 12 V, IOUT = 0.5 × IOUT MAX
Default
Programmable to
Default
Programmable, 1.56% steps
-5.5
1
3.125
7
100
ADC
1
At negative (sink) output current (bus terminator mode) the efficiency of the DP8110 degrades resulting in increased internal
power dissipation and switching noise. Therefore maximum allowable negative current under specific conditions is lower than the
current determined from the de-rating curves shown in paragraph.
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DP8110G
2.3.
3
PROTECTION SPECIFICATIONS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Output Overcurrent Protection
Type
Threshold
Default
Non-Latching, 130 ms period
Programmable
Latching / Non-Latching
Default
132
Programmable in 11 steps
Threshold Accuracy
%IOUT
36
132
%IOUT
-20
+20
%IOCP.SET
Output Overvoltage Protection
Type
Threshold
Threshold Accuracy
Default
Non-Latching, 130 ms period
Programmable
Latching / Non-Latching
Default
130
Programmable in 10% steps
Measured at VO.SET = 2.5 V
%VO.SET
110
130
-2
+2
%VO.SET
%VOVP.SE
T
Delay
Turn Off Behavior2
From instant when threshold is exceeded
until the turn-off command is generated
Default
μs
6
Emergency Off
Programmable to
Critical Off / Emergency Off
Output Undervoltage Protection
Type
Threshold
Threshold Accuracy
Delay
Turn Off Behavior2
Default
Non-Latching, 130 ms period
Programmable
Latching / Non-Latching
Default
75
%VO.SET
Programmable in 5% steps
75
90
Measured at VO.SET=2.5V
-2
2
From instant when threshold is exceeded
until the turn-off command is generated
Default
%VO.SET
%VOVP.SE
T
μs
6
Sequenced Off
Programmable to
Sequenced / Critical Off
Overtemperature Protection
Type
Turn Off Threshold
Turn On Threshold
Default
Non-Latching, 130 ms period
Programmable
Latching / Non-Latching
Temperature is increasing
Temperature is decreasing after the module
was shut down by OTP3
Threshold Accuracy
Delay
Turn Off Behavior2
120
C
110
C
-5
From instant when threshold is exceeded
until the turn-off command is generated
Default
C
5
μs
6
Sequenced Off
Programmable to
Sequenced / Critical Off
Tracking Protection (when Enabled)
Type
Threshold
Default
Disabled
Programmable
Latching/Non-Latching,130ms
Enabled during output voltage ramping up
Threshold Accuracy
Delay
-50
From instant when threshold is exceeded
until the turn-off command is generated
6
250
mVDC
50
mVDC
μs
2
Sequenced Off: The turn-off follows the turn-off delay and slew-rate settings; Critical Off: At turn-off both low and high switches
are immediately disabled; Catastrophic Off: At turn-off the high side switch is disabled and the low side switch is enabled.
3
OTP clears when Overtemp Warning (Status Register TW bit) turns off.
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DP8110G
4
Overtemperature Warning
Threshold
Threshold Accuracy
Always enabled, reported in Status register
(TW bit)4
From Nominal Set Point
C
110
-5
Hysteresis
+5
C
C
1.7
Power Good Signal (PG pin)
Logic
Lower Threshold
Upper Threshold
Threshold Accuracy
PG On Delay5
VOUT is inside the PG window
High
VOUT is outside the PG window
Low
Default
Programmable in 5% steps
Default
%VO.SET
95
110
%VO.SET
%VO.SET
Programmable in 5% steps
105
110
%VO.SET
Measured at VO.SET = 2.5 V
-2
2
%VO.SET
Default
Programmable at
Default
PG Off Delay
Programmable same as PG On Delay
2.4.
90
90
0
ms
0, 10, 50, 150
PG disabled when
VOUT ≤ VUV threshold
PG disabled at turn-off
command (Reset function)
ms
FEATURE SPECIFICATIONS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNITS
Current Share
Type
Maximum Number of Modules
Connected in Parallel
Current Share Accuracy
Active, Single Line
IOUT ≥ 0
4
IOUT ≥ 20% IOUT NOM
±20
%IOUT
Interleave
Interleave (Phase Shift)
Default
Programmable in 22.5 steps
0
0
Degree
337.5
Degree
Sequencing6
Turn ON Delay
Turn OFF Delay
Default
Programmable in 1ms steps
0
0
Default
Programmable in 1ms steps
ms
255
0
0
ms
ms
63
ms
Tracking
Turn ON Slew Rate
Turn OFF Slew Rate
Default
Programmable in 8 steps
0.05
Default
Programmable in 8 steps
V/ms
2.07
0.05
-0.05
V/ms
-2.07
-0.05
V/ms
V/ms
Optimal Voltage Positioning
Load Regulation
Default
Programmable in 7 steps
0
mV/A
0
2.45
0.01
2
mV/A
Feedback Loop Compensation
Proportional (Kr)
Programmable
4
Temp. Warning error same sign and proportional with OTP error.
From instant when threshold is exceeded until status of PG signal changes high
6
Timing based on SD clock and subject to tolerances of SD.
7
Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment. See Rising and Falling
Slew Rates.
5
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DP8110G
5
Integral (Ti)
Programmable
1
100
µs
Differential (Td)
Programmable
1
100
µs
Differential Roll-Off (Tv)
Programmable
1
100
µs
Monitoring
Voltage Monitoring Accuracy
12 Bit Resolution over 0.5…5.5V
-0.5
0.5
%
Current Monitoring Accuracy
20%×IOUT NOM < IOUT < IOUT NOM
-20
+20
%IOUT
Temperature Monitoring Accuracy
Junction temperature of dPOL controller
-5
+5
C
Remote Voltage Sense (+VS and –VS pins)8
Voltage Drop Compensation
Between +VS and VOUT
300
mV
Voltage Drop Compensation
Between -VS and PGND
100
mV
2.5.
SIGNAL SPECIFICATIONS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNITS
VDD
Logic In Max
Internal supply voltage
Pull Up Logic max safe input
3.15
3.3
3.45
VDD+.5
V
V
0.3
475
0.3 x VDD
VDD + 0.5
0.45 x VDD
60
300
10
1.0
525
V
V
V
mA
ns
pF
mA
kHz
% of clock
cycle
% of clock
cycle
SYNC/DATA Line (SD pin)
ViL_sd
ViH_sd
Vhyst_sd
VoL
Tr_sd
Cnode_sd
Ipu_sd
Freq_sd
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current @ 0.5V
Maximum allowed rise time 10/90%VDD
Added node capacitance
Pull-up current source at Vsd=0V
Clock frequency of external SD line
-0.5
0.75 x VDD
0.25 x VDD
14
Tsynq
Sync pulse duration
22
28
T0
Data=0 pulse duration
72
78
-0.5
0.7 x VDD
0.1 x VDD
0.3 x VDD
VDD+0.5
0.3 x VDD
V
V
V
10
kOhm
5
Inputs: ADDR0…ADDR4, EN, IM
ViL_x
ViH_x
Vhyst_x
RdnL_ADDR
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
External pull down resistance
ADDRX forced low
Power Good and OK Inputs / Outputs
Iup_PG
Iup_OK
ViL_x
ViH_x
Vhyst_x
IoL
Pull-up current source input forced low PG
Pull-up current source input forced low OK
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
25
175
-0.5
0.7 x VDD
0.1 x VDD
4
110
725
0.3 x VDD
VDD+0.5
0.3 x VDD
20
μA
μA
V
V
V
mA
Pull-up current source at VCS = 0V
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
Maximum allowed rise time 10/90% VDD
0.84
-0.5
0.75 x VDD
0.25 x VDD
14
3.1
0.3 x VDD
VDD+0.5
0.45 x VDD
60
100
mA
V
V
V
mA
ns
Current Share Bus (CS pin)
Iup_CS
ViL_CS
ViH_CS
Vhyst_CS
IoL
Tr_CS
8
For remote sense, it is recommended to place a 0.01-0.1μF ceramic capacitor between +VS and –VS pins as close to the dPOL
converter as possible.
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BCD.00262_D
DP8110G
6
3.
PIN ASSIGNMENTS AND DESCRIPTIONS
PIN NAME
PIN NUMBER
PIN TYPE
BUFFER TYPE
PIN DESCRIPTION
OK
8
I/O
PU
Fault/Status Condition
SD
9
I/O
PU
Sync/Data Line
NOTES
Connect to OK pin of other dPOLs
and/or DPM. Leave floating, if not used
Connect to SD pin of DPM
PG
6
I/O
PU
Power Good
Pin state reflected in Status Register.
ADDR4
10
I
PU
dPOL Address Bit 4
Tie to GND for 0 or leave floating for 1
ADDR3
5
I
PU
dPOL Address Bit 3
Tie to GND for 0 or leave floating for 1
ADDR2
4
I
PU
dPOL Address Bit 2
Tie to GND for 0 or leave floating for 1
ADDR1
3
I
PU
dPOL Address Bit 1
Tie to GND for 0 or leave floating for 1
ADDR0
2
I
PU
dPOL Address Bit 0
Tie to GND for 0 or leave floating for 1
VOUT
1
P
Output Voltage
GND
7
P
Power Ground
VIN
11
P
Input Voltage
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
4.
TYPICAL PERFORMANCE CHARACTERISTICS
4.1.
THERMAL DERATING CURVES
Figure 2. Available output current vs. ambient air
temperature and airflow rates for converter DP8110G
mounted horizontally with air flowing from input to output,
MOSFET temperature 120 C, Vin = 12 V, Vout = 5 V, and
Fsw= 1MHzw
12
12
10
10
Load Current [Adc]
Load Current [Adc]
Figure 1. Available output current vs. ambient air
temperature and airflow rates for converter DP8110G
mounted horizontally with air flowing from input to output,
MOSFET temperature 120 C, Vin = 12 V, Vout = 5 V, and
Fsw= 500KHz
8
6
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
4
2
8
6
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
4
2
0
20
30
40
50
60
70
Ambient Temperature [°C]
80
90
0
20
30
40
50
60
70
80
90
Ambient Temperature [°C]
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DP8110G
4.3.
7
EFFICIENCY CURVES
Figure 3. Efficiency vs. Load. Vin=12V, Fsw=500kHz
Figure 4 Efficiency vs. Load. Vin=12V, Fsw=1MHz
Figure 5. Efficiency vs. Output Voltage, Iout=10A,
Fsw=500kHz and Fsw=1MHz
Figure 6 Efficiency vs Vout, Vin=12, Load=10A
Figure 7 Efficiency vs Vin, Load=10A, Fsw=500KHz
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DP8110G
8
4.5.
DISSIPATION
Figure 8. Dissipation vs Load. Vin=12V, Fsw=500kHz
5.
Figure 9 Dissipation vs Load, Vin=12V, Fsw=1MHz
PROGRAMMABLE FEATURES
Performance parameters of DP8110G dPOL converters are programmed by the system DPM over a self-clocking
single wire bus as need. Each parameter is stored in FLASH memory in the DPM and loaded into volatile memory
registers in the dPOL control chip detailed in Table 1. Setup registers 00h through 14h are programmed at the
system power-up. When the input voltage is removed, the dPOL controller's default values are restored.
Table 1. DP8110G Memory Registers
CONFIGURATION REGISTERS
Name
Register
PC1
Protection Configuration 1
PC2
Protection Configuration 2
PC3
Protection Configuration 3
TC
Tracking Configuration
INT
Interleave and Frequency Configuration
DON
Turn-On Delay
DOF
Turn-Off Delay
VLC
Voltage Loop Configuration
CLS
Current Limit Set-point
DCL
Duty Cycle Limit
PC4
Protection Configuration 4
V1H
Output Voltage Setpoint 1 (Low Byte)
V1L
Output Voltage Setpoint 1 (High Byte)
V2H
Output Voltage Setpoint 2 (Low Byte)
V2L
Output Voltage Setpoint 2 (High Byte)
V3H
Output Voltage Setpoint 3 (Low Byte)
V3L
Output Voltage Setpoint 3 (High Byte)
CP
Controller Proportional Coefficient
CI
Controller Integral Coefficient
CD
Controller Derivative Coefficient
B1
Controller Derivative Roll-Off Coefficient
STATUS REGISTERS
Name
Register
RUN
Run enable / status
ST
Status
MONITORING REGISTERS
Name
VOH
VOL
IO
TMP
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
Address
0x15
0x16
Register
Output Voltage High Byte (Monitoring)
Output Voltage Low Byte (Monitoring)
Output Current (Monitoring)
Temperature (Monitoring)
Address
0x17
0x27
0x18
0x19
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DP8110G
9
DP8110G converters can be programmed using the Graphical User Interface or directly via the I2C bus by using high
and low level commands as described in the “DPM Programming Manual”.
DP8110G parameters can be reprogrammed at any time during the system operation and service except for the digital
filter coefficients, the switching frequency and the duty cycle limit, that can only be changed when the dPOL output
is turned off.
5.1.
OUTPUT VOLTAGE
The output voltage can be programmed in the GUI Output Configuration window shown in the Figure 10 or directly
via the I2C bus by writing into the VOS register shown in Figure 11.
Figure 10. Output Configuration Window
Note that the GUI shows the effect of setting PG, OV and UV limits as both values and graphical limit bars. Vertical
hashed lines are error bars for the Overcurrent (OC) limit.
5.1.1.
Output Voltage Setpoint
The output voltage programming range is from 0.7 V to 5.5 V. The resolution is constant across the range and is 2.5
mV. A Total of 3 registers are provided: one should be used for the normal setpoint voltage; the other two can be used
to define a low/high margining voltage setpoint. Note that each register is 16bit wide and that the high byte needs
always to be written / read first. The writing of the low byte triggers the refresh of the whole 16bit register (the high
byte is written to a shadow register).
Unlike other configuration registers, the dPOL controller's VOS registers are dynamic. Changes to VOS values can be
made while the output is enabled over the I2C bus through register bypass commands and the POL will change its
output immediately.
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DP8110G
10
Figure 11. Output Voltage Setpoint Register VOS
VOS: Output Voltage Set-Point
Address: 0x0B … 0x10
Coefficient
V1H
First Vo Setpoint High Byte
V1L
First Vo Setpoint Low Byte
V2H
Second Vo Setpoint High Byte
V2L
Second Vo Setpoint Low Byte
V3H
Third Vo Setpoint High Byte
V3L
Third Vo Setpoint Low Byte
Mapping:
- 12 bit data word, left aligned
- 1LSB = 2.5mV
5.1.2.
Addr
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Bits
8
8
8
8
8
8
Default
Note:
- all registers are readable and writeable
- always write and read the high byte first
Output Voltage Margining
If the output voltage needs to be varied by a certain percentage, the margining function can be utilized. The margining
can be programmed in the dPOL Configuration window or directly via the I2C bus using high level commands as
described in the “DM7300 Digital Power Manager Programming Manual”.
In order to properly margin dPOLs that are connected in parallel, the dPOLs must be members of one of the Parallel
Buses. Refer to the GUI System Configuration Window shown in Figure 50.
5.1.3.
Output Load Regulation Control
When Load Regulation is programmed to be non-zero, the output voltage will decrease as the output current
increases, so the VI characteristic will have a negative slope at the point of regulation. This can be programmed in the
GUI Output Configuration window shown in Figure 10. In the DP8110G Load Regulation can be set to one of eight
values: 0, 0.74, 1.49, 2.23, 2.79, 3.71, 4.46, or 5.2 mv/A.
Figure 12. Optimal Voltage Positioning Concept
VOUT
Upper Regulation
Limit
Lower Regulation
Limit
Operating
Point
VI Curve Without
Load Regulation
VI Curve With
Load Regulation
Headroom without
Load Regulation
Headroom with
Load Regulation
Light
Load
IOUT
Heavy
Load
Figure 13 shows a DP8110G POL with 0 mv/A (load current) regulation. Alternating high and low output load currents
causes large transients in Vout to appear with each change.
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DP8110G
11
Figure 13 Transient Response with Regulation
set to 0 mV/A.
Figure 14 Transient response with non-zero Regulation.
As the Load Regulation parameter is increased, step offsets in output voltage begin to appear, as shown in Figure 14
with non-zero Regulation.
5.2.
SEQUENCING AND TRACKING
Turn-on delay, turn-off delay, and rising and falling output voltage slew rates can be programmed in the dPOL
Configure Sequencing window shown in Figure 15 or directly via the I2C bus by writing into the DON, DOF, and TC
registers, respectively. The registers are shown in Figure 16, Figure 18, and Figure 19.
Figure 15. dPOL Configure Sequencing Window
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DP8110G
12
5.2.2.
Turn-On Delay
Turn-on delay is defined as an interval from the application of the Turn-On command until the output voltage starts
ramping up.
Figure 16. Turn-On Delay Register DON
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DON7
DON6
DON5
DON4
DON3
DON2
DON1
DON0
Bit 7
Bit 0
Bit 7:0 DON[7:0]: Turn-on delay time
00h: corresponds to 0ms delay after turn-on command has occurred
…
FFh: corresponds to 255ms delay after turn-on command has occurred
5.2.3.
Turn-Off Delay
Turn-off delay is defined as an interval from the application of the Turn-Off command until the output voltage reaches
zero (if the falling slew rate is programmed) or until both high side and low side switches are turned off (if the slew rate
is not programmed). Therefore, for the slew rate controlled turn-off the ramp-down time is included in the turn-off
delay as shown in Figure 17.
Figure 17. Relationship between Turn-Off Delay and Falling Slew Rate
User programmed turn-off delay, T DF
Turn-Off
Command
Internal
ramp-down
command
Calculated
delay T D
Ramp-down time, T F
Ramp-down time, TF
VOUT
Falling slew
rate dVF/dT
Time
As it can be seen from the figure, the internally calculated delay TD is determined by the equation below.
TD = TDF −
VOUT
,
dVF
dT
For proper operation TD shall be greater than zero. The appropriate value of the turn-off delay needs to be programmed
to satisfy the condition.
If the falling slew rate control is not utilized, the turn-off delay only determines an interval from the application of the
Turn-Off command until both high side and low side switches are turned off. In this case, the output voltage rampdown process is determined by load parameters.
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DP8110G
13
Figure 18. Turn-Off Delay Register DOF
DOF: Turn-Off Delay Configuration
Address: 0x06
5.3.
U
U
--Bit 7
---
R/W0
DOF5
R/W0
DOF4
R/W1
DOF3
Bit
7:6
Unimplemented: read as ‘0’
Bit
5:0
DOF[5:0]: Turn-Off delay in ms
0x00 = 0ms
0x01 = 1ms
…
0x0B = 11ms (default)
…
0x3F = 63ms
R/W0
DOF2
R/W1
DOF1
R/W-1
DOF0
Bit 0
TURN-ON CHARACTERISTICS
Once delays are accounted for, turn-on and turn-off characteristics are simply a function of slew rates, which are
selectable.
5.3.1.
Rising and Falling Slew Rates
Output voltage ramp up (and down) control is accomplished by programming the rising and falling slew rates of the
output voltage, supported in the GUI as shown in Figure 15, which is implemented by the DPM through writing data
to the TC register, Figure 19.
To achieve programmed slew rates, the output voltage is being changed in 10mV steps where duration of each step
determines the slew rate. For example, ramping up a 1.0V output with a slew rate of 0.5V/ms will require 100 steps
duration of 20μs each.
Duration of each voltage step is calculated by dividing the master clock frequency generated by the DPM. Since all
dPOLs in the system are synchronized to the master clock, the matching of voltage slew rates of different outputs is
very accurate as it can be seen in Figure 20 and Figure 25.
During the turn on process, a dPOL not only delivers current required by the load (I LOAD), but also charges the load
capacitance. The charging current can be determined from the equation below:
ICHG = CLOAD dVR
dt
Where, CLOAD is load capacitance, dVR/dt is rising voltage slew rate, and ICHG is charging current.
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Figure 19. Tracking Configuration Register TC
TC: Tracking Configuration
Address: 0x03
U
--Bit 7
Bit 7
Bit 6:4
R/W-0
R2
R/W-0
R1
R/W-1
R0
R/W-1
SC
R/W-1
F2
R/W-0
F1
R/W-0
F0
Bit 0
Unimplemented: read as ‘0’
R[2:0]: Vo rising slew rate
0 = 0.05 V/ms (default when in bus terminator mode)
1 = 0.1 V/ms (default)
2 = 0.2 V/ms
3 = 0.25 V/ms
4 = 0.5 V/ms
5 = 1.0 V/ms
6 = 2.0 V/ms
7 = Reserved
Bit 3
SC: Turn-off slew rate control
0 = disabled
1 = enabled (default)
Bit 2:0
F[2:0]: Vo falling slew rate
0 = -0.05 V/ms
1 = -0.1 V/ms
2 = -0.2 V/ms
3 = -0.25 V/ms (default when in bus terminator mode)
4 = -0.5 V/ms (default)
5 = -1.0 V/ms
6 = -2.0 V/ms
7 = Reserved
When selecting the rising slew rate, a user needs to ensure that
ILOAD + ICHG IOCP
Where IOCP is the overcurrent protection threshold of the dPOL. If the condition is not met, then the overcurrent
protection will be triggered during the turn-on process. To avoid this, dVR/dt and the overcurrent protection threshold
should be programmed to meet the condition above.
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5.3.2.
15
Delay and Slew Rate Combination
The effect of setting slew rates and turn on/off delays is illustrated in the following sets of figures.
Figure 20. Tracking Turn-On. Rising Slew Rate is
Programmed at 0.5V/ms for each output.
Figure 21. Turn-On with Different Rising Slew Rates. Rising
Slew Rates are V1-1V/ms, V2-0.5V/ms, V3-0.2V/ms.
Figure 22. Sequenced Turn-On. Rising Slew Rate is
Programmed at 1V/ms. V2 Delay is 2ms, V3 delay is 4ms.
Figure 23 Two outputs delayed 5ms. All slew rates at
0.5V/ms.
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5.3.3.
Pre-Bias
In some applications, power may "leak" from a powered circuit to an unpowered bus, typically through ESD protection
diodes. The d-pwer® controller in the DP8110G holds off turn on its output until the desired ramp up point crosses
the pre-bias point, as seen in Figure 24.
Figure 24. Turn On into Prebiased Load. V3 is Prebiased by V2 via a Diode.
Figure 24 was captured with an actual system where a diode was added to pre-bias a 1.5V bus from a 1.85V bus in
order to simulate the effect of current leakage through protection circuits of unpowered logic connected to powered
logic outputs (a common source of pre-bias in power systems).
5.4.
TURN-OFF CHARACTERISTICS
Turn of captures show that combining turn off delays and ramp rates. Note that while turnoff delays have a lower
upper time limit as compared to turn on delays, all ramp down rates are available independently to turn on and off.
Figure 25. Tracking Turn-Off. Falling Slew Rate is
Programmed at 0.5V/ms.
Figure 26. Turn-Off with Tracking and Sequencing. Falling
Slew Rate is Programmed at 0.5V/ms
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5.6.
17
FAULTS ERRORS AND WARNINGS
All dPOL series converters have a comprehensive set of programmable fault and error protection functions that can
be classified into three groups based on their effect on system operation: warnings, faults, and errors. These are
warnings, errors and faults. Warnings include Thermal (Overtemperature limit near) and Power Good (a warning in a
negative sense.)
Faults in DP7xxx and DP8xxx series dPOLs include overcurrent protection, overvoltage, overtemperature and tracking
failure detection. Errors include only undervoltage. Control of responses to Faults and Errors are distributed between
different dPOL registers and are configurable in the GUI.
Thresholds of overcurrent, over- and undervoltage detection, and Power Good limits can be programmed in the GUI
Output Configuration window (Figure 10) or directly via the I2C bus by writing into the PC2 registers shown in Fig. 27.
Figure 27. Protection Configuration Register PC2
PC2: Protection Configuration Register 2 1)
Address: 0x01
U
--Bit 7
U
---
R/W-0
PGHL
R/W-0
PGLL
R/W-1
OVPL1
R/W-0
OVPL0
R/W-0
UVPL1
R/W-0
UVPL0
Bit 0
Bit7:6
Unimplemented: read as ‘0’
PGHL: Power Good High Level
Bit 5
1 = 105% of Vo
0 = 110% of Vo (default)
PGLL: Power Good Low Level
Bit 4
1 = 95% of Vo
0 = 90% of Vo (default)
OVPL: Over Voltage Protection Level
00 = 110% of Vo
Bit 3:2
01 = 120% of Vo
10 = 130% of Vo (default)
11 = 130% of Vo
UVPL: Under Voltage Protection Level
00 = 75% of Vo (default)
Bit 1:0
01 = 80% of Vo
10 = 85% of Vo
11 = 90% of Vo
1)
This register can only be written when PWM is not active (RUN[RUN] is ‘0’)
Note that the overvoltage and undervoltage protection thresholds and Power Good limits are defined as percentages
of the output voltage. Therefore, the absolute levels of the thresholds change when the output voltage setpoint is
changed either by output voltage adjustment or by margining.
Overcurrent limits are set either in the GUI POL Output configuration dialog or in the POL's CLS register as shown in
Figure 28.
Note that the CLS register includes bits which control the Regulation option settings. When writing into this register
be careful to not change Regulation by accident.
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Figure 28. Current Limit Setpoint Register CLS
CLS: Current Limit Setting
Address: 0x08
R/W-0
LR2
Bit 7
Bit 7:5
Bit 4
Bit 3:0
5.6.1.
R/W-0
LR1
R/W-0
LR0
R/W-1
TCE
R/W-1
CL3
R/W-0
CL2
R/W-1
CL1
R/W-1
CL0
Bit 0
LR[2:0]: Load Regulation setting
0 = 0 V/A/Ω (default)
1 = 0.39 V/A/Ω
2 = 0.78 V/A/Ω
3 = 1.18 V/A/Ω
4 = 1.57 V/A/Ω
5 = 1.96 V/A/Ω
6 = 2.35 V/A/Ω
7 = 2.75 V/A/Ω
TCE: Temperature Compensation for Current Limitation Enable
0 = disabled
1 = enabled (default)
CLS[3:0]: Current Limit set-point when Vo Stationary or Falling
0x0 = 37%
0x1 = 47%
…
0xB = 140% (default)
values higher than 0xB are translated to 0xB (140%)
Warnings
This group includes Overtemperature Warning and Power Good Signal. Warnings do not turn off dPOLs but rather
generate signals that can be transmitted to a host controller via the I2C bus.
5.6.1.1. Overtemperature Warning
The Overtemperature Warning is generated when temperature of the controller exceeds 120°C. The Overtemperature
Warning changes the TW bit of the status register ST. When the temperature falls below 117°C, the PT bit is cleared
and the Overtemperature Warning is removed.
5.6.1.2. Power Good
Power Good (PG) is an open collector output that is pulled low, if the output voltage is outside of the Power Good
window. The window is formed by the Power Good High threshold that is programmable at 105 or 110% of the output
voltage and the Power Good Low threshold that can be programmed at 90 or 95% of the output voltage.
Power Good protection is only enabled after the output voltage reaches its steady state level. A programmable delay
can be set between 0 and 150ms to delay the release of the PG pin after the voltage has reached the steady state
level (see Figure 15). This allows using the PG pin to reset load circuits properly. The Power Good protection remains
active during margining voltage transitions. The threshold will vary proportionally to the voltage change (see Figure
29).
The Power Good Warning pulls the PG pin low and changes the PG bit of the status register ST to 0. When the
output voltage returns within the Power Good window, the PG pin is released high, the PG bit is cleared and the
Power Good Warning is removed. The Power Good pin can also be pulled low by an external circuit to initiate the
Power Good Warning.
At turn-off the PG pin can be programmed to either be pulled low immediately following the turn-off command, or
then when the voltage actually starts to ramp down (Reset vs. Power Good functionality in Figure 15).
NOTE: To retrieve status information, Status Monitoring in the GUI DPM Configure Devices window should be enabled
(refer to Digital Power Manager Data Sheet). The DPM will retrieve the status information from each dPOL on a
continuous basis.
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5.6.3.
19
Faults
This group includes overcurrent, overtemperature, undervoltage, and tracking protections. Triggering any protection
in this group will turn off the dPOL.
5.6.3.1. Overcurrent Protection
Overcurrent protection is active whenever the output voltage of the dPOL exceeds the prebias voltage (if any). When
the output current reaches the OC threshold, the POL control chip asserts an OC fault. The dPOL sets the OC bit in
the register ST to 0. Both high side and low side switches of the dPOL are turned off instantly (fast turn-off).
Current sensing is across the dPOLs choke. To compensate for copper winding TC, compensation is added to keep
the OC threshold approximately constant at temperatures above room temperature. Note that the temperature
compensation can be disabled in the dPOL Configure Output window or directly via the I2C by writing into the CLS
register. However, it is recommended to keep the temperature compensation enabled.
5.6.3.2. Undervoltage Protection
The undervoltage protection is only active during steady state operation of the dPOL to prevent nuisance tripping. If
the output voltage decreases below the UV threshold and there is no OC fault, the UV fault signal is generated, the
dPOL turns off, and the UV bit in the register ST is changed to 0. The output voltage is ramped down according to
sequencing and tracking settings (regular turn-off).
5.6.3.3. Overtemperature Protection
Overtemperature protection is active whenever the dPOL is powered up. If temperature of the controller exceeds
130°C, the OT fault is generated, dPOL turns off, and the OT bit in the register ST is changed to 0. The output voltage
is ramped down according to sequencing and tracking settings (regular turn-off).
If non-latching OTP is programmed, the dPOL will restart as soon as the temperature of the controller decreases
below the Overtemperature Warning threshold of 120°C.
5.6.3.4. Tracking Protection
Ramp up and down operations are under control by the dPOL. Tracking protection, however, is active only when the
output voltage is ramping up. The purpose of the protection is to ensure that the voltage differential between multiple
rails being tracked does not exceed 250mV. This protection eliminates the need for external clamping diodes between
different voltage rails which are frequently recommended by ASIC manufacturers.
When the tracking protection is enabled, the dPOL continuously compares actual value of the output voltage to its
programmed value as defined by the output voltage and its rising slew rate. If absolute value of the difference exceeds
250mV, the tracking fault signal is generated, the dPOL turns off, and the TR bit in the register ST is changed to 0.
Both high side and low side switches of the dPOL are turned off instantly (fast turn-off).
The tracking protection can be disabled, if it contradicts requirements of a particular system (for example turning into
high capacitive load where rising slew rate is not important). It can be disabled in the dPOL Configure Fault window
or directly via the I2C bus by writing into the PC1 register.
5.6.4.
Faults and Margining
As noted earlier, UV and OV protection settings are a percentage of Vout. As Vout ramps between nominal, low or
high margin values, UVP and OVP limits adjust accordingly. This is illustrated in Figure 29. The middle plot of Vo
(Vout) level is the result of a Low Margining command. Note that Tracking is not re-enabled during changes to Vout
from margining commands.
Figure 29. Protection Enable Conditions
Vo
RUN
OC enabled
PG enabled
Vo_Rise
H
K_
TR
1.0V
pre-biased output
L
K_
TR
Vo_Stable
Vo_Fall
Vo_Stable
Vo_Rise
Vo_Stable
OVP Limit
OVP Limit
PG High Limit
PG High Limit
Vo
OVP Limit
PG High Limit
PGLow Limit
UVP Limit
Vo_Fall
PGLow Limit
PGLow Limit
UVP Limit
UVP Limit
Time
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5.6.5.
Errors
This protection group includes only overvoltage protection.
5.6.5.1. Overvoltage Protection
The overvoltage protection is active whenever the output voltage of the dPOL exceeds the pre-bias voltage (if any). If
the output voltage exceeds the overvoltage protection threshold, the overvoltage error signal is generated, the dPOL
turns off, and the OV bit in the register ST is changed to 0. The high side switch is turned off instantly, and
simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads. The low side switch
provides low impedance path to quickly dissipate energy stored in the output filter and achieve effective voltage
limitation. The OV threshold can be programmed from 110% to 130% of the output voltage setpoint, but not lower
than 0.5V. Also the OV threshold will always be at least 0.25V above the setpoint.
5.6.6.
Fault and Error Latching
The user has the option of setting up any protection option as either latching/non-latching and propagating or nonpropagating. Propagation and Latching for each POL is set in the GUI (Figure 30 below) or directly via the I2C by
writing into the PC1 register shown in Figure 31.
Figure 30. GUI dPOL Fault Propagation Option Window
If the non-latching protection is selected, a dPOL will attempt to restart every 130ms until the condition that
triggered the protection is removed. When restarting, the output voltages follow tracking and sequencing settings.
If the latching type is selected, a dPOL will turn off and stay off. The dPOL can be turned on after 130ms, if the
condition that caused the fault is removed and the respective bit in the ST register was cleared, or the Turn On
command was recycled, or the input voltage was recycled.
Figure 31. Protection Configuration Register PC1
PC1: Protection Configuration Register 1
Address: 0x00
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
TRE
PVE
TRC
OTC
OCC
Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W-0
UVC
R/W-1
OVC
R/W-1
PVC
Bit 0
TRE: Tracking fault enable
1 = enabled
0 = disabled
PVE: Phase voltage error enable
1 = enabled
0 = disabled
TRC: Tracking Fault Protection Configuration
1 = latching
0 = non-latching
OTC: Over Temperature Protection Configuration
1 = latching
0 = non-latching
OCC: Over Current Protection Configuration
1 = latching
0 = non- latching
UVC: Under Voltage Protection Configuration
1 = latching
0 = non- latching
OVC: Over Voltage Protection Configuration
1 = latching
0 = non- latching
PVC: Phase Voltage Protection Configuration
1 = latching
0 = non- latching
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5.6.7.
21
Fault and Error Turn Off Control
In the GUI dPOL Fault dialog is a column of spin controls which set the Turn-Off style OT, UV and OV events. The
choices are defined as:
Sequenced: Outputs shut down according to ramp down rate control settings. This is the method used when a dPOL
is told to do a normal, controlled shut down.
Critical: Both high side and low side switches of the dPOL are turned off instantly.
Emergency: The high side switch is turned off instantly, and simultaneously the low side switch is turned on to ensure
reliable protection of sensitive loads.
5.6.8.
Fault and Error Status
Status of dPOL protection logic is stored in the dPOL's ST register shown in Figure 32.
When Status monitoring is enabled for a group, the DPM will read this register and make the information available for
uses such as GUI Monitor display.
Figure 32. Protection Status Register ST
ST: Status register
Address: 0x16
R-1
R-0
TW
PG
R/W-11) R/W-11) R/W-11) R/W-11) R/W-11) R/W-11)
TR
OT
OC
UV
OV
Bit 7
PV
Bit 0
Bit 7
TW: Temperature Warning
Bit 6
PG: Power Good Warning (high and low)
Bit 5
Bit 4
Bit 3
TR: Tracking Fault
OT: Over Temperature Fault
OC: Over Current Fault
Bit 2
UV: Under Voltage Fault
Bit 1
OV: Over Voltage Error
Bit 0
PV: Reserved
Note: an activated fault is encoded as ‘0’
1)
5.6.9.
Writing a ‘1’ into a fault/error bit clears a latching fault/error
Fault and Error Propagation
The feature adds flexibility to the fault management scheme by giving users control over propagation of fault signals
within and outside of the system. The propagation means that a fault in one dPOL can be programmed to turn off
other dPOLs and devices in the system, even if they are not directly affected by the fault
5.6.9.1. Fault Propagation
When propagation is enabled, the faulty dPOL pulls its OK pin low. This signals to the DPM and any other dPOL
connected to that signal, that the dPOL has a Fault or Error condition. A low OK line initiates turn-off of other dPOLs
connected to the same OK line with the same turn-off behavior as the faulty dPOL. The turn-off type is encoded into
the OK line when it transitions from high to low.
5.6.9.2. Grouping of dPOLs
d-pwer® dPOLs can be arranged in groups of up to 4, 8, 16 or 32 POLs (depending upon the DPM model used).
Membership in a group is set in the GUI in the DPM / Configure / Devices dialog, and implemented in hardware by
connecting the OK pins of each POL in the group to the matching OK input on the DPM.
In order for a particular Fault or Error to propagate through the OK line, Propagation needs to be checked in the GUI
POL Configure / Fault Management Window. This read in the dPOLs PC3 register shown in Figure 34.
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Figure 33. DPM Configure Faults Window
Note that the turn-off type of the fault as it propagates through the DPM will remain unchanged.
Propagation options for dPOLs can be read or set in the dPOL PC3 register shown in Figure 34.
Figure 34. Protection Configuration Register PC3
PC3: Protection Configuration Register 3
Address: 0x02
U
--Bit 7
Bit
7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U
---
R/W-1
TRP
R/W-1
OTP
R/W-1
OCP
R/W-1
UVP
R/W-1
OVP
R/W-1
PVP
Bit 0
Unimplemented: Read as ‘0’
TRP: Tracking Protection Propagation
0 = disabled
1 = enabled
OTP: Over Temperature Protection Propagation
0 = disabled
1 = enabled
OCP: Over Current Protection Propagation
0 = disabled
1 = enabled
UVP: Under Voltage Protection Propagation
0 = disabled
1 = enabled
OVP: Over Voltage Protection Propagation
0 = disabled
1 = enabled
PVP: Reserved
5.6.9.3. Front End and Crowbar
If an error is propagated to at least the Group level, the DPM can also be configured to generate commands to turn
off a front end (a DC-DC converter generating the intermediate bus voltage) and to trigger an optional crowbar
protection to accelerate removal of the IBV voltage.
5.6.9.4. Propagation Process
Understanding Fault and Error propagation is easier with the following examples.
The First example is of of non-propagation from a dPOL, as shown in Figure 35. An undervoltage error shuts down
the Vo, but since propagation was not enabled, OK-A is not pulled down and Vo2 stays up.
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Figure 35. No Group Fault Propagation
23
Figure 36. Turn-On into UVP on V3. The UV Fault Is
Programmed To Be Non-Latching. Ch1 – Vo1, Ch2 –
Vo2(Group A), Ch3 – Vo3 (Group B) Vo4 not shown.
Figure 36 shows a scope capture an actual system when undervoltage error detection is set to not propagate.
In this example, the dPOL connected to scope Ch 1 encounters the undervoltage fault after turn-on. Because fault
propagation is not enabled for this POL, it alone turns off and generates the UV fault signal. Because a UV fault
triggers the sequenced turn-off, the dPOL meets its turn-off delay and falling slew rate settings during the turn-off
process as shown in the trace for Ch1. Since the UV fault is programmed to be non-latching, the dPOL will attempt
to restart every 130 ms, repeating the process described above until the condition causing the undervoltage is
removed. The 130ms hiccup interval is guaranteed regardless of the turn-off delay setting.
The next example is intra-group propagation, the dPOL propagates its fault or error events. Here fault propagation
between POLs is enabled.
In Figure 37 the dPOL powering output Vo1 again encounters an undervoltage error. It pulls its OK line low. Since
the dPOL powering output Vo2 (Ch3 in the picture) belongs to the same group (A in this case), pulling down OKA tells that dPOL to execute a regular turn-off.
Figure 37 Intra Group Fault Propagation
Figure 38. Turn-On into UVP on V3. The UV Fault Is
Programmed To Be Non-Latching and Propagate From
Group C to Group A. Ch1 – V3 (Group C), Ch2 – V2, Ch3 –
V1 (Group A)
Since both Vo1 and Vo2 have the same delay and slew rate settings they will continue to turn off and on
synchronously every 130ms as shown in Figure 38 until the condition causing the undervoltage is removed.
Note that the dPOL powering the output Vo2 (Ch3) actually reaches its voltage set point before the error in Vo1 is
detected.
The turn-off type of a POL fault/error as propagated by the faulty dPOL via the OK line is propagated through the
DPM to other dPOLs connected to other Groups (per configuration in Figure 33 ) through its connection to their
OK line or lines.
This behavior assures that all dPOLs configured to be affected through Group linkages will switch off with the
same turn-off type.
A summary of protection support, their parameters and features are shown in Table 2.
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Table 2. Summary of Protection Parameters and Features
CODE
NAME
TYPE
WHEN ACTIVE
TURN
OFF
LOW SIDE
SWITCH
PROPAGATION
DISABLE
Warning
Whenever VIN is applied
No
N/A
Status Bit
No
PG
Temperature
Warning
Power Good
Warning
During steady state
No
N/A
PG
No
TR
Tracking
Fault
During ramp up
Fast
Off
Yes
OT
Overtemperature
Fault
Whenever VIN is applied
Regular
Off
Critical
Sequenced or
Critical
OC
Overcurrent
Fault
When VOUT exceeds
prebias
Fast
Off
Critical
No
TW
UV
OV
5.7.
Undervoltage
Overvoltage
Fault
During steady state
Regular
Off
Error
When VOUT exceeds
prebias
Fast
On
Sequenced or
Critical
Critical or
Emergency
No
No
No
OK FAULT AND ERROR CODING
d-pwer® dPOLs have an additional functionality added to the OK line signal. The OK line is used to propagate and
receive information from other devices in the power system belonging to the same group as to the kind of turn-off
procedure a device has initiated because of a fault.
Figure 39 shows the three types of OK encoding. The bubbles show when the SD and OK line logic levels are
sampled by dPOL and DPM logic.
Figure 39. OK Severity Encoding Waveforms
Note that the OK line state changes are always executed by dPOLs at the negative edge of the SD line.
The chart shows shut down response types as the user can select the kind of response desired for each type of
Fault or Error (within the limits of choice provided for each type of Fault or Error). All dPOL devices in the same
Group are expected to trigger the same turn-off procedure in order to maintain overall tracking of output voltages
in the system. And when fault propagation is set to go from one group to another, the encoding is passed along
un-changed.
5.8.
SWITCHING AND COMPENSATION
d-pwer® dPOLs utilize the digital PWM controller. The controller enables users to program performance
parameters, such as switching frequency, interleave, duty cycle, PWM limiting and feedback loop compensation.
5.8.1.
Switching Frequency
Switching actions of all dPOLs connected to the SD line are synchronized to the master clock generated by the
DPM. Each dPOL is equipped with a PLL and generates internal clocking locked to the SD.
The switching frequency of the DP8110G can be programmed to either 500KHz or 1MHz in the GUI PWM
Controller window shown in Figure 40 or directly via the I2C bus by writing into the INT register shown in Fig. 41.
Each dPOL is equipped with a PLL that locks to the 500 KHzSD signal which is generated by the DPM. This sets
up for switching actions to be synchronous to the falling edge of SD by all dPOLs, which are thereby kept
coordinated to each other.
Although synchronized to SD, switching frequency selection is independent for each dPOL, with the exception of
shared load bus groups, where dPOLs attached to a shared load bus are forced to use the same frequency by the
GUI.
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Figure 40. PWM Controller Window
In some applications, switching at higher frequencies is desirable even though efficiency is lower, because it allows
for better transient response or lower application system noise.
5.8.2.
Interleave Selection
Within the same PWM dialog is the switching Interleave control. Interleave is defined as a phase delay between
the synchronizing slope of the master clock on the SD pin and the start of each dPOL PWM cycle. This parameter
can be programmed in the dPOL Controller Configure Compensation window or directly via the I2C bus by writing
into the INT register in 22.5 steps.
Figure 41. Interleave Configuration Register INT
INT: Interleave Configuration
Address: 0x04
R
R
PHS1
Bit 7
PHS0
Bit 7:6
Bit 5
Bit 4
Bit 3:0
R/W0
FRQ
U
---
R/W-0
R/W-0
R/W-0
R/W-0
INT3
INT2
INT1
INT0
Bit 0
PHS[1:0]: Phase selection
0 = Single phase (PWM0)
1 = Dual phase (PWM0 and PWM2)
2 = Triple phase (PWM0, PWM1 and PWM2)
3 = Quad phase (PWM0, PWM1, PWM2 and PMW3)
FRQ: PWM frequency selection
0 = 500 kHz (default)
1 = 1000 kHz
Unimplemented: Read as ‘0’
INT[3:0]: PWM interleave phase with respect to SD line
0x00 = 0° phase lag
0x01 = 22.5° phase lag
0x02 = 45° phase lag
…
0x1F = 337.5° phase lag
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5.8.3.
Interleave and Input Bus Noise
When a dPOL turns on its high side switch there is an inrush of current. If no interleave is programmed, inrush
current spikes from all dPOLs in the system reflect back into the input source at the same time, adding together
as shown in Figure 42.
Figure 42. Input Voltage Noise, No Interleave
Figure 43. Input Voltage Noise with Interleave
Figure 43 shows the input voltage noise of the three-output system with programmed interleave. Instead of all
three dPOLs switching at the same time as in the previous example, the dPOLs V1, V2, and V3 switch at 67.5°,
180°, and 303.75°, respectively. Noise is spread evenly across the switching cycle resulting in more than 1.5 times
reduction. To achieve similar noise reduction without the interleave will require the addition of an external LC filter.
5.8.4.
Interleave and Current Sharing Noise
Similar noise reduction can be achieved on the output of dPOLs connected in parallel. Figure 44 and Figure 45
show the output noise of two dPOLs connected in parallel without and with a 180° interleave, respectively.
Resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra
capacitance on the output of the dPOLs.
Figure 44. Output Voltage Noise, Full Load, No Interleave
5.8.5.
Figure 45. Output Voltage Noise, Full Load, 180
Interleave
Duty Cycle Limit
The DP8110G is a step-down converter therefore VOUT is always less than VIN. The relationship between the two
parameters is characterized by the duty cycle and can be estimated from the following equation:
DC =
VOUT
VIN.MIN
,
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27
Where, DC is the duty cycle, VOUT is the required maximum output voltage (including margining), VIN.MIN is the
minimum input voltage.
The dPOL controller sets PWM duty cycle higher or lower than the above to compensate for drive train losses or
to pull excess charge out of the output filter to keep the output voltage where it is supposed to be.
A side effect of PWM duty cycle is it also sets the rate of change of current into the output filter. A high limit helps
deal with transients. However, if this is too high, an overcurrent alarm can be tripped. Thus DC limiting must be a
compromise between supplying drive train losses and avoiding nuisance trips from transient load responses.
The duty cycle limit can be programmed in the GUI PWM Controller window Figure 40 or directly via the I2C bus
by writing into the DCL register shown in Figure 46.
Figure 46. Duty Cycle Limit Register
DCL: Duty Cycle Limitation
Address: 0x09
R/W1
DCL5
Bit 7
Bit 7:2
Bit 1:0
5.9.
R/W1
DCL4
R/W1
DCL3
R/W0
DCL2
R/W1
DCL1
R/W0
DCL0
U
---
U
--Bit 0
DCL[5:0]: Duty Cycle Limitation
0x00 = 0
0x01 = 1/64
0x02 = 2/64
…
0x1F = 63/64
Unimplemented: Read as ‘0’
FEEDBACK LOOP COMPENSATION
Programming feedback loop compensation allows optimizing dPOL performance for various application
conditions. For example, increase in bandwidth can significantly improve dynamic response.
The dPOL implements a programmable PID (Proportional, Integral, and Derivative) digital controller to shape the
open loop transfer function for desired bandwidth, phase/gain margin.
Feedback loop compensation can be programmed in the GUI PWM Controller window by setting Kr (Proportional),
Ti (Integral), Td (Derivative), and Tv (Derivative roll-off) parameters or directly writing into the respective registers
(CP, CI, CD, B1). Note that the coefficient Kr and the timing parameters (Ti, Td, Tv) displayed in the GUI do not
map directly to the register values. It is therefore strongly recommended to use only the GUI to set the
compensation values.
The GUI offers 3 ways to compensate the feedback loop:
Auto-Compensation: The GUI will calculate compensation settings from either information entered as to output
capacitors in the application circuit, or, if the SysID function has been run, the frequency response measured
through the SysID function in the target dPOL. This method is usually sufficient, but is sensitive to accurate
accounting of capacitor values and esr. The GUI displays the results of running Auto-Compensation as a set of
graphs and compensation values.
Manual Compensation: The GUI supports manually adjusting feedback compensation parameters. As the
parameters are changed the GUI recalculates expected frequency and phase performance.
System Identification (SysID) and Auto-Compensation: Hardware built into the dPOL controller that injects
pseudo random bit sequence (PRBS) noise into PWM calculations and observes the response of the output
voltage. The GUI collects this data and calculates actual system frequency response. Having frequency response
data allows the Auto-Compensation function to have a better idea of actual output filter characteristics when it
calculates feedback coefficients.
Using noise to plumb the output filter requires current values for compensation be good enough that injected
signal can be extracted from system noise and the added noise does not trip a fault or error response. A moderately
workable solution for compensation must be obtained by calculating from assumed system component values
before invoking SysID.
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5.10. TRANSIENT RESPONSE
The following figures show the deviation of the output voltage in response to alternating 25 and 75 % step loads
applied at 2.5A/μs. The dPOL converter is switching at 500KHz and has 10 x 22μF ceramic capacitors connected
across the output pins. Bandwidth of the feedback loop was optimized for slightly overdamped response.
Figure 47. Transient Response with Regulation set to 0.0
mV/A.
Figure 48. Transient Response with Regulation set to 3.72
mV/A
5.11. CURRENT SHARING
Current sharing is not supported in DP8110G dPOL converters.
5.12. MONITORING
Along with status information, dPOL converters can monitor their own performance parameters such as output
voltage, output current, and temperature.
The output voltage is measured at the output sense pins, output current is measured using the ESR of the output
inductor and temperature is measured by the thermal sensor built into the controller IC. Output current readings
are adjusted based on temperature readings to compensate for the change of ESR of the inductor with
temperature.
A 12-Bit Analog to Digital Converter (ADC) converts the output voltage, output current, and temperature into a
digital signal to be transmitted via the serial interface (12Bits for the Voltage, 8 Bits for the Current and
Temperature).
Monitored parameters are stored in registers (VOM, IOM, and TMON) that are continuously updated in the DPM
at a fixed refresh rate of 1sec. These monitoring values can be accessed via the I2C interface with high and low
level commands as described in the ‘”DPM Programming Manual”.
Shown in Figure 49 is a capture of the GUI System Monitor while operating the ZM7300 Evaluation board.
In System Monitoring
In system parametric and status monitoring is implemented through the I2C interface. The appropriate protocols
are covered in the ZM7300 DPM Programming Manual. The GUI uses the published commands.
In writing software for I2C bus transactions, it is important to note that I2C responses are lower in priority in DPM
operation than SD bus transactions. If an I2C transaction overlaps an SD bus transaction, the DPM will put the I2C
bus on "hold" until it completes its SD activity. The GUI is aware of this and such delays are transparent.
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Figure 49. DPM Monitoring Window
6.
ADDING DPOLS INTO THE SYSTEM
The dPOL converters are added to a d-pwer® system through the DPM Configuration/Devices dialog. Clicking on
an empty address location brings up a menu which allows specifying which dPOL type is needed. Figure 50 is an
example using all of the DP7000 series devices currently offered.
Note that Auto-On, P-Monitor and S-Monitor options are only configurable by Group, and not by individual dPOL
configuration. These options affect only DPM behavior. Enabling them does not burden a dPOL.
Auto-On sets a group to turn on once all IBV power is available and dPOLs are configured.
P-Monitor enables periodic query of Vout, Iout and Temp values from each dPOL in the group where it is enabled
(dPOLs will always measure these parameters in an ongoing basis even if Vout is not enabled.
S-Monitor enables periodic query of dPOL Status. While a DPM will always be able to detect a low OK condition,
it requires this option enabled for Monitor function to query status registers.
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Figure 50 Evaluation Board Configuration showing Current Share Bus Assignment
7.
TESTING FAULT AND ERROR RESPONSE
Included in the architecture of d-pwer® dPOLs is a mechanism for simulating errors and faults. This allows the
designer to test their response configuration without actually needing to induce the fault.
The Power-One GUI supports this feature in the Monitor window when monitoring is active (See Figure 51). When
monitoring is off, the Fault Injection control boxes are disabled and grayed out.
Figure 51. Fault Injection Controls In Monitor Window
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Fault injection into a dPOL requires selecting that dPOL in the POL status dialog in the left column of the Monitoring
dialog window. As long as the checkbox is checked, the fault trigger is present in the dPOL. An injected fault is
handle by the dPOL in the same fashion as an actual fault. It therefore gets propagated to the other dPOLs /
Groups and shuts down in the programmed way the dPOL/Group/System as programmed for that fault.
Figure 52. Example Overtemp Fault Injection in the GUI
In Figure 52 we see the effects of injecting an Overtemp (OT) fault. Note that dPOL-0 shows an OT fault. dPOL-0
and -1 are in the same Group and fault propagation for the dPOL is to propagate to the group. dPOL -4 and above
are in Groups B and C. Propagation is not enabled from Group A to B.
The OT fault shows up as an orange indicator in the dPOL and RUN status LEDs. Group LEDs show yellow,
indicating all of the members of the group have shut down.
Fault recovery depends whether the fault is a latching or non-latching fault:
A non latching fault is cleared by unchecking the checkbox (clears the fault trigger). The dPOL will re-start after
the 130ms time out of non-latching faults (hiccup time) (Group and System follows restart).
Latching faults clear in one of two ways. The first method is to clear the fault trigger (uncheck the checkbox) (note:
the dPOL remains off since the fault is latching).
Alternately, a latched fault can be cleared by toggling the EN pin or by commanding the dPOL to turn-off and turnoff again via the GUI interface (obviously more convenient). Therefore, once the fault trigger is cleared, click the
“Off” button of the dPOL or Group (clears the fault, status LEDs turn back to green) and then the “On” button of
the dPOL or Group to re-enable it.
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32
8.
TYPICAL APPLICATION
Shown in Figure 53 is a block diagram of a multiple dPOL power system. The key interconnections needed between
the DPM and the dPOLs are Intermediate Voltage Bus (IBV), SD, OK (A - D), and, between the first two dPOLs which
share a bus load, their CS connections. Each dPOL has its own output bulk filter capacitors. This illustrates how
simple a dPOL based system is to implement in hardware. SD provides synchronization of all dPOLs as well as
communication. PG, not shown, is optional, though this is usually used with auxiliary power supplies that are not
digitally controlled.
Figure 53. Multi-dPOL Power System Diagram
Intermediate Voltage Bus
IBV
Linear
Regulator
For
IBV>3.3V
Linear
Regulator
Crowbar
(Optional)
Jumper
For
IBV=3.3V
R5
+3.3V
C3
6
25
42
57
C4
C5
C6
R6
60
R1
VDD VDD VDD VDD VDD
48
44
R4
SDA
SCL
R3
C1
R2
IBVS
AREF
CB
FE_EN
C2
SD
30
27
45
46
47
36
37
40
41
61
18
16
4
23
17
56
SD
SDA
SCL
OKD
OKC
OKB
OKA
ADDR2
ADDR1
ADDR0
INT3_N
INT2_N
INT1_N
INT0_N
TDI
TDO
TCK
TMS
DM7332
53
20
13
11
34
33
31
32
VIN
SD
OK
VIN
OK
dPWER
POL(s)
Group D
dPWER
POL(s)
Group C
SD
VIN
SD
OK
VIN
OK
dPWER
POL(s)
Group B
dPWER
POL(s)
Group A
JTAG
LCK_N
RES_N
ACFAIL_N
EN3
EN2
EN1
EN0
HRES_N
PG3
PG2
PG1
PG0
50
55
7
5
49
51
52
54
VIN
ENABLE
VRM
POWER
GOOD
VIN
ENABLE
LDO
ERROR
FLAG
VSS VSS VSS VSS VSS VSS
8
9
26
38
43
58
Shown in Figure 54 is a more detailed schematic of a typical application using a DM7300 series Digital Power Manager
(DPM) and at least one DP7007 point-of-load converter (dPOL). Additional d-pwer® series dPOLs may be connected
(Note SD and OK dashed lines "TO OTHER dPOLS"). As noted earlier, OK connections are determined by which group
a given dPOL is assigned to in the user's application.
In this case the DP7007 is connected to OK-A. Shown connected to the dP7007 OK pin is an optional low value
resistor helpful in some cases for fault isolation.
The type, value, and the number of output capacitors shown in the schematic are required to meet the specifications
published in the data sheet. However, all d-pwer® dPOLs are fully operational with different configurations of output
capacitors. The supervisory reset circuit in the above diagram, U2, is recommended for systems where the 3.3V supply
to the DPM does not turn on faster than 0.5 V/ms.
The DPM does require some passive components which are located close to that part but not shown in the diagram
above.
Note: The DP8110G is footprint compatible with the ZY8110—No change in PCB is needed to upgrade to d-pwer®
parts. However, configuration data must be altered through the Power-One I2C GUI and programmed into the DPM.
When upgrading to d-pwer®, mixing ZY and DP series devices is not recommended. All parts must be upgraded.
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Figure 54. Typical Application with Digital Power Manager and I2C Interface
9.
SAFETY
The DP8110G dPOL converters do not provide isolation from input to output. The input devices powering DP8110G
must provide relevant isolation requirements according to all IEC 60950 based standards. Nevertheless, if the system
using the converter needs to receive safety agency approval, certain rules must be followed in the design of the
system. In particular, all of the creepage and clearance requirements of the end-use safety requirements must be
observed. These requirements are included in UL/CSA 60950, although specific applications may have other or
additional requirements.
The DP8110G dPOL converters have no internal fuse. If required, the external fuse needs to be provided to protect
the converter from catastrophic failure. Refer to the “Input Fuse Selection for DC/DC converters” application note on
www.power-one.com for proper selection of the input fuse. Both input traces and the chassis ground trace (if
applicable) must be capable of conducting a current of 1.5 times the value of the fuse without opening. The fuse must
not be placed in the grounded input line.
Abnormal and component failure tests were conducted with the dPOL input protected by a fast-acting 65 V, 15 A,
fuse. If a fuse rated greater than 15 A is used, additional testing may be required.
In order for the output of the DP8110G dPOL converter to be considered as SELV (Safety Extra Low Voltage),
according to all IEC 60950 based standards, the input to the dPOL needs to be supplied by an isolated secondary
source providing a SELV also.
10. ENVIRONMENTAL
PARAMETER
DESCRIPTION / CONDITION
MIN
Ambient Temperature Range
Storage Temperature (Ts)
MAX
UNIT
-40
NOM
85
C
-55
125
C
MTBF
Calculated Per Telcordia Technologies SR-332
Peak Reflow Temperature
DP8110G
245
Lead Plating
DP8110G
100% Matte Tin
Moisture Sensitivity Level
DP8110G
3
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MHrs
C
260
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34
11. MECHANICAL DRAWINGS
PARAMETER
CONDITIONS/DESCRIPTION
MAX
UNITS
Dimensions
Width
Height
Depth
30.73
25.31
6.00
mm
8
g
Weight
Figure 55 - Mechanical Drawing
Figure 56 - Recommended Footprint – Top View
Note: DP8105 and DP8110G share the same PCB with substitution of power train components to support the higher
current rating of the DP8110.
I2C is a trademark of Philips Corporation.
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35
12. ORDERING INFORMATION
DP
81
10
G
-
zz
Dash
Packaging Option9
T100 - 100pc Tray
Sample quantity orders have no
suffix.
Product Family
Series
Output Current
RoHS Compliance
d-pwer®
Intelligent dPOL
Converter
10 A
G - RoHS compliant for
all six substances
Example: DP8110G-T100: A 100-piece reel of RoHS compliant dPOL converters. Each dPOL converter is labeled DP8110G.
Reference Documents
•
•
•
•
DM7300 Digital Power Manager Data Sheet
DM7300 Digital Power Manager Programming Manual
I2C Graphical User Interface
DM00056-KIT - USB to I2C Adapter Kit User Manual (EOL - contact factory for further technical assistance)
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support
systems, equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change
depending on the date manufactured. Specifications are subject to change without notice.
9
Packaging option is used only for ordering and not included in the part number printed on the dPOL converter label.
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