The PES2200-12-080xA is a 2200 Watt AC to DC, power-factorcorrected (PFC) power supply that converts standard AC power into a
main output of +12 VDC for powering intermediate bus architectures
(IBA) in high performance and reliability servers, routers, and network
switches.
The PES2200-12-080xA utilizes full digital control architecture for
greater efficiency, control, and functionality.
This power supply meets international safety standards and displays
the CE-Mark for the European
Low Voltage Directive (LVD).
•
High Efficiency, meet 80 plus “Platinum” efficiency requirement
•
Auto-selected input voltage ranges: 90-140 VAC, 180-264 VAC
•
AC input with active power factor correction
•
2200 W continuous output power capability
•
Always-on 12 VSB / 3.5 A standby output
•
Hot-plug capable
•
Parallel operation with active current sharing
•
Full digital controls for improved performance
•
High power density design: 59 W/in3
•
Small form factor: 80 x 40 x 195 mm (3.15 x 1.57 x 7.68 in)
•
Power Management Bus communication interface for control,
programming and monitoring
•
Status LED with fault signaling
•
Networking Switches
•
Servers & Routers
•
Telecommunications
PES2200-12-080xA
2
PES
2200
Product Family Power Level
-
12
-
080
x
Dash
V1 Output
Dash
Width
Airflow
A
X
Input
Specific code3
A: AC
x = Blank
x = S+3 digits
1)
PES Front-Ends
2200 W
12 V
80 mm
N: Normal
R: Reverse2)
1
“N” Normal Airflow (NAF) from Output connector to Input DC socket
Ordering PN: PES2200-12-080NA
2
“R” Reverse Airflow (RAF) from Input DC socket to Output connector
Ordering PN: PES2200-12-080RA
3
Contact factory for availability of Specific code
Ordering PN: PES2200-12-080NAS474
The PES2200-12-080xA AC/DC power supply is a fully DSP controlled, highly efficient front-end power supply. It incorporates
resonance-soft-switching technology to reduce component stresses, providing increased system reliability and very high
efficiency. With a wide input operational voltage range the PES2200-12-080xA maximizes power availability in demanding server,
network, and other high availability applications. The supply is fan cooled and ideally suited for integration with a matching airflow
path.
The PFC stage is digitally controlled using a state-of-the-art digital signal processing algorithm to guarantee best efficiency and
unity power factor over a wide operating range. The DC/DC stage uses soft switching resonant techniques in conjunction with
synchronous rectification. An active OR-ing device on the output ensures no reverse load current and renders the supply ideally
suited for operation in redundant power systems. The always-on standby output provides power to external power distribution and
management controllers. It is protected with an active OR-ing device for maximum reliability.
Status information is provided with a front-panel LED. In addition, the power supply can be controlled and the fan speed set via the
I2C bus. The I2C bus allows full monitoring of the supply, including input and output voltage, current, power, and inside temperatures.
Cooling is managed by a fan controlled by the DSP controller. The fan speed is adjusted automatically depending on the actual
power demand and supply temperature and can be overridden through the I2C bus.
L
V1
DC
Filter
Curr
ent
limit
PFC
DC
PWM
N
PE
VSB
GND
Aux
Converter
EEPROM
PFM
Fan
Digital
Primary
Controls
Communication Bus
V1_SENSE
V1_SENSE_RTN
Digital
Secondary
Controls
ISHARE
I2C
A2..0
Logic Signals
Figure 1. PES2200-12-080xA Block Diagram
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliability, and
cause permanent damage to the supply.
PARAMETER
CONDITIONS / DESCRIPTION
Vi maxc
Continuous
Maximum Input
MIN
MAX
UNITS
264
VAC
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PES2200-12-080xA
3
General Condition: TA = 0… 50 °C, unless otherwise noted.
PARAMETER
Vi nom
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Rated Voltage High Line (Vi nom HL)
200
230
240
VAC
Rated Voltage Low Line (Vi nom LL)
100
115
127
VAC
AC Nominal Input Voltage
Vi nom DC
Vi DC
Vi
DC Nominal Input Voltage
Rated HVDC
DC Input Voltage range
Normal operating (Vi min to Vi max )
180
300
VDC
Normal operating (Vi min HL to Vi max HL), High Line
180
264
VAC
Normal operating (Vi min LL to Vi max LL), Low Line
90
140
VAC
VIN = 90 VAC, I1 = 96 A, ISB = 3.5 A
15
ARMS
VIN = 180 VAC, I1 = 183 A, ISB = 3.5 A
14
ARMS
Input Voltage Ranges
Ii max
240
VDC
Maximum Input Current
Ii inrush
Inrush Current Limitation
fi
Vi min to Vi max, TNTC = 25°C, 5 ms
Input Frequency
47
50/60
50
Ap
63
Hz
Vi = 230 VAC, 50 Hz and 60 Hz, Vi = 115 VAC,60 Hz
Power Factor
PF
1
Vi on
Turn-on Input Voltage
Vi off
Turn-off Input Voltage1
Efficiency2
η
TV1 holdup
Hold-up Time V1
TVSB holdup
Hold-up Time VSB
10% Load
0.8
W/VA
20% Load
0.9
W/VA
50% Load
0.9
W/VA
100% Load
0.95
W/VA
Ramping up
85
90
VAC
Ramping down
80
85
VAC
VIN = 230 VAC, 10% load
82
VIN = 230 VAC, 20% load
90
94
%
VIN = 230 VAC, 50% load
94
95
%
VIN = 230 VAC, 100% load
91
93
%
VIN = 230 VAC, I1 = 183 A, ISB = 3.5 A
11
ms
VIN = 115 VAC, I1 = 96 A, ISB = 3.5 A
11
ms
12 VSB, full load
70
ms
%
4.1 INPUT FUSE
Time-lag 20 A input fuse (5.4 x 22.5 mm) in series with the L-line inside the power supply protects against severe defects. The
fuse is not accessible from the outside and is therefore not a serviceable part.
4.2 INRUSH CURRENT
The AC-DC power supply exhibits an X capacitance of only 5.9 µF, resulting in a low and short peak current, when the supply
is connected to the mains. The internal bulk capacitor will be charged through a PTC which will limit the inrush current.
NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in-rush current limiting device (NTC) may
not sufficiently cool down.
1
The Front-End is provided with a typical hysteresis of 5 VAC during turn-on and turn-off within the ranges.
PSU will restart once input voltage within the Vi on.
2
Efficiency measured without fan power per EPA server guidelines.
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BCD.01005_A
PES2200-12-080xA
4
4.3 INPUT UNDER-VOLTAGE
If the sinusoidal input voltage stays below the input under voltage lockout threshold Vi on, the supply will be inhibited. Once the
input voltage returns within the normal operating range, the supply will return to normal operation again.
4.4 POWER FACTOR CORRECTION
Power factor correction (PFC) is achieved by controlling the input current waveform synchronously with the input voltage. A
fully digital controller is implemented giving outstanding PFC results over a wide input voltage and load ranges. The input current
will follow the shape of the input voltage. If for instance the input voltage has a trapezoidal waveform, then the current will also
show a trapezoidal waveform.
4.5 EFFICIENCY
96
95.5
95
94.5
94
93.5
93
92.5
92
91.5
Power Factor
Efficiency[]%
High efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft-transition
topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the losses
in the high current output path. The speed of the fan is digitally controlled to keep all components at an optimal operating
temperature regardless of the ambient temperature and load conditions.
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0
0
500
1000
1500
Po[W]
2000
500
1500
2000
2500
Po[W]
2500
Figure 2. Efficiency vs. Load (ratio metric loading)
1000
Figure 3. Power factor vs. Load
Figure 4. Inrush current, Vin = 230Vac, 90°
CH1: Vin (250V/div), CH2: Iin (10A/div)
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5
4.6 INPUT LINE CURRENT HARMONIC
The power supply shall meet the requirements of EN61000-3-2 Class A and the Guidelines for the Suppression of Harmonics
in Appliances and General Use Equipment Class A for harmonic line current content at full rated power.
Per: EN 61000-3-2
Per: JEIDA MITI
Harmonic Order
n
Maximum permissible Harmonic
current at 230 VAC / 50 Hz in Amps
Maximum permissible Harmonic current at
100 VAC /50 Hz in Amps
3
5
7
9
11
13
2.3
1.14
0.77
0.4
0.33
0.21
0.15x (15/n)
Odd Harmonics
15 n 39
5.29
2.622
1.771
0.92
0.759
0.483
0.345x (15/n)
Even Harmonics
2
4
6
1.08
0.43
0.3
0.23x (8/n)
8 n 40
2.484
0.989
0.69
0.529x (8/n)
Table 1. Harmonic Limits for Class A Equipment
4.7 AC LINE TRANSIENT SPECIFICATION
AC line transient conditions shall be defined as “sag” and “surge” conditions. “Sag” conditions are also commonly referred to
as “brownout”, these conditions will be defined as the AC line voltage dropping below nominal voltage conditions. “Surge” will
be defined to refer to conditions when the AC line voltage rises above nominal voltage.
The power supply shall meet the requirements under the following AC line sag and surge conditions.
AC Line Sag (10 sec interval between each sagging)
Duration
Sag
Operating AC Voltage
Line
Frequency
Performance Criteria
0 to 1/2 AC cycle
95%*
Nominal AC Voltage ranges
50/60 Hz
No loss of function or performance
1 AC cycle to 500ms
>30%
Nominal AC Voltage ranges
50/60 Hz
Loss of function acceptable, self-recoverable
* Comment: for 95% sag condition, the load is 80%.
AC Line Surge
Duration
Surge
Operating AC Voltage
Line
Frequency
Performance Criteria
Continuous
10%
Nominal AC Voltages
50/60 Hz
No loss of function or performance
0 to ½ AC cycle
30%
Mid-point of nominal AC Voltages
50/60 Hz
No loss of function or performance
Table 2. AC Line Transient Performance
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6
General condition: TA = 0…50 °C, Vi = 230 VAC unless otherwise noted.
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
+1
%V1 nom
240
mV
Main Output V1
V1 nom
V1 set
Nominal Output Voltage
Output Setpoint Accuracy
0.5 ∙ I1 nom, TA = 25°C
dV1 load
Load Regulation
0 to 100% I1 nom
dV1 line
Line Regulation
Vi min LL to Vi max HL
dV1 tot
Total Regulation
Vi min to Vi max, 0 to 100% I1 nom
P1 nom
Nominal Output Power
I1 peak
I1 nom
I1 nom red
V1 pp
Vi min HL to Vi max HL
2200
Vi min LL to Vi max LL
1155
Output Current
3
120
mV
+5
%V1 nom
W
W
205
ADC
300
ADC
115
ADC
0.0
183
ADC
Vi min LL to Vi max LL
0.0
96
ADC
Vi min to Vi max, 0 to 100% I1 nom, 20MHz Bandwidth
Current Sharing
Deviation from I1 tot / N, I1 > 20%
VISHARE
Current Share Bus Voltage
I1 nom
dV1 dyn
Dynamic Load Regulation
Test frequency between 50 Hz and 5 kHz at duty cycles
from 10% to 90%, ΔI1 = 60% I1nom, I1 = 3 A … 100%
I1nom, 2000 µF capacitive loading
dI1/dt = 0.25 A/µs, recovery within 1% of V1nom
Recovery Time
VDC
Vi min HL to Vi max HL
dI1 share
trec
-5
Vi min HL to Vi max HL (max 20 s)
Vi min HL to Vi max HL (max 100 µs)
Vi min LL to Vi max LL (max 20 s)
Peak Output Loading
Output Ripple Voltage
12.0
-1
tV1 rise
Output Voltage Rise Time
V1 = 10…90% V1 nom
-5
150
mVpp
+5
% I1 nom
8
11.40
VDC
12.60
1
VDC
2
ms
70
ms
tV1 ovr sh
Output Turn-on Overshoot
Vi nom HL, 0 to 100% I1 nom
0.6
V
dV1 sense
Remote Sense
Compensation for cable drop, 0 to 100% I1 nom
0.25
V
CV1 load
Capacitive Loading
22
mF
+1
%VSBnom
Standby Output VSB
VSB nom
VSB set
Nominal Output Voltage
Output Setpoint Accuracy
0.5 ∙ISB nom, TA = 25°C
12.0
-1
VDC
dVsb load
Load Regulation
0 to 100% ISB nom
480
mV
dVsb line
Line Regulation
Vi min LL to Vi max HL
120
mV
dVSB tot
Total Regulation
Vi min to Vi max, 0 to 100% ISB nom
+5
%VSBnom
PSB nom
Nominal Output Power
Vi min to Vi max
ISB
Peak Output Loading
Vi min LL to Vi max HL
Output Current
Vi min to Vi max
peak
ISB nom
VSB pp
dVSB dyn
trec
Output Ripple Voltage
3
Dynamic Load Regulation
-5
42
4
ADC
0.0
3.5
ADC
120
mVpp
11.40
12.60
VDC
2
ms
Vi min to Vi max, 0 to 100% ISB nom, 20 MHz bandwidth
Recovery Time
ΔISB = 50% ISB nom, ISB = 0 … 100% ISB nom,
dISB/dt = 0.25A/µs, recovery within 1% of VSB nom
tVSB rise
Output Voltage Rise Time
VSB = 10…90% VSB nom,
tVSB ovr sh
Output Turn-on Overshoot
Vi nom HL, 0 to 100% ISB nom
CVSB load
Capacitive Loading
W
5
10
ms
0.6
V
1000
µF
3 Ripple noise and dynamic load measured with a 10 µF low ESR capacitor in parallel with a 0.1 µF ceramic capacitor at the point of
measurement.
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PES2200-12-080xA
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5.1 OUTPUT GROUND / CHASSIS CONNECTION
The output return path serves as power and signal ground. All output voltages and signals are referenced to these pins. To
prevent a shift in signal and voltage levels due to ground wiring voltage drop a low impedance ground plane should be used
as shown in Figure 5. Alternatively, separated ground signals can be used as shown in Figure 6. In this case the two ground
planes should be connected together at the power supplies ground pins.
NOTE:
Within the power supply the output GND pins are connected to the Chassis, which in turn is connected to the Protective Earth
terminal on the AC inlet. Therefore, it is not possible to set the potential of the output return (GND) to any other than Protective
Earth potential.
Line
PES2200-12-080NA
Application
V1
VSB
Neutral
Logic,
Controls
Logic
Signals
PE
GND
Load
VSB
Load
V1
Voltage drop
Figure 5. Common Low Impedance Ground Plane
Line
PES2200-12-080NA
VSB
Neutral
Logic,
Controls
PE
Application
V1
Logic
Signals
Load
VSB
Load
V1
GND
Figure 6. Separated Power and Signal Ground
5.2 CLOSED LOOP STABILITY
The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges.
A minimum of: 45 degrees phase margin and -6dB-gain margin is required. The power supply manufacturer shall provide
proof of the unit’s closed-loop stability with local sensing through the submission of Bode plots. Closed-loop stability must
be ensured at 10%, 20%, 50% and 100% loads as applicable, 0% is just for reference.
5.3 RESIDUAL VOLTAGE IMMUNITY IN STANDBY MODE
The power supply should be immune to any residual voltage placed on its outputs (Typically a leakage voltage through the
system from standby output) up to 500 mV. There shall be no additional heat generated, nor stressing of any internal
components with this voltage applied to any individual or all outputs simultaneously. It also should not trip the protection
circuits during turn on.
The residual voltage at the power supply outputs for no load condition shall not exceed 100mV when AC voltage is applied
and the PSON_L signal is de-asserted.
5.4 COMMON MODE NOISE
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency band of 10 Hz to 20 MHz.
The measurement shall be made across a 100 Ω resistor between each of DC outputs, including ground at the DC power
connector and chassis ground (power subsystem enclosure), the test set-up shall use a FET probe such as Tektronix model
P6046 or equivalent.
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8
5.5 SOFT STARTING
The Power Supply shall contain control circuit which provides monotonic soft start for its outputs without overstress of the
AC line or any power supply components at any specified AC line or load conditions.
5.6 ZERO LOAD STABILITY REQUIREMENTS
When the power subsystem operates in a no load condition, it does not need to meet the output regulation specification, but
it must operate without any tripping of over-voltage or other fault circuitry. When the power subsystem is subsequently loaded,
it must begin to regulate and source current without fault.
5.7 HOT SWAP REQUIREMENTS
Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system.
During this process the output voltages shall remain within the limits with the capacitive load specified. The hot swap test
must be conducted when the system is operating under static, dynamic, and zero loading conditions. The power supply shall
use a latching mechanism to prevent insertion and extraction of the power supply when the AC power cord is inserted into
the power supply.
5.8 FORCED LOAD SHARING
The PES front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be
interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will disconnect
its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases.
The current share function uses an analog bus to transmit and receive current share information. The controller implements a
Master/Slave current share function. The power supply providing the largest current among the group is automatically the
Master. The other supplies will operate as Slaves and increase their output current to a value close to the Master by slightly
increasing their output voltage. The voltage increase is limited to +250 mV. The output will share within 10% at full load.
The 12 VSB output is not required to actively share current between power supplies (passive sharing).
5.9 RIPPLE / NOISE
The test set-up shall be following Figure 7.
VOUT
AC HOT
POWER SUPPLY V
RETURN
AC NEUTRAL
LOAD
10uF
.1uF
LOAD MUST BE
ISOLATED FROM
THE GROUND OF
THE POWER
SUPPLY
AC GROUND
GENERAL NOTES:
1. LOAD THE OUTPUT WITH ITS MINIMUM
LOAD CURRENT.
2. CONNECT THE PROBES AS SHOWN.
3. REPEAT THE MEASUREMENTS WITH THE
MAXIMUM LOAD ON THE OUTPUT.
SCOPE
SCOPE NOTE:
USE A TEKTRONIX 7834 OSCILLOSCOPE WITH 7A13 AND
DIFFERENTIAL PROBE P6055 OR EQUIVALENT.
Figure 7. Differential Noise Test Setup
NOTE: Load must be isolated from the safety ground to Figure 7.
NOTE: When performing this test, the probe clips and capacitors should be located close to the load.
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PES2200-12-080xA
PARAMETER
F
9
DESCRIPTION / CONDITION
Input fuse (L)
Not use accessible, time-lag (T)
MIN
NOM
MAX
20
UNIT
A
V1 OV
OV Threshold V1
Over Voltage V1 Protection, Latch-off Type
13.0
13.9
14.5
VDC
VVSB OV
OV Threshold VSB
Over Voltage VSB Protection, Automatic recovery Type
13.0
13.9
14.5
VDC
V1 UV
UV Threshold V1
Under Voltage V1 Protection, Latch-off Type
11.2
VDC
VVSB UV
UV Threshold VSB
Under Voltage VSB Protection, Automatic recovery Type
11.2
VDC
Over Current Limitation, Latch-off, Vi min HL to Vi max HL
IV1 OC
OC Limit V1
IVSB OC
OC Limit VSB
Over Current Limitation, Automatic recovery Type
Over Temperature On
Critical Points
Automatic shut-down
ADC
Refer to section 6.5
Over Current Limitation, Latch-off, Vi min LL to Vi max LL
TSD
ADC
4.5
5.5
Refer to Table 11
A
°C
6.1 PROTECTION CIRCUITS
Protection circuits inside the power supply shall cause only the power supply’s main output to shut down. If the power supply
latches off due to a protection circuit tripping, an AC cycle OFF for 15 sec and a PSON_L cycle HIGH for 1sec shall be able to
reset the power supply.
6.2 OVER TEMPERATURE PROTECTION (OTP)
The power supply will be protected against over temperature conditions caused by loss of fan cooling or excessive ambient
temperature.
In an OTP condition the PSU will shut down, OT warning SMB_ALERT_L assertion must always precede the OTP shutdown,
when the power supply temperature drops to within specified limits, the power supply shall restore power automatically, while
the 12 VSB remains always on, the OTP circuit must have built in margin such that the power supply will not oscillate on and
off due to temperature recovering condition, the OTP trip temperature level shall be at least 5degC higher than SMB_ALERT_L
over temperature warning threshold level.
6.3 OVER VOLTAGE PROTECTION
The PES2200-12-080xA front-end provides a fixed threshold overvoltage (OV) protection implemented with a HW comparator
for both the main and the standby output. Once an OV condition has been triggered on the main output, the supply will shut
down and latch the fault condition. The latch can be unlocked by disconnecting the supply from the AC mains or by toggling
the PSON_L input. 12 VSB will be auto-recovered after removing OVP limit.
6.4 UNDER VOLTAGE DETECTION
Both main and standby outputs are monitored. LED and PWOK_H pin signal if the output voltage exceeds ±5% of its
nominal voltage.
The main output will latch off if the main output voltage V1 falls below 11.2 V (typically in an overload condition), The latch can
be unlocked by disconnecting the supply from the AC mains or by toggling the PSON_L input.
If the standby output leaves its regulation bandwidth for more than 10 ms then the main output is disabled to protect the
system.
6.5 Current limitation
The main output current limitation level IV1 lim will decrease if the ambient (inlet) temperature increases beyond 50 °C (see
Figure 8 and Table 3). Note that the current limitation on V1 will kick in at a current level approximately 10A-16A higher nominal
output current that is shown.
The 2nd protection is a substantially rectangular output characteristic controlled by a software feedback loop. This protects
the power supply and system during the 20s peak load. after the 20s goes out, the supply will shut down.
The 3rd protection is a substantially rectangular output characteristic controlled by a software feedback loop. This protects
the power supply and system during the 20ms blanking time of the static over current protection. If the output current is rising
fast and reaches IV1 lim, the supply will immediately shut down.
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10
When the main output over current, the V1 will shut down and latch off. The latch can be cleared by recycling the input voltage
or the PSON_L input. A failure on the Main output will shut down only the Main output, while Standby continues to operate.
Additionally, the main output power limitation will decrease if the ambient (inlet) temperature increases beyond 55°C, which
is defined as a short term operation condition and NOT recommend to operate at this condition for long term.
Vin (Vac)
90
100
110
120
130
140
150
160
170
175
180
190
200
210
220
270
50℃
Iout_Nom (A)
96
96
96
96
96
96
96
96
96
183
183
183
183
183
183
183
50℃
Iout_OCP (A)
103~110
103~110
103~110
103~110
103~110
103~110
103~110
103~110
103~110
196~205
196~205
196~205
196~205
196~205
196~205
196~205
50℃
peak load (A) (20s)
110
110
110
110
110
110
110
110
110
205
205
205
205
205
205
205
55℃
Iout_Nom (A)
96
96
96
96
96
96
96
96
96
167
167
167
167
167
167
167
55℃
Iout_OCP (A)
103~110
103~110
103~110
103~110
103~110
103~110
103~110
103~110
103~110
179 ~187
179 ~187
179 ~187
179 ~187
179 ~187
179 ~187
179 ~187
55℃
peak load (A) (20s)
110
110
110
110
110
110
110
110
110
187
187
187
187
187
187
187
Table 3. Main Output Nominal Output Current I1 nomll & Current Limitation IV1 lim vs Inlet Temperature (degC) & Vin(Vac)
output power(W)
2250
2200
2150
2100
2050
2000
1950
0
10
20
30
40
50
60
70
Teperature (C)
Figure 8. Power derating vs temperature
6.6 PEAK LOAD WITH ADDED SYSTEM BUFFER CAPACITANCE
The power supply shall be able to support higher peak power levels with added system buffer capacitance for up to 100 µs.
Table 4 are PMAX testing conditions.
PEAK POWER
PEAK CURRENT
SYSTEM CAPACITANCE
PEAK LOAD DURATION
VOLTAGE UNDERSHOOT
2736W
228A
6,150 µF
100 µs
5%
Table 4. PMAX Testing Conditions
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11
The power supply operating parameters can be accessed through I2C interface. For more details refer to chapter
I2C / POWER MANAGEMENT BUS COMMUNICATION and document PES2200-12-080xA Power Management Bus
Communication Manual.
PARAMETER
Vi mon
Input Voltage
Ii mon
Input Current
Pi mon
True Input Power
Ei mon
V1 mon
I1 mon
P nom
E nom
Tambmon
FS
Total Input Energy
DESCRIPTION / CONDITION
MIN
MAX
UNIT
-2
+2
VAC
-1
+1
A
Pi > 700 W
-5
+5
%
Pi ≤700 W
35
35
W
Pi > 700 W
-5
+5
%
Pi ≤700 W
35
35
W
Vi min LL ≤ Vi ≤ Vi max
V1 Voltage
V1 Current
V1 Output Power
V1 Onput Energy
Ambient Temperature
NOM
-1
+1
%
I1 > 30 A
-2
+2
%
I1 ≤ 30 A
-1
+1
A
Po > 250 W
-5
+5
%
Po ≤ 250 W
-15
+15
W
Po > 250 W
-5
+5
%
Po ≤ 250 W
-15
+15
W
0℃ ≤ Tamb ≤ 55℃
Fan speed
-5
+5
℃
-500
+500
RPM
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8.1 ELECTRICAL CHARACTERISTICS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
V
PSON_L
VIL
Input Low Level Voltage
PSON_L: Main output enabled
0
0.8
VIH
Input High Level Voltage
PSON_L: Main output disabled
2
5.25
V
IIL,H
Maximum Source Current
VI = -0.2 V to +3.5 V
4
mA
Rpull up
Pull-up to 3V3 Located in Power Supply
10
kΩ
PWOK_H
VOL
Output Low Level Voltage
Vi < Vi min LL, Isink = 400 µA
VOH
Output High Level Voltage
Vi > Vi min LL, Isource = 200 µA
IS
Maximum Sink Current
Maximum Source Current
PWOK_H = low
400
µA
PWOK_H = high
2
mA
3.46
V
0.4
V
SMB_ALERT_L = low
4
mA
SMB_ALERT_L= high
50
µA
3.46
V
0.4
V
4
mA
0
0.4
V
2.4
3.46
V
SMB_ALERT_L
Vext
Maximum External Pull up Voltage
VOL
Output Low Level Voltage
Rpull up
IS
Failure or Warning condition, Isink < 4 mA
0
Pull-up to 3V3 Located in Power Supply
None
Sink Current
VIN_OK_H
Vext
Maximum External Pull up Voltage
VOL
Output Low Level Voltage
Rpull up
IS
Failure or Warning condition, Isink < 4 mA
Pull-up to 3V3 Located in Power Supply
Sink Current
0
1
VIN_OK_H = low
kΩ
8.2 SENSE INPUTS
The main output has sense lines implemented to compensate for voltage drop on load wires in both positive and negative
path. The maximum allowed voltage drop is 200 mV on the positive rail and 50 mV on the GND rail.
With open sense inputs the main output voltage will rise by 250 mV. Therefore, if not used, these inputs should be connected
to the power output and GND at the power supply connector. The sense inputs are protected against short circuit. In this case
the power supply will shut down.
8.3 PRESENT_L OUTPUT
The PRESENT_L pin is wired through a 100 Ohms resistor to internal GND within the power supply. This pin does indicate that
there is a power supply present in this system slot. An external pull-up resistor has to be added within the application. Current
into PRESENT_L should not exceed 5mA to guarantee a low level voltage if power supply is seated.
PSU PDU
Vext
PRESENT_L
100Ω
Figure 9. PRESENT_L Connection
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8.4 PSON_L INPUT
The PSON_L is an internally pulled-up (3.3 V) input signal to enable/disable the main output V1 of the front-end. With low level
input the main output is enabled. This active-low pin is also used to clear any latched fault condition. The PSON_L can be
either controlled by an open collector device or by a voltage source.
PSU 1 PDU
PSU 1 PDU
3.3V
3.3V
PSON_L
PSON_L
PSU 2
PSU 2
3.3V
3.3V
PSON_L
PSON_L
Figure 10. PSON_L connection
8.5 PWOK_H OUTPUT
PWOK_H is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are within the
regulation limits of the power supply. When any output voltage falls below regulation limits or when AC power has been
removed for a time sufficiently long so that power supply operation is no longer guaranteed, PWOK_H will be de-asserted to
a LOW state. The start of the PWOK_H delay time shall be inhibited as long as any power supply output is in current limit.
The PWOK_H and I2C bus of PSU are connected together on the redundant system. The below block diagram was shown the
wiring on the system. The internal PWOK_H circuit of power supply is designed so that the PWOK_H bus is the wire-ORed
function of the individual PWOK_H signals of all the power supply in parallel. Suggest system Pull-up to 3V3 and pull-up
resistance is 10K. The PWOK_H signal also can be separated for each PSU design in system side to indicate each PSU output
state.
PWOK_H
PSU1
System PWOK_H
Detection Circuit
PWOK_H
PSU2
Figure11. PWOK_H connection
8.6 SMB_ALERT_L OUTPUT
The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate.
This is a logical OR of the Shutdown and Warning events. It is asserted (pulled Low) at Shutdown or Warning events such as
reaching temperature warning/shutdown threshold of critical component, general failure, over-current, over-voltage, undervoltage or low-speed of failed fan. This signal may also indicate the power supply is operating in an environment exceeding
the specified limits. This signal is to be asserted in parallel with LED turning solid Yellow.
The power supply shall assert the over temperature SMB_ALERT_L signal when a hot spot or inlet temperature sensor crosses
a warning threshold. The inlet temperature warning threshold must be set at 59°C, preventing exhaust air and cord
temperatures temperature exceeding safety ratings. The warning gets de-asserted once inlet air temperature returns into
specified operating temperature range. Fan speed control algorithm shall ramp up the fan speed to the maximum prior to the
SMB_ALERT_L insertion.
In case exhaust air temperature exceeds 70 °C higher temp rating cord must be used.
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PSU 1 PDU
SMBALERT_L
3.3V
≥1kΩ
PSU 2
SMBALERT_L
Figure 12. SMB_ALERT_L Connection
8.7 VIN_OK_H OUTPUT
This signal will be asserted, driven high, by the power supply to indicate that the input voltage meets the minimum requirements
of the parametric PSU specification.
The PSU shall de-assert (drive low) under input over-voltage condition.
AC Line and AC loss detection algorithm
AC line voltage detection for power on:
The power supply will use Vrms to determine if the input voltage is within the specified requirements for turning on the power
supply unit as called out by the individual power supply specification for AC input voltage range. The Vrms of the input must
be determined within 5-cycles after the application of AC & Standby has reached regulation. Assertion requirements for
VIN_OK_H remain the same.
AC line voltage detection for an AC brownout and dropout:
PSU shall detect both AC brown out and dropout conditions and issue a power down warning to the end system. The PSU
shall de-assert (drive low) VIN_OK_H at least 4mS(T1) prior to the de-assertion of PWOK_H upon input conditions that fall
below the Vin (turn-off) specification of the PSU parametric specification. Under such conditions. After VIN_OK_H de-assertion,
the PSU shall be capable of delivering all outputs within the regulation limits for at least 4mS before de-asserting PWOK_H(T1).
In a similar manner the PSU shall de-assert PWOK_H a minimum of 1 ms prior to the main rail voltage degrading to 95% of
the set point voltage value. Upon a VIN_OK_H de-assertion, the PSU shall derive an average RMS input voltage, measured
over a moving average window equal to T2, to establish if conditions meet the requirements for assertion of VIN_OK_H. Refer
to Figure 13.
AC Input
12V
T1
PWOK_H
12VSB
T3
VIN_OK_H
T2
T4
Figure 13. VIN_OK_H Timing
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PARAMETER
15
DESCRIPTION / CONDITION
MIN
T1
VIN_OK_H & PWOK_H
4
T2
VIN_OK_H Dwell Time
75
T3
VIN_OK_H delay to AC
T4
VIN_OK_H to 12VSB
NOM
MAX
UNIT
ms
120
ms
1700
ms
20
ms
NOTE: T2 is the minimum VIN_OK_H de-assertion dwell time that is initiated when the PSU has declared a loss of input voltage.
Table 5. VIN_OK_H Timing Requirements
8.8 TIMING REQUIREMENTS
These are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation
limits (Tvout_rise) within 1 to 70 ms. For 12 VSB, it is allowed to rise from 5.0 between 10 ms. All outputs must rise monotonically.
Table 6 shows the timing requirements for the power supply being turned on and off two ways; 1) via the AC input with PSON_L
held low; 2) via the PSON_L signal with the AC input applied. The PSU needs to remain off for 1 second minimum after
PWOK_H is de-asserted.
AC Input
T12V_holdup
12V
TPWOK_H_low
TAC_on_delay
TVSB_on_delay
TPWOK_H_on
PWOK_H
12VSB
TPWOK_H_off
TVSB_on_delay
TPWOK_H_on
TPWOK_H_holdup
TVSB
TPWOK_H_off
TPSON_L_PWOK_H
TVSB_holdup
TPSON_L_on_delay
PSON_L
AC turn on/off cycle
PSON turn on/off cycle
Figure 14. Turn On/Off Timing
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PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
70 *
ms
T12V_rise
Output voltage rise time
1.0 *
TVSB_on_delay
Delay from AC being applied to 12VSB being within regulation.
1500
ms
T AC_on_delay
Delay from AC being applied to all output voltages being within regulation.
3000
ms
T12V_holdup
Time 12V output voltage stay within regulation after loss of AC.
10.5
ms
TPWOK_H_holdup
Delay from loss of AC to de-assertion of PWOK_H
9
ms
TPSON_L_on_delay
Delay from PSON_L active to output voltages within regulation limits.
5
T PSON_L_PWOK_H
Delay from PSON_L deactivate to PWOK_H being de-asserted.
Delay from output voltages within regulation limits to PWOK_H asserted at
turn on.
Delay from PWOK_H de-asserted to output voltages dropping out of
regulation limits.
Duration of PWOK_H being in the de-asserted state during an off/on cycle
using AC or the PSON_L signal.
Delay from 12VSB being in regulation to O/Ps being in regulation at AC turn
on.
TPWOK_H_on
T PWOK_H_off
TPWOK_H_low
TVSB
TVSB_holdup
Time the 12VSB output voltage stays within regulation after loss of AC.
TAC_off_SMB_ALERT_L
The power supply shall assert the SMB_ALERT_L signal quickly after a loss
of AC input voltage
100
400
ms
5
ms
500
ms
1
ms
100
ms
50
1000
70
ms
ms
2
ms
* The 12VSB output voltage rise time shall be from 5.0 ms between 10 ms.
Table 6. Timing Requirements
8.9 HOT_STANDBY
The hot-standby operation is an operating mode allowing to further increase efficiency at light load conditions in a redundant
power supply system. Under specific conditions one of the power supplies is allowed to disable Oring gate, to make sure into
hot standby mode. This will save the power losses associated with this power supply and at the same time the other power
supply will operate in a load range having a better efficiency.
8.10
LED INDICATOR
The front-end has one front LED showing the status of the supply. The LED is bi-colored: green and yellow and indicates AC
and DC power presence and warning or fault conditions. Table 8 lists the different LED status.
MIN λd
WAVELENGTH
NOMINAL λd
WAVELENGTH
MAX λd
WAVELENGTH
UNITS
Green
570
nm
Yellow
590
nm
Table 7. LED Characteristics
OPERATING CONDITION
LED STATE
Output ON and OK
Solid GREEN
No AC power to all power supplies
OFF
AC present / Only 12VSB on (PS off) or PS in Hot standby state
1Hz Blink GREEN
AC cord unplugged; with a second power supply in parallel still with AC input power.
OFF
Power supply warning events where the power supply continues to operate; high
temp, high power, high current, slow fan.
1Hz Blink YELLOW
Power supply critical event causing a shutdown; failure, OCP, OVP, Fan Fail
Solid YELLOW
Power supply in FW upload mode
2Hz Blink GREEN
Table 8. LED Status
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The PES front-end is a communication Slave device only; it never initiates messages on the I2C/SMBus by itself.
The communication bus voltage and timing is defined in Figure 15 further characterized through:
•
•
•
•
•
•
•
The SDA/SCL IOs use 3V3 logic levels
External pull-up resistors on SDA/SCL required for
correct signal edges
Full SMBus clock speed of 100 kbps
Clock stretching limited to 1 ms
SCL low time-out of >25 ms with recovery
within 10 ms
Recognizes any time Start/Stop bus conditions
3.3V
3.3/5V
RX
TX_EN
10kΩ
Rpull-up
TX
SDA/SCL
DSP or EEPROM
Figure15. Physical layer of communication interface
Communication to the DSP or the EEPROM will be possible as long as the input AC voltage is provided. If no AC is present,
communication to the unit is possible as long as it is connected to a life VSB output or V1 output (provided e.g. by the
redundant unit).
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
UNIT
-0.5
1.0
V
3.5
V
SCL / SDA
ViL
Input low voltage
ViH
Input high voltage
2.3
Vhys
Input hysteresis
0.15
VoL
Output low voltage
3 mA sink current
V
0
0.4
V
20+0.1Cb1
1000
ns
20+0.1Cb1
250
ns
-10
10
μA
50
pF
100
kHz
1000 ns / Cb1
Ω
tr
Rise time for SDA and SCL
tof
Output fall time ViHmin → ViLmax
10 pF < Cb1 < 400 pF
Ii
Input current SCL/SDA
0.1 VDD < Vi < 0.9 VDD
Ci
Internal Capacitance for each SCL/SDA
fSCL
SCL clock frequency
Rpull-up
External pull-up resistor
fSCL ≤ 100 kHz
tHDSTA
Hold time (repeated) START
fSCL ≤ 100 kHz
4.0
μs
tLOW
Low period of the SCL clock
fSCL ≤ 100 kHz
4.7
μs
tHIGH
High period of the SCL clock
fSCL ≤ 100 kHz
4.0
μs
tSUSTA
Setup time for a repeated START
fSCL ≤ 100 kHz
4.7
μs
tHDDAT
Data hold time
fSCL ≤ 100 kHz
0
tSUDAT
Data setup time
fSCL ≤ 100 kHz
250
ns
tSUSTO
Setup time for STOP condition
fSCL ≤ 100 kHz
4.0
μs
tBUF
Bus free time between STOP and START
fSCL ≤ 100 kHz
5
ms
1
0
3.45
μs
Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF
Table 9. I2C / SMBus Specification
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tof
tLOW
tHIGH
tLOW
tr
SCL
tSUSTA
tHDSTA
tHDDAT tSUDAT
tSUSTO
tBUF
SDA
Figure 16. I2C / SMBus Timing
ADDRESS SELECTION
The address for I2C communication can be configured by pulling address input pins A2, A1 and A0 either to GND (Logic Low)
or leave them open (Logic High). An internal pull up resistor will cause the A2 / A1 / A0 pin to be in High Level if left open. A
fixed addressing offset exists between the Controller and the EEPROM.
I2C Address *
A2
A1
A0
Controller
EEPROM
0
0
0
0xB0
0xA0
0
0
1
0xB2
0xA2
0
1
0
0xB4
0xA4
0
1
1
0xB6
0xA6
1
0
0
0xB8
0xA8
1
0
1
0xBA
0xAA
1
1
0
0xBC
0xAC
1
1
1
0xBE
0xAE
* The LSB of the address byte is the R/W bit
Table 10. Address and Protocol Encoding
9.1 CONTROLLER AND EEPROM ACCESS
The controller and the EEPROM in the power supply share the same I2C bus physical layer (see Figure 17) and can be accessed
under different addresses, see ADDRESS SELECTION.
The SDA/SCL lines are connected directly to the controller and EEPROM which are supplied by internal 3V3.
The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply.
A2..0
Address Selection
SDA
DSP
SCL
Protection
EEPROM
Figure 17. I2C Bus to DSP and EEPROM
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9.2 EEPROM PROTOCOL
The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read
commands are defined, it is recommended to use the single byte write / read commands.
WRITE
The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte
with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus
should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.
S Address W A
Data Address
A
Data
A
P
READ
The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data
address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the
data byte at the specified location.
S Address W A
S Address R
Data Address
A
Data
A
nA P
9.3 POWER MANAGEMENT BUS PROTOCOL
The Power Management Bus is an open standard protocol that defines means of communicating with power conversion and
other devices. For more information, please see the System Management Interface Forum web site at : www.powerSIG.org.
Power Management Bus command codes are not register addresses. They describe a specific command to be executed.
The PES2200-12-080xA supply supports the following basic command structures:
•
Clock stretching limited to 1 ms
•
SCL low time-out of >25 ms with recovery within 10 ms
•
Recognized any time Start/Stop bus conditions
WRITE
The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte
or after the first data byte (Byte command) or then after sending 2 data bytes (Word command).
S Address W A
Data Low Byte1) A
1)
Command
A
Data High Byte1) A
P
Optional
In addition, Block write commands are supported with a total maximum length of 255 bytes.
S Address W A
Byte 1
Command
A
A
Byte Count
A
Byte N
A
P
READ
The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word.
S Address W A
S Address R
1)
A
Command
A
Data (Low) Byte A
Data High Byte1) nA P
Optional
In addition, Block read commands are supported with a total maximum length of 255 bytes.
S Address W A
Byte Count
A
Command
Byte 1
A
A
S Address R
Byte N
A
nA P
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9.4 POWER SUPPLY DIAGNOSTIC “EVENT RECORDER”
The power supply shall save the latest Power Management Bus data and other pertinent data into nonvolatile memory when a
critical event shuts down the power supply. This data shall be accessible via the Power Management Bus interface with an
external source providing power to the 12Vstby output.
Critical Events to trigger an update to the Event Recorder includes:
•
Output OVP
•
Output OCP
•
Input OV/UV Fault
•
Fan fault
•
OTP
•
Other faults to cause output shutdown.
Refer to BCA.00199_PES2200-12-080xA Power Management Bus Communication Application Note for further information
about the Power Management Bus commands to support this function.
9.5 FIRMWARE UPDATE
The power supply shall have the capability to update its firmware via the Power Management Bus interface while it is in
standby mode. This FW can be updated when in the system and in standby mode and outside the system with power applied
to the 12Vstby pins. BPS standard GUI supports the firmware upgrade function.
9.6 GRAPHICAL USER INTERFACE
Bel Power Solutions provides with its “I2C Utility” a Windows® XP/Vista/Win7 compatible graphical user interface allowing the
programming and monitoring of the PES2200-12-080xA Front-End. The utility can be downloaded on: belfuse.com/powersolutions and supports both the PSMI and Power Management Bus protocols.
The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation
tree. In the monitoring view the power supply can be controlled and monitored.
If the GUI is used in conjunction with the YTM.00103 Evaluation Board it is also possible to control the PSON_L pin(s) of the
power supply.
Figure 18. Monitoring dialog of the I2C Utility
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To achieve best cooling results sufficient airflow through the supply must be ensured. Do not block or obstruct the air-flow at
the rear of the supply by placing large objects directly at the output connector. The PES2200-12-080xA is pro-vided with a
rear to front airflow, which means the air enters through the DC-output of the supply and leaves at the AC-inlet.
The PES2200-12-080xA supply has been designed for horizontal operation.
The fan inside of the supply is controlled by a microprocessor. The rpm of the fan is adjusted to ensure optimal supply cooling
and is a function of output power and the inlet temperature.
The fan oscillation shall be controlled such that associated sound power level variation falls within a band of 2.0 dBA (roughly
10% mean speed). This condition may be treated as steady state fan speed condition.
After the new load and/or cooling condition steady state is established, transition to the steady state fan speed shall take place
within 60 s.
The PES2200-12-080xA provides access via I2C to the measured temperatures of in total 4 sensors within the power supply,
see Table 11. The microprocessor is monitoring these temperatures and if warning threshold of one of these sensors is reached
it will set fan to maximum speed. If temperatures continue to rise above shut down threshold the main output V1 (or VSB if
auxiliary converter is affected) will be disabled. At the same time the warning or fault condition is signalized accordingly through
LED, PWOK_H and SMB_ALERT_L.
POWER
MANAGEMENT
BUS REGISTER
TEMPERATURE SENSOR
DESCRIPTION / CONDITION
Inlet air temperature (NA)
Outlet air temperature (RA)
Sensor located on control board close to DC
end of power supply
8Dh
Syn rectifier Mosfet
Sensor located close to Syn rectifier Mosfet
8Eh
Outlet air temperature (NA)
Inlet air temperature (RA)
Sensor located on main board close to AC
front of power supply
8Fh
PFC heat sink
Sensor located on PFC heat sink
EAh
WARNING
THRESHOLD
SHUT DOWN
THRESHOLD
NA:98
RA:95
NA:110
RA:120
NA:80
RA:68
NA:73
RA:100
NA:115
RA:128
NA:85
RA:73
96
101
Table 11. Temperature Sensor Location and Thresholds
Airflow
Figure19. Airflow Direction
30000
28000
26000
24000
22000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
25℃
35℃
45℃
55℃
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Figure 20. Fan Speed vs. Main Output Load
Comment: The fan minimum speed is 6000RPM.
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22
11.1
IMMUNITY
DESCRIPTION / CONDITION
PARAMETER
ESD Contact Discharge
ESD Air Discharge
Radiated Electromagnetics
Filed
Burst
Surge
RF Conducted Immunity
Voltage Dips and Interruptions
1.
11.2
IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point
(metallic case, LEDs, connector body)
IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point
(non-metallic user accessible surfaces)
IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation,
1 µs Pulse Modulation, 10 kHz…2 GHz
IEC / EN 61000-4-4, level 3
AC port ±2 kV, 1 minute
DC port ±1 kV, 1 minute
IEC / EN 61000-4-5
Line to earth: level 3, ±2 kV
Line to line: level 2, ±1 kV
IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz
IEC/EN 61000-4-11
1) Vi 230Volts, 80% Load, Dip 100%, Duration 10ms
2) Vi 230Volts, 100% Load, Dip 100%, Duration < 50 ms
3) Vi 230Volts, 100% Load, Dip 100%, Duration > 50 ms
CRITERION
A
A
A
A
A
A
A
V1: B; VSB: A
B
EMISSION
PARAMETER
Conducted Emission
Radiated Emission
Acoustical Noise
DESCRIPTION / CONDITION
EN 55032/CISPR32: 0.15 … 30 MHz, QP and AVG,
single power supply
EN 55032/CISPR32: 0.15 … 30 MHz, QP and AVG,
2 power supplies in a system
EN 55032/CISPR32: 30 MHz … 1 GHz, QP,
single power supply
EN 55032/CISPR32: 30 MHz … 1 GHz, QP,
2 power supplies in a system
A-weighted sound power, 25°C, 50% Load
CRITERION
Class A
Class A
Class A
Class A
60 dB (TBD)
Maximum electric strength testing is performed in the factory according to UL/CSA/IEC/EN 62368-1 and IEC 60950-1. Inputto-output electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims
resulting from electric strength field tests.
PARAMETER
Agency Approvals
Isolation Strength
DESCRIPTION / CONDITION
Approved to latest edition of the following standards:
UL/CSA 62368-1 (USA / Canada)
IEC/EN 62368-1, IEC 60950-1 (International/ Europe)
CB Certificate & Report, IEC60950-1, IEC62368-1
(report to include all country national deviations)
Nordics – EMKO-TSE (74-SEC) 207/94
CE - Low Voltage Directive 2014/35/EC (Europe)
GB4943.1- CNCA Certification (China)
CNS14336-1
Input (L/N) to chassis (PE)
Input (L/N) to output
Output to chassis
Electrical Strength Test
NOTE
Approved
Basic
Reinforced
None (Direct connection)
Input to output
4242 VDC
Input to chassis
2121 VDC
Comment: All printed wiring boards and all connectors meet UL94V-0 level.
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The power supply must meet UL enclosure requirements for temperature rise limits. All sides of the power supply with
exception to the air exhaust side must be classified as “Handle, knobs, grips, etc. held for short periods of time only”.
In case the exit air temperature requirement cannot be met, the power supply must have a warning label for high touch
temperature that is in compliance with IEC/UL 60950-1 and additionally 85C rated power cords must also be used with this
power supply.
ITEM
DESCRIPTION
MIN
Load
Maximum typical load under redundant configurations
1320
W
Top1
Operating temperature range; 1800 m
0
50
C
Top2
Operating temperature range; 3050 m
0
45
C
Texit
Maximum exit air temperature
68
C
Tnon-op
Non-operating temperature range
70
C
Altitude1
Maximum operating altitude; 50C inlet
3050
m
Altitude2
Maximum operating altitude; 55C inlet
900
m
-40
MAX
UNITS
Table 12. Requirements for Redundant Power Supply Configuration
ITEM
DESCRIPTION
Load
Maximum rated output load
Top1
Operating temperature range; 900m
Top2
Operating temperature range; 3050m
Texit
Maximum exit air temperature
Tnon-op
Non-operating temperature range
Altitude1
Altitude2
MIN
MAX
UNITS
2200
W
0
50
C
0
45
C
68
C
70
C
Maximum operating altitude; 50C inlet
3050
meters
Maximum operating altitude; 55C inlet
900
meters
-40
Table 13. Requirements for Non-Redundant Power Supply Configuration (High System Ambient)
13.1 HUMIDITY
Operating: To 85% relative humidity (non-condensing)
Non-Operating: To 95% relative humidity (non-condensing)
NOTE: 95% relative humidity is achieved with a dry bulb temperature of 55°C and a wet bulb temperature of 54°C.
13.2 ALTITUDE
Operating: To 3050 m (Maximum operating altitude 5000 meters and the Maximum operating temperature to 40C.)
Non-operating: To 15200 m
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13.3 SHOCK AND VIBRATION
13.3.1
RANDOM VIBRATION – OPERATING
Sample Size: For all product classes and categories, the minimum number of samples shall be 3 devices.
Test Method: The devices shall be tested per the methods described in IEC 60068-2-64, Environmental testing Part 2: Test methods - Test Fh: Vibration, broad-band random (digital control) and guidance. Each device shall
be tested in three axes for a minimum of 30 minutes per axis. The device shall be powered for the duration of the
test at nominal input voltage and no load. For operating vibration testing, see Figure .
Figure 21. Class ll PCDs Operating Vibration Test: Acceleration vs Frequency
The total acceleration for Class ll PCDs is approximately 2.4 g rms (See Table 14)
Frequency
Class I Acceleration Specification
2 2
2
Class II Acceleration Specification
Hz
(m/s ) /Hz
G /Hz
(m/s2)2/Hz
G2/Hz
10
0.022
0.000229
0.1
0.00046
30
0.20
0.0021
2
0.0052
200
0.20
0.0021
2
0.0052
500
0.0052
0.000054
0.2
0.0001
Grms = 0.71
Grms = 2.40
Table 14. Operation Vibration Profile Charts
Pass Criteria: Each power and signal output of each unit under test shall be monitored continuously during the
test. Sampling at greater than 1 millisecond periods is not permitted. The units under test shall operate within
specification during the entire test.
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25
RANDOM VIBRATION - NON-OPERATING
Sample Size: For all product categories and product classes, the minimum number of samples shall be 3
devices packaged in their fully populated, bulk shipping package or individual packages of product.
Test Method: The devices shall be tested per the methods described in IEC 60068-2-64, Environmental testing Part 2: Test methods - Test Fh: Vibration, broad-band random (digital control) and guidance, with the
acceleration spectral density curves provided in this document. The products are in the shipping packaging for
this test. For non-operating vibration testing, see Table 15. Each shipping package shall be tested in three axes
for a minimum of 30 minutes per axis.
The total acceleration for Class II PCDs is approximately 3.8 g rms (See Table 15).
Frequency
Class I Acceleration Specification
Class II Acceleration Specification
Hz
(m/s2)2/Hz
G2/Hz
(m/s2)2/Hz
G2/Hz
5
1
0.01
5
0.0052
200
1
0.01
5
0.0052
500
0.03
0.003
0.3
0.003
Grms = 1.90
Grms = 3.80
Table 15. Non-Operating Vibration Profile Charts
Pass Criteria: At the conclusion of all three axes of testing, the products shall be unpackaged and visually
inspected for any signs of damage. Only minor cosmetic damage that does not affect form, fit or function is
allowed. Bent connector pins, damaged switches, damaged handles, labels with impaired readability, or bent or
deformed sheet metal are not allowed. All units shall also pass a functional test.
There are no requirements on the condition of the shipping package.
13.3.3
SHOCK – OPERATING
Sample Size: For all product types and product classes, the minimum number of samples shall be three devices.
Test Method: The devices shall be tested per the methods described in IEC 60068-2-27, Environmental TestingPart 2.27 Test Ea and guidance: Shock. Each tested device shall be exposed to three shocks in each of 3 axes.
The amplitude of each shock shall be no less than 30 g with a half sine wave shape and a duration of 11mS.
Pass Criteria: Each power and signal output of each unit under test shall be monitored continuously during the
test. Sampling at greater than 1 millisecond periods is not permitted. The units under test shall operate within
specification during the entire test.
13.3.4
THERMAL SHOCK (SHIPPING)
Non-operating: -40°C to +70°C, 50 cycles, 30C/min. transition time 15C/min., duration of exposure to
temperature extremes for each half cycle shall be 30 minutes.
PARAMETER
DESCRIPTION / CONDITION
MIN
MTBF
TA = 40°C, 75% load, according Telcordia SR-332,
issue 2
250
Mean time between failure
NOM
MAX
UNIT
kh
Comment: All components de-rating follows IPC9592B.
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PARAMETER
Dimensions
m
DESCRIPTION / CONDITION
Width
Heigth
Depth
MIN
NOM
MAX
UNIT
80
40
195
mm
mm
mm
1
kg
Weight
Tolerance unless otherwise stated: 0.5-30 mm: +/-0. 3 mm; 30-120 mm: +/-0.4 mm; 120-400 mm: +/-0.5 mm.
Figure 22.1. Top, bottom and side view
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Figure 22.2. Front view
Figure 22.3. Rear view
PARAMETER
DESCRIPTION / CONDITION
AC inlet
IEC 60320 C20
AC cord requirement
Wire size
Output connector
PCB card edge
Manufacturer : FCI Electronics
Manufacturer P/N: 10130248-005LF or 10139371-1824CLF
Refer to Table 16 and Table 17 respectively for the pin assignment, as the FCI pin definition of the 2
connectors are different
Mating output connector
MIN
NOM
MAX
14
UNIT
AWG
Figure 23.1. Rear view
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For Mating output connector 10130248-005LF Pin definition (pic refer to Figure 23.1)
PIN
SIGNAL NAME
P1 ~ P10
GND
P29 ~ P36
GND
P11 ~ P18
V1
P19 ~ P28
V1
S1
A0
S2
A1
S3, S4
VSB
S5
Hot_ Standby
S6
ISHARE
S7
Mating Sequence4
DESCRIPTION
Power and signal ground (return)
1
+12VDC main output
2
1
I2C address selection input
1
+12V Standby positive output (as pins S3, S4)
1
Hot standby Bus
1
Analog current share bus
1
VIN_OK _H
Input OK signal output, active-high
1
S8
PRESENT_L
Power supply seated, active-low
3
S9
A2
I2C address selection input
1
Power and signal ground (return)
1
Power OK signal output, active-high
1
S10 ~ S15
GND
S16
PWOK_H
S17
V1_SENSE
Main output positive sense
1
S18
V1_SENSE_R
Main output negative sense
1
S19
SMB_ALERT_L
SMB Alert signal output, active-low
1
S20
PSON_L
Power supply on input, active-low
3
S21, S22
VSB
+12V Standby positive output (as pins S3, S4)
1
S23
SCL
I2C clock signal line
1
S24
SDA
I2C data signal line
1
4
1 = First, 3 = Last, given by different card edge finger pin lengths and mating connector pin arrangement
Table 16. Output connector pin assignment
Figure 23.2. Rear view
.
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For Mating output connector 10139371-1824CLF Pin definition (pic refer to Figure 23.2)
PIN
SIGNAL NAME
P1 ~ P5
P15 ~ P18
P6 ~ P9
GND
GND
V1
P10 ~ P14
V1
S1
S2
S3, S4
A0
A1
VSB
S5
Hot_ Standby
S6
ISHARE
S7
Mating Sequence4
DESCRIPTION
Power and signal ground (return)
1
+12 VDC main output
2
I2C address selection input
+12 V Standby positive output
1
1
1
Hot standby Bus
1
Analog current share bus
1
VIN_OK_H
Input OK signal output, active-high
1
S8
PRESENT_L
Power supply seated, active-low
3
S9
A2
I2C address selection input
1
Power and signal ground (return)
1
Power OK signal output, active-high
1
S10 ~ S15
GND
S16
PWOK_H
S17
V1_SENSE
Main output positive sense
1
S18
V1_SENSE_R
Main output negative sense
1
S19
SMB_ALERT_L
SMB Alert signal output, active-low
1
S20
PSON_L
Power supply on input, active-low
3
S21, S22
VSB
+12 V Standby positive output (as pins S3, S4)
1
S23
SCL
I2C clock signal line
1
S24
SDA
I2C data signal line
1
4
1 = First, 3 = Last, given by different card edge finger pin lengths and mating connector pin arrangement
Table 17. Output connector pin assignment
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ITEM
ORDERING PART
NUMBER
SOURCE
I2C Utility
Windows XP/Vista/7 compatible GUI
to program, control and monitor
Front-End power supplies (and other
I2C units)
N/A
belfuse.com/power-solutions
Evaluation Board
Connector board to operate
PES2200-12-080A. Includes an onboard USB to I2C converter (use I2C
Utility as desktop software).
YTM.00103 (TBD)
belfuse.com/power-solutions
DESCRIPTION
It is recommended to add each a width 18 mm x thickness 1 mm x length 35 mm busbar for 12 V+/- on loading board as such
high output current density.
Maximum electric strength testing is performed in the factory according to UL/CSA/IEC/EN 62368-1 and IEC 60950-1. Input-tooutput electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims
resulting from electric strength field tests.
DATE
REVISION
SECTION
2018/07/26
001
/
ISSUE
First release
Add 10139371-1824CLF connector pin defined and picture,
add mating input connector to table
Fix the EMI immunity performance to A; Increase low line
power output to at least 1155 W;
Update Efficiency and Power Factor curve;
I2C spec rise time from 300 ns to 1000 ns
Remove the ‘typical ambient’ table.
PREPARED BY
ECO/MCO
REFERENCE NO.
Zhiqun Wan
2018/08/08
002
15&16
2019/01/09
003
/
2019/4/9
004
/
Update monitoring date, add power derating curve
Zhiqun Wan
2019/6/5
005
/
Add RA version
Zhiqun Wan
2019/7/30
005
/
Change the pictures of page 1 and Figure 21
Ryan Li
C95037
/
Adjust the description in Table 3.
Correct some tables and pictures with incorrect bit numbers;
Change EMC standards from EN 55022/CISPR22 to EN
55032/CISPR32;
Change Safety standards from 60950 to 62368.
Jonas Wu
CO110340
2021/1/26
A
Ryan Li
Zhiqun Wan
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
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