The PFE3000-12-069RA is a 3000 Watt AC/DC power-factorcorrected (PFC) and DC-DC power supply that converts standard AC
mains power or high voltage DC bus voltages into a main output of
12 VDC for powering intermediate bus architectures (IBA) in high
performance and reliability servers, routers, and network switches.
The PFE3000-12-069RA meets international safety standards and
displays the CE-Mark for the European Low Voltage Directive (LVD).
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Best-in-class, Platinum efficiency
Wide input voltage range: 90-300 VAC
AC input with power factor correction
DC input voltage range: 192-400 VDC
Hot-plug capable
Parallel operation with active current sharing thru analog bus
Full digital controls for improved performance
High density design: 30.5 W/in3
Small form factor: 555 x 69 x 42 mm (21.85 x 2.72 x 1.65 in)
I2C communication interface with Power Management Bus protocol for
monitoring, control, and firmware update via bootloader
Overtemperature, output overvoltage and overcurrent protection
RoHS Compliant
2 Status LEDs: AC OK and DC OK with fault signaling
Safety-approved to IEC/EN 60950-1 and UL/CSA 60950-1 2nd ed.
US Patent Pending
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High Performance Servers
Routers
Switches
PFE3000-12-069RA
2
PFE
3000
Product Family
Power Level
PFE Front-Ends
3000 W
Dash
12
V1 Output
-
069
Dash
12 V
R
A
Option Code
Blank: Standard model
S366: Screw for Key-in
feature is installed.
Width
Airflow
Input
69 mm
R: Reversed1
A: AC
Front to Rear
The PFE3000-12-069RA is a fully DSP controlled, highly efficient front-end power supply. It incorporates resonant-soft-switching
technology and interleaved power trains to reduce component stresses, providing increased system reliability and very high
efficiency. With a wide input operating voltage range and minimal linear derating of output power with respect to ambient
temperature, the PFE3000-12-069RA maximizes power availability in demanding server, switch, and router applications. The power
supply is fan cooled and ideally suited for server integration with a matching airflow path.
The PFC stage is digitally controlled using a state-of-the-art digital signal processing algorithm to guarantee best efficiency and
unity power factor over a wide operating range.
The DC-DC stage uses soft switching resonant techniques in conjunction with synchronous rectification. An active OR-ing device
on the output ensures no reverse load current and renders the supply ideally suited for operation in redundant power systems.
The always-on +12V standby output provides power to external power distribution and management controllers. Its protection with
an active OR-ing device provides for maximum reliability.
Status information is provided with front-panel LEDs. In addition, the power supply can be monitored and controlled (i.e. fan speed
setpoint) via I2C communication interface with Power Management Bus protocol. It allows full monitoring of the supply, including
input and output voltage, current, power, and inside temperatures. The same I2C bus supports the bootloader to allow field update
of the firmware in the DSP controllers.
Cooling is managed by a fan, controlled by the DSP controller. The fan speed is adjusted automatically depending on the actual
power demand and supply temperature and can be overridden through the I2C bus.
L
V1
DC
Vsb
Filter
+12V
SB
PFC
DC
N
Aux
Converter
EEPROM
FAN
PWM
PE
GND
PWM
1
-
Digital
Prim
Controls
Communication Bus
V1Sense+
Digital
Sec
Controls
V1SenseI2C
Logic Signals
Figure 1 - PFE3000-12-0069RA Block Diagram
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PFE3000-12-069RA
3
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliability, and
cause permanent damage to the supply.
PARAMETER
CONDITIONS / DESCRIPTION
Vi maxc
Continuous
Maximum Input
MIN
MAX
UNITS
300
VAC
General Condition: TA = 0… 45 °C unless otherwise noted.
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
100
230
277
VAC
Vi nom
AC Nominal Input Voltage
Vi
AC Input Voltage Ranges
Vinom DC
DC Nominal input voltage
Vi DC
DC Input voltage ranges
Vi red
Derated Input Voltage
Range
Ii max
Max Input Current
Ii p
Inrush Current Limitation
Fi
Input Frequency
PF
Power Factor
Vi nom, 50Hz, > 0.3 I1 nom
Vi on
Turn-on Input Voltage2
Ramping up
80
87
VAC
Vi off
Turn-off Input Voltage2
Ramping down
73
85
VAC
η
Normal operating (Vi min to Vi max)
90
300
VAC
240
380
VDC
Normal operating (Vi min to Vi max)
192
400
VDC
See Figure 20 and Figure 33
90
180
VAC
Vi > 200 VAC, >100 VAC
17
Arms
Vi min to Vi max, 0 ° TNTC = 25°C (Figure 5)
50
Ap
47
50/60
Hold-up Time
2
Hz
W/VA
Vi nom, 0.1∙Ix nom, Vx nom, TA = 25°C
90.0
91.85
Vi nom, 0.2∙Ix nom, Vx nom, TA = 25°C
93.0
94.40
Vi nom, 0.5∙Ix nom, Vx nom, TA = 25°C
94.5
94.95
Vi nom, Ix nom, Vx nom, TA = 25°C
After last AC zero point, V1 > 10.8 V,
VSB within regulation, Vi = 230 VAC, Px nom
93.0
93.75
Efficiency without Fan
Thold
63
0.96
%
12
ms
The Front-End is provided with a minimum hysteresis of 3 V during turn-on and turn-off within the ranges
4.1 INPUT FUSE
Quick-acting 25 A input fuses (6.3 × 32 mm) in series with both the L- and N-line inside the power supply protect against severe
defects. The fuses are not accessible from the outside and are therefore not serviceable parts.
4.2 INRUSH CURRENT
The AC-DC power supply exhibits an X capacitance of only 4.3μF, resulting in a low and short peak current, when the supply is
connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current.
NOTE:
Do not repeat plug-in / out operations below 90sec interval time at maximum input, high temperature condition, or else the
internal in-rush current limiting device (NTC) may not sufficiently cool down and excessive inrush current or component failure(s)
may result.
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PFE3000-12-069RA
4
4.3 INPUT UNDER-VOLTAGE
If the RMS value of input voltage (either AC or DC) stays below the input undervoltage lockout threshold Vi on, the supply will
be inhibited. Once the input voltage returns within the normal operating range, the supply will return to normal operation again.
4.4 POWER FACTOR CORRECTION
Power factor correction (PFC) (see Figure 4) is achieved by controlling the input current waveform synchronously with the input
voltage. A fully digital controller is implemented giving outstanding PFC results over a wide input voltage and load ranges. The
input current will follow the shape of the input voltage. If for instance the input voltage has a trapezoidal waveform, then the
current will also show a trapezoidal waveform. At DC input voltage the PFC is still in operation, but the input current will be DC
in this case.
4.5 EFFICIENCY
96
96
95
95
94
94
93
93
Efficiency [%]
Efficiency [%]
The high efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft-transition
topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the losses
in the high current output path. The rpm of the fan is digitally controlled to keep all components at an optimal operating
temperature regardless of the ambient temperature and load conditions.
Figure 3 shows efficiency when input voltage is supplied from a high voltage DC source.
92
91
Vi = 230Vac, fan internal
Vi = 230Vac, fan external
Platinum
90
89
500
1000
1500
2000
2500
91
Vi = 380Vdc, fan internal
Vi = 380Vdc, fan external
Platinum
90
89
88
0
92
3000
Po [W]
Figure 2 – AC Input Efficiency vs. Load current
(ratio metric loading)
88
0
500
1000
1500
Po [W]
2000
2500
3000
Figure 3 - DC Input Efficiency vs. load current
(ratio metric loading)
1
Power factor
0.96
0.92
0.88
Vi = 230Vac
Vi = 277Vac
Vi = 300Vac
0.84
0.8
0
500
1000
1500
2000
2500
3000
Po [W]
Figure 4 - Power factor vs. Load current
Figure 5 - Inrush current, Vin = 230 Vac, 0°phase angle
CH4: Vin (200 V/div), CH3: Iin (10 A/div)
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General Condition: TA = 0…45 °C unless otherwise noted.
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
Main Output V1
V1 nom
Nominal Output Voltage
V1 set
Output Setpoint Accuracy
dV1 tot
Total Regulation
Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max
P1 nom
Nominal Output Power
V1 = 12.3 VDC, Vin < 180 VAC
1400
W
I1 nom
Nominal Output Current
V1 = 12.3 VDC, Vin < 180 VAC
114
ADC
P1 nom
Nominal Output Power
V1 = 12.3 VDC, Vin > 180 VAC
3000
W
I1 nom
Nominal Output Current
244
ADC
IV1 ol
Short time over load current
V1 = 12.3 VDC, Vin > 180 VAC
V1 = 12.3 VDC, Vin > 180 VAC
Ta min to Ta max, maximum duration 20 ms
v1 pp
Output Ripple Voltage
(See Section 5.2)
V1 nom, I1 nom, 20 MHz BW (See Section 5.1)
dV1 Load
Load Regulation
Vi = Vi nom, 0 - 100 % I1 nom
dV1 Line
Line Regulation
Vi =Vi min…Vi max
Vi < 180 VAC, Ta < 45°C
Vi < 180 VAC, Ta = 55 °C 3)
Vi > 180 VAC, Ta < 45°C
Vi > 180 VAC, Ta = 55 °C 3)
Deviation from I1 tot / N, I1 > 25% I1 nom
ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom,
dI1/dt = 1A/μs, f ΔI1 = 0.05...10 kHz,
12.3
0.5 ∙I1 nom, Tamb = 25 °C
-0.5
+0.5
% V1 nom
-1
+1
% V1 nom
292
A
160
mVpp
170
IV1 ol lim
Current limitation
dIshare
Current Sharing
dVdyn
Dynamic Load Regulation
Trec
Recovery Time
tAC V1
Start-up Time from AC
V1 = 10.8 VDC (see Figure 7)
tV1 rise
Rise Time
V1 = 10…90% V1 nom (see Figure 8)
CLoad
Capacitive Loading
Ta = 25°C
3
VDC
mV
0
Duty ΔI1 = 10...90%, recovery within 1% of V1 final
steady state
mV
120
92
248
186
-5%
127
99
274
212
+5%
-0.6
+0.6
ADC
A
V
0.5
ms
3
sec
2.5
ms
30000
μF
+0.5
%VSBnom
+1
%VSBnom
See Figure 20 for linear derating > 45°C
Stanby Output VSB
VSB nom
Nominal Output Voltage
VSB set
Output Setpoint Accuracy
dVSB tot
Total Regulation
Vi min to Vi max, ISB nom, Ta min to Ta max
PSB nom
Nominal Output Power
VSB = 12 VDC
60
W
ISB nom
Nominal Output Current
VSB = 12 VDC
5
ADC
VSB pp
Output Ripple Voltage
VSB nom, ISB nom, 20 MHz BW (See Section 5.1)
dVSB
Droop
0 - 100 % ISB nom
IVSB lim
Current Limitation
12
ISB nom, Tamb = 25°C
-0.5
-1
VDC
300
400
ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom,
dIo/dt = 1A/μs, f ΔI1 = 0.05...10kHz, Duty ΔI1 =
10...90%, recovery within 1% of VSB final steady
state
dVSBdyn
Dynamic Load Regulation
Trec
Recovery Time
tAC VSB
Start-up Time from AC
VSB = 90% VSB nom (see Figure 7)
tVSB rise
Rise Time
VSB = 10…90% VSB nom (see Figure 9)
CLoad
Capacitive Loading
Tamb = 25°C
mVpp
mV
6
9
ADC
-0.6
+0.6
VSBnom
0.5
ms
3
sec
10
ms
3000
μF
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6
5.1 OUTPUT VOLTAGE RIPPLE
The internal output capacitance at the power supply output (behind OR-ing element) is minimized to prevent disturbances
during hot plug. In order to provide low output ripple voltage in the application, external capacitors should be added close to
the power supply output.
The setup of Figure 6 has been used to evaluate suitable capacitor types. The capacitor combinations of Table 1 and Table 2
should be used to reduce the output ripple voltage.
The ripple voltage is measured with 20 MHz BWL, close to the external capacitors.
L
Vout
N
C
PSU
Probe
Load
Gnd
Scope
20MHz BW
Figure 6 - Output Ripple Test Setup
NOTE: Care must be taken when using ceramic capacitors with a total capacitance of 1 µF to 50 µF on output V1, due to their
high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects.
External Capacitor V1
dV1max
Unit
External capacitor VSB
dVSBmax
Unit
2Pcs 47µF/16V/X5R/1210
160
mVpp
1Pcs 10µF/16 V/X7R/1206
300
mVpp
160
mVpp
160
mVpp
90
mVpp
1Pcs 1000µF/16V/Low ESR
Aluminum/ø10x20
1Pcs 270µF/16V/Conductive
Polymer/ø8x12
2Pcs 47µF/16V/X5R/1210 plus
1Pcs 270µF Conductive Polymer OR
1Pcs 1000µF Low ESR AlCap
Table 1 - Suitable Capacitors for V1
Table 2 - Suitable Capacitors for VSB
The output ripple voltage on VSB is influenced by the main output V1. Evaluating VSB output ripple must be done when
maximum load is applied to V1.
5.2 SHORT TIME OVERLOAD
The main output has the capability to allow load current up to 20% above the nominal output current rating for a maximum
duration of 20 ms. This allows the system to consume extended power for short time dynamic processes.
5.3 OUTPUT ISOLATION
Main and standby output and all signals are isolated from the chassis and protective earth connection, although the applied
voltage must not exceed 100 Vpeak to prevent any damage of the supply.
Internal to the supply the main output ground, standby output ground and signal ground are interconnected through 10Ω
resistors to prevent any circulating current within the supply. In order to prevent any potential difference in outputs or signals
within the application these 3 grounds must be directly interconnected at system level. See also section 14 for pins to be
interconnected.
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Figure 7 - Turn-On AC Line 230 VAC, full load (500 ms/div)
CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div)
Figure 8 - Turn-On AC Line 230 VAC, full load (1 ms/div)
CH1: V1 (2 V/div)
Figure 9 - Turn-On AC Line 230 VAC, full load (5 ms/div)
CH2: VSB (2 V/div)
Figure 10 - Turn-Off AC Line 230 VAC, full load (20 ms/div)
CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div)
Figure 11 - Short circuit on V1 (50ms/div)
CH1: V1 (2V/div) CH2: VSB (2V/div) CH4: I1 (200A/div)
Figure 12 - AC drop out 12ms (10ms/div)
CH1: V1 (2V/div) CH2: VSB (2V/div) CH3: Vin (200V/div)
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PFE3000-12-069RA
8
Figure 13 - AC drop out 40 ms, full load (20 ms/div)
CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div)
Figure 14 - AC drop out 40 ms, full load (200 ms/div),V1 restart
after 1 sec CH1: V1 (5 V/div); CH2: VSB (2 V/div);
CH3: I1 (200 V/div)
Figure 15 - Load transient V1, 3 to 125 A (500 μs/div)
CH1: V1 (200 mV/div); CH4: I1 (100 A/div)
Figure 16 - Load transient V1, 125 to 3 A (500 μs/div)
CH1: V1 (200 mV/div); CH4: I1 (100 A/div)
Figure 17 - Load transient V1, 122 to 244 A (500 μs/div)
CH1: V1 (200 mV/div); CH4: I1 (100 A/div)
Figure 18 - Load transient V1, 244 to 122 A (500 μs/div)
CH1: V1 (200 mV/div); CH4: I1 (100 A/div)
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PFE3000-12-069RA
9
PARAMETER
DESCRIPTION / CONDITION
F
Input Fuses (L+N)
Not user accessible, quick-acting (F)
V1 OV
OV Threshold V1
tOV V1
OV Latch Off Time V1
VSB OV
OV Threshold VSB
tOV VSB
OV Latch Off Time VSB
Ta < 45°C
Ta = 55 °C 4
Ta < 45°C
Ta = 55 °C 4
MIN
NOM
MAX
25
A
13.6
14.2
14.8
1
ms
13.3
13.9
14.5
VDC
1
ms
A
ms
IV1 lim
Current limitation
tV1 lim
Current limit blanking time
Time to latch off when in over current
20
22
24
IV1 ol lim
Current limit during short time
overload V1
Maximum duration 20 ms
292
300
308
Max Short Circuit Current V1
V1 < 3 V
tV1 SC off
Short circuit latch off time
Time to latch off when in short circuit
IVSB lim
Current limitation VSB
tVSB lim
Current limit blanking time
Over temperature on critical points
TSD
4
5
120
92
248
186
350
5
10
6
VDC
127
99
274
212
Vi < 180 VAC,
Vi < 180 VAC,
Vi > 180 VAC,
Vi > 180 VAC,
IV1 SC
UNIT
A
A
ms
9
A
Time to hit hiccup when in over current
1
ms
Inlet Ambient Temperature
PFC Primary Heatsink Temperature
Secondary Sync Mosfet Temperature
Secondary OR-ing Mosfet Temperature
60
80
115
125
°C
See Figure 20 for linear derating > 45°
Limit set don’t include effects of main output capacitive discharge.
6.1 AUTOMATIC RETRY
For all fault conditions except current limitation on Standby output, the supply will shut down for 10sec and restart
automatically. The supply will auto-restart from a fault up to 5 times, after that it will latch off. The latch and restart counter
can be cleared by recycling the input voltage or the PSON_L input. A failure on the Standby output will shut down both Main
and Standby outputs. A failure on the Main output will shut down only the Main output, while Standby continues to operate.
6.2 OVERVOLTAGE PROTECTION
The PFE front-ends provide a fixed threshold overvoltage (OV) protection implemented with a HW comparator. Once an OV
condition has been triggered, the supply will shut down and latch the fault condition.
6.3 UNDERVOLTAGE DETECTION
Both main and standby outputs are monitored. LED and PWOK_L pin signal if the output voltage exceeds ±7% of its nominal
voltage.
Output undervoltage protection is provided on both outputs. When either V1 or VSB falls below 93% of its nominal voltage,
the output is inhibited.
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10
6.4 CURRENT LIMITATION
MAIN OUTPUT
Two different over current protection features are implemented on the main output.
A static over current protection will shut down the output, if the output current does exceed I V1 lim for more than 20 ms. If the
output current is increased slowly this protection will shut down the supply. The main output current limitation level IV1 lim will
decrease if the ambient (inlet) temperature increases beyond 45 °C (see Figure 20). Note that the actual current limitation on
V1 will kick in at a current level approximately 20 A higher than what is shown in Figure 20 (see also section 9 for additional
information).
The 2nd protection is a substantially rectangular output characteristic controlled by a software feedback loop. This protects the
power supply and system during the 20ms blanking time of the static over current protection. If the output current is rising fast
and reaches IV1 ol lim, the supply will immediately reduce its output voltage to prevent the output current from exceeding IV1 ol lim.
When the output current is reduced below IV1 ol lim, the output voltage will return to its nominal value.
250
10
8
6
4
Force Current Limitation
2
Static Over Current
Protection
0
0
100
200
300
Main Output Nominal Current [A]
Main Output Voltage [V]
12
200
150
100
Nominal Current > 180Vac
Current Limitation > 180Vac
Nominal Current < 180Vac
Current Limitation < 180Vac
50
0
0
11
22
33
44
55
Ambient Temperature [°C]
Main Output Current [A]
Figure 19 - Current Limitation on V1 (Vi = 230VAC)
Figure 20 - Derating on V1 vs. Ta
STANDBY OUTPUT
On the standby output a hiccup type over current protection is implemented. This protection will shut down the standby output
immediately when standby current reaches or exceeds IVSB lim. After an off-time of 1s the output automatically tries to restart.
If the overload condition is removed the output voltage will reach again its nominal value. At continuous overload condition the
output will repeatedly trying to restart with 1s intervals.
Standby Output Voltage [V]
12
10
8
6
4
2
0
0
2
4
6
8
Standby Output Current [A]
Figure 21 - Current Limitation on VSB
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11
PARAMETER
DESCRIPTION / CONDITION
MIN
Vi mon
Vi min ≤ Vi ≤ Vi max
Ii mon
Pi mon
Input RMS Voltage
Input RMS Current
True Input Power
Ei mon
Total Input Energy
V1 mon
V1 Voltage
I1 mon
V1 Current
Po nom
Total Output Power
Eo mon
Total Output Energy
VSB mon
Standby Voltage
ISB mon
Standby Current
NOM
MAX
UNIT
-2.5
+2.5
%
Ii > 4 Arms
-5
+5
%
Ii ≤ 4 Arms
-0.2
+0.2
Arms
Pi > 700 W
-5
+5
%
Pi ≤ 700 W
-35
+35
W
Pi > 700 W
-5
+5
%
Pi ≤ 700 W
-35
+35
Wh
-2
+2
%
I1 > 30 A
-2
+2
%
I1 ≤ 30 A
-0.6
+0.6
A
Po > 200 W
-5
+5
%
Po ≤ 200 W
-10
+10
W
Po > 200 W
-5
+5
%
Po ≤ 200 W
-10
+10
Wh
-2
+2
%
-0.3
+0.3
A
ISB ≤ ISB nom
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PFE3000-12-069RA
12
8.1 ELECTRICAL CHARACTERISTICS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
V
PSKILL / PSON_L inputs
VIL
Input low level voltage
-0.2
0.8
VIH
Input high level voltage
2.0
3.6
V
IIL, H
Maximum input sink or source current
0
1
mA
RpuPSKILL
Internal pull up resistor on PSKILL
10
kΩ
RpuPSON_L
Internal pull up resistor on PSON_L
10
kΩ
PWOK_L output
VOL
Output low level voltage
VpuPWOK_L
External pull up voltage
RpuPWOK_L
Recommended external pull up resistor on
PWOK_L at VpuPWOK_L = 3.3 V
Low level output
All outputs are turned on and within regulation
High level output
In standby mode or V1/VSB have triggered a
fault condition
Isink < 4 mA
-0.2
0.4
V
12
V
kΩ
10
INOK_L output
VOL
Output low level voltage
VpuINOK_L
External pull up voltage
RpuINOK_L
Recommended external pull up resistor on
INOK_L at VpuINOK_L= 3.3 V
Low level output
Input voltage is within range for PSU to operate
High level output
Input voltage is not within range for PSU to
operate
Isink < 4 mA
-0.2
0.4
V
12
V
kΩ
10
SMB_ALERT_L output
VOL
Output low level voltage
VpuSMB_ALERT_L
External pull up voltage
RpuSMB_ALERT_L
Recommended external pull up resistor on
SMB_ALERT_L at VpuSMB_ALERT_L= 3.3 V
Low level output
PSU in warning or failure condition
High level output
PSU is ok
Isink < 4 mA
-0.2
10
0.4
V
12
V
kΩ
8.2 INTERFACING WITH SIGNALS
A 15V zener diode is added on all signal pins versus signal ground SGND to protect internal circuits from negative and high
positive voltage. Signal pins of several supplies running in parallel can be interconnected directly. A supply having no input
power will not affect the signals of the paralleled supplies.
ISHARE pins must be interconnected without any additional components. This in-/output also has a 15 V zener diode as a
protection device and is disconnected from internal circuits when the power supply is switched off.
8.3 FRONT LEDs
The front-end has 2 front LEDs showing the status of the supply. LED number one is green and indicates AC power is on or
off, while LED number two is bi-colored: green and yellow, and indicates DC power presence or fault situations. For the position
of the LEDs see Table 3 listing the different LED status.
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PFE3000-12-069RA
13
OPERATING CONDITION
LED SIGNALING
AC LED
AC Line within range
Solid Green
AC Line UV condition
Off
DC LED *
Normal Operation
Solid Green
PSON_L High
Blinking Yellow (1:1)
V1 or VSB out of regulation
Over temperature shutdown
Output over voltage shutdown (V1 or VSB)
Solid Yellow
Output under voltage shutdown (V1 or VSB)
Output over current shutdown (V1 or VSB)
Over temperature warning
Blinking Yellow/Green (2:1)
Minor fan regulation error (>5%, 25 ms with recovery
within 10 ms
Recognizes any time Start/Stop bus conditions
3.3V
RX
3.3V
100kΩ
TX
Rpull-up
SDA/SCL
PFE
Figure 27 - Physical layer of communication interface
The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should
investigate. This is a logical OR of the Shutdown and Warning events.
Communication to the DSP or the EEPROM will be possible as long as the input AC (DC) voltage is provided. If no AC (DC) is
present, communication to the unit is possible as long as it is connected to a live VSB output (provided e.g. by the redundant
unit). If only V1 is provided, communication is not possible.
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
UNIT
ViL
ViH
Input low voltage
-0.2
0.4
V
Input high voltage
2.1
3.6
V
Vhys
Input hysteresis
VoL
Output low voltage
tr
Rise time for SDA and SCL
tof
Output fall time ViHmin → ViLmax
10 pF < Cb* < 400 pF
Ii
Input current SCL/SDA
0.1 VDD < Vi < 0.9 VDD
Ci
Capacitance for each SCL/SDA
fSCL
SCL clock frequency
Rpu
External pull-up resistor
fSCL ≤ 100 kHz
tHDSTA
Hold time (repeated) START
fSCL ≤ 100 kHz
4.0
μs
tLOW
Low period of the SCL clock
fSCL ≤ 100 kHz
4.7
μs
tHIGH
High period of the SCL clock
fSCL ≤ 100 kHz
4.0
μs
tSUSTA
Setup time for a repeated START
fSCL ≤ 100 kHz
4.7
μs
tHDDAT
Data hold time
fSCL ≤ 100 kHz
0
tSUDAT
Data setup time
fSCL ≤ 100 kHz
250
ns
tSUSTO
Setup time for STOP condition
fSCL ≤ 100 kHz
4.0
μs
tBUF
Bus free time between STOP and START
fSCL ≤ 100 kHz
4.7
μs
0.15
4 mA sink current
V
0
0.4
V
20+0.1Cb*
300
ns
20+0.1Cb*
250
ns
-10
10
μA
10
pF
0
100
kHz
1000 ns / Cb*
3.45
Ω
μs
EEPROM_WP
ViL
Input low voltage
-0.2
0.4
ViH
Input high voltage
2.1
3.6
V
Ii
Input sink or source current
-1
1
mA
Rpu
Internal pull-up resistor to 3.3V
10k
V
Ω
* Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF
Table 8 - I2C / SMBus Specification
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PFE3000-12-069RA
tof
tLOW
17
tHIGH
tLOW
tr
SCL
tSUSTA
tHDSTA
tHDDAT tSUDAT
tSUSTO
tBUF
SDA
Figure 28 - I2C / SMBus Timing
8.12
ADDRESS
The supply supports Power Management Bus communication protocol. Its address is fixed to 0x20. The EEPROM is at fixed
address = 0xA0.
8.13
CONTROLLER AND EEPROM ACCESS
The controller and the EEPROM in the power supply share the same I2C bus physical layer (see Figure 29).
In order to write to the EEPROM, the write protection needs to be disabled by setting EEPROM_WP input correctly.
If EEPROM_WP is High, write is not allowed to the EEPROM and if Low, write is allowed. The EEPROM provides 2k bytes of
user memory. None of the bytes are used for the operation of the power supply.
Address
3.3V
SDAi
SDA
DSP
SCLi
SCL
EEPROM_WP
WP
EEPROM
Addr
Protection
PFE
Figure 29 - I2C Bus to DSP and EEPROM
8.14
EEPROM PROTOCOL
The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read
commands are defined, it is recommended to use the single byte write / read commands.
WRITE
The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte
with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus
should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.
S Address W A
Data Address
A
Data
A
P
READ
The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data
address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the
data byte at the specified location.
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PFE3000-12-069RA
18
S Address W A
S Address R
8.15
Data Address
A
Data
A
nA P
POWER MANAGEMENT BUS PROTOCOL
The Power Management Bus is an open standard protocol that defines means of communicating with power conversion and
other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org.
Power Management Bus command codes are not register addresses. They describe a specific command to be executed.
PFE3000-12-069RA supply supports the following basic command structures:
•
Clock stretching limited to 1 ms
•
SCL low time-out of >25 ms with recovery within 10 ms
•
Recognized any time Start/Stop bus conditions
WRITE
The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte
or after the first data byte (Byte command) or then after sending 2 data bytes (Word command).
S Address W A
Data Low Byte1) A
1)
Command
A
Data High Byte1) A
P
Optional
In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE3000-12-069RA Power
Management Bus Communication Manual BCA.00070 for further information.
S Address W A
Byte 1
Command
A
A
Byte Count
A
Byte N
A
P
READ
The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word.
S Address W A
S Address R
1)
A
Command
A
Data (Low) Byte A
Data High Byte1) nA P
Optional
In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE3000-12-069RA Power
Management Bus Communication Manual BCA.00070 for further information.
S Address W A
Byte Count
A
Command
Byte 1
A
A
S Address R
Byte N
A
nA P
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PFE3000-12-069RA
8.16
19
GRAPHICAL USER INTERFACE
Bel Power Solutions I2C Utility provides a Windows® Vista/Win7/8 compatible graphical user interface allowing the
programming and monitoring of the PFE3000-12-069RA Front-End. The utility can be downloaded on
belfuse.com/power-solutions and supports the Power Management Bus protocol.
The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation
tree. In the monitoring view the power supply can be controlled and monitored.
If the GUI is used in conjunction with the PFE3000-12-069RA Evaluation Kit it is also possible to control the PSON_L pin(s) of
the power supply.
Figure 30 - Monitoring dialog of the I2C Utility
To achieve best cooling results sufficient airflow through the supply must be ensured. Do not block or obstruct the airflow at
the rear of the supply by placing large objects directly at the output connector. The PFE3000-12-069RA is provided with a
reverse airflow, which means the air enters through the front of the supply and leaves at the rear. PFE supplies have been
designed for horizontal operation.
The fan inside of the supply is controlled by a microprocessor. The rpm of the fan is adjusted to ensure optimal supply cooling
and is a function of output power and the inlet temperature.
Reverse Air Flow Direction
Figure 31 - Airflow Direction
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PFE3000-12-069RA
20
3000
20
Main Output Power [W]
Fan Speed [1000xRPM]
25
15
10
25°C
45°C
55°C
5
2250
1500
750
Vi > 180VAC
Vi < 180VAC
0
0
0%
20%
40%
60%
80%
100%
0
Main Output Current [%]
Figure 32 - Fan speed vs. main output load for
PFE3000-12-069RA
10.1
11
22
33
Ambient Temperature [°C]
44
55
Figure 33 - Thermal derating for PFE3000-12-069RA
IMMUNITY
NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003.
PARAMETER
DESCRIPTION / CONDITION
CRITERION
IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point
(metallic case, LEDs, connector body)
IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point
(non-metallic user accessible surfaces)
IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation,
1 µs Pulse Modulation, 10 kHz…2 GHz
IEC / EN 61000-4-4, level 3
AC port ±2 kV, 1 minute
DC port ±1 kV, 1 minute
IEC / EN 61000-4-5
Line to earth: level 3, ±2 kV
Line to line: level 2, ±1 kV
A
A
A
A
A
IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz
A
IEC/EN 61000-4-11
1: Vi 230Volts, 100% Load, Dip 100%, Duration 12ms
2: Vi 230Volts, 100% Load, Dip 100%, Duration < 150 ms
3. Vi 230Volts, 100% Load, Dip 100%, Duration > 150 ms
A
V1: B, VSB: A
B
PARAMETER
DESCRIPTION / CONDITION
CRITERION
Conducted Emission
EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG
Class A
Radiated Emission
EN55022 / CISPR 22: 30 MHz … 1 GHz, QP
Class A
Harmonic Emissions
IEC61000-3-2, Vin = 115/230 VAC, 50 Hz, 100% Load
Sound power statistical declaration (ISO 9296, ISO 7779, IS9295)
@ 50% load
IEC / EN 61000-3-3, dmax < 3.3%
Class A
10.2
EMISSION
Acoustical Noise
AC Flicker
60 dBA
PASS
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PFE3000-12-069RA
21
Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output
electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims resulting
from electric strength field tests.
PARAMETER
Agency Approvals
Isolation Strength
dC
MIN
Approved to the latest edition of the following standards:
• IEC60950-1 2nd edition (CB)
• EN60950-1 2nd Edition (Nemko)
• UL/CSA0950-1 2nd Edition (cCSAus)
• CNS14336-1, CNS13438 (BSMI)
• EAC, TR-CU (Russia)
• BIS, (India)
• KCC Safety/EMC, (South Korea)
Input (L/N) to case (PE)
Input (L/N) to output
Output to case (PE)
NOM
MAX
UNIT
Basic
Reinforced
Functional
Creepage / Clearance
Primary (L/N) to protective earth (PE)
Primary to secondary
Electrical Strength Test
Input to case
Input to output (tested by manufacturer only)
2121
4242
DESCRIPTION / CONDITION
MIN
PARAMETER
TA
DESCRIPTION / CONDITION
VDC
NOM
MAX
UNIT
Vi min to Vi max, I1 nom, ISB nom at 4000 m
0
+35
°C
Vi min to Vi max, I1 nom, ISB nom at 1800 m
0
+45
°C
Ambient Temperature
TAext
Extended Temp. Range
Derated output (see Figure 20 and Figure 33) at 1800 m
+45
+55
°C
TS
Storage Temperature
Non-operational
-40
+70
°C
Altitude
Operational, above Sea Level (see derating)
Audible Noise
Vi nom, 50% Io nom, TA = 25°C
Cooling
System Back Pressure
Na
PARAMETER
Dimensions
m
-
4000
60
DESCRIPTION / CONDITION
MIN
NOM
m
dBA
0.5
in-H20
MAX
UNIT
Width
69
mm
Heigth
42
mm
Depth
555
mm
2.60
kg
Weight
NOTE: A 3D step file of the power supply casing is available on request.
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PFE3000-12-069RA
22
Figure 34 - Bottom view
Figure 35 - Side view
Figure 36 - Top view
Figure 37 - Front and Rear view
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PFE3000-12-069RA
23
Figure 38 - PFE3000-12-069RA with Key-in screw dimension (Option code S366)
Figure 39 - PFE3000-12-069RA with Key-in screw (Option code S366)
1
2
P1
Unit:
FCI Connectors P/N 51939-768LF
Counterpart: FCI Connectors P/N 51915-401LF
For Main Output Pins, see section 15
P2
3
P3
P4
D
C
B
P5 A
4
1 2 3 4 5
Note: A1 and A2 are Trailing Pin (short pins)
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PFE3000-12-069RA
24
PIN
NAME
DESCRIPTION
3,4
V1
+12 VDC main output
1,2
PGND
+12 VDC main output ground
P1
LIVE
AC Live Pin
P2
N.C
No metal pin connection
P3
NEUTRAL
AC Neutral Pin
P4
N.C.
No metal pin connection
P5
P.E.
Protective Earth Pin
A1
PSKILL
Power supply kill (trailing pin): active-high
B1
PWOK_L
Power OK signal output: active-low
C1
INOK_L
Input OK signal: active-low
D1
PSON_L
Power supply on input: active-low
A2
PRESENT_L
Power supply present (trailing pin): active-low
B2
SGND
Signal ground* (return)
C2
SGND
Signal ground* (return)
D2
SGND
Signal ground* (return)
A3
SCL
I2C clock signal line
B3
SDA
I2C data signal line
C3
SMB_ALERT_L
SMB Alert signal output: active-low
D3
ISHARE
V1 Current share bus
A4
EEPROM_WP
EEPROM write protect
B4
RESERVED
Reserved
C4
V1_SENSE_R
Main output negative sense
D4
V1_SENSE
Main output positive sense
A5
VSB
Standby positive output
B5
VSB
Standby positive output
C5
VSB_GND
Standby Ground*
D5
VSB_GND
Standby Ground*
Output
Input Pins
Control Pins
* These pins should be connected to PGND on the system. See Section 8 for pull up resistor settings of signal pins.
All signal pins are referred to SGND
Table 9 – Pin assignment
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PFE3000-12-069RA
25
The recommended pin configuration below is based on company’s own Shelf design and provided here as reference.
Customer pin lengths within the range indicated is acceptable.
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PFE3000-12-069RA
26
ITEM
DESCRIPTION
ORDERING PN
SOURCE
tech.support@psbel.com
PFE3000-12-069RA
REV
AA
DESCRIPTION
Initial Release of Datasheet.
▪
AB
AC
▪
▪
▪
▪
▪
AD
▪
▪
▪
▪
AE
▪
AE
▪
▪
▪
AF
▪
▪
▪
▪
AF1
AG
27
▪
▪
▪
▪
Handle position and size has changed to a diagonal format to
allow better handling/grip.
+12VSB turn-on delay is changed from 2 seconds to 3 seconds.
Main output will only turn on (if enabled by PSKILL and PSON)
once +12VSB is in regulation.
Datasheet format was changed to Bel Power Solution.
Added option code model in ordering information.
S101 denotes Screw for Key-in feature is added.
+12VSB parameter change in output ripple voltage, droop, and
current read back accuracy.
PSU Fans is supplied only from Internal Auxiliary.
Option code is changed from S101 to S366.
Added Revision History.
PSU Revision on product label was incremented due to internal
documentation.
Clarification on Dynamic Load Regulation, Mechanical Drawing
and Key-in Screw accessory for option code S366.
Passed EAC certification and added EAC logo on product label.
PSKILL and SMB_ALERT_L pin active state description on
section 14 was corrected but no functional change.
PSU firmware was updated to support calibration of MFR Model
suffix.
Passed BIS certification and added BIS logo on product label.
Transfer 80plus platinum logo on product label.
Mechanical update on section 13 for PSU height tolerance.
Mechanical update on section 13.
PSU height tolerance on hinge side was adjusted to 42 +0.3/0.5mm.
Removed “80plus optional coloured label” on PSU drawing.
PSU firmware was updated to improve I2C during hot plug.
Passed KCC certification and added KCC logo on product label.
A disclaimer added to the first page
Figure 28. I2C / SMBus Timing updated
PSU
PRODUCT
VERSION
DATE
AUTHOR
V001
V004
V007
11-27-2013
GS
V008
10-22-2014
GS
V009
12-22-2014
GS
V010
09-09-2015
GS
V011
10-28-2016
GS
V204
04-06-2017
GS
V205
05-09-2017
GS
V205
08-14-2017
GS
V206
11-28-2017
GS
V207
01-09-2018
GS
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
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