BL24C128A-NTRC

BL24C128A 128K bits (16,384×8) Features ⚫ ⚫ Compatible with all I2C bidirectional data transfer protocol – 1 MHz – 400 kHz – 100 kHz Memory array: – 128 Kbit (16 Kbytes) of EEPROM – Page size: 64 bytes – Additional Write lockable page Single supply voltage and high speed: – 1 MHz Write: – Byte Write within 3 ms – Page Write within 3 ms Operating Ambient Temperature: – From -40 °C up to +85 °C ⚫ ⚫ ⚫ ⚫ High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Internally Organized: – BL24C128A, 16,384 X 8 (128K bits) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol Write Protect Pin for Hardware Data Protection Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) 8-lead PDIP/SOP/TSSOP/UDFN/TSOT23-5 packages ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Description The BL24C128A provides 131,072 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 16,384 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The BL24C128A is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP，TSOT23-5 packages and is accessed via a two-wire serial interface. In addition, the BL24C128A is available in 1.7V (1.7V to 5.5V) version. Pin Configuration ８-lead PDIP A0 １ 8 A1 ２ A2 ３ GND ４ ８-lead SOP ８-lead TSSOP VCC A0 １ 8 7 WP A1 ２ 6 SCL A2 ３ 5 SDA GND ４ ８-pad DFN 5-lead TSOT23-5 WP VCC VCC A0 1 8 VCC 7 WP A1 2 7 WP 6 SCL A2 3 6 SCL 5 SDA GND 4 5 SDA VCC A0 １ 8 7 WP A1 ２ 6 SCL A2 ３ 5 SDA GND ４ ５ １ ２ ３ SCL GND SDA BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn ４ 1-19 BL24C128A 128K bits (16,384×8) Pin Descriptions Pin Name Type Functions A0-A2 I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write Protect GND P Ground Vcc P Power Supply Table 1 Block Diagram Vcc GND WP SCL START STOP LOGIC SDA EN SERIAL CONTROL LOGIC HIGH VOLTAGE PUMP/TIMING LOAD DATA RECOVERY CCMP DEVICE ADDRESS COMPARATOR LOAD INC DATA WORD ADRESS COUNTER A1 A2 Y DECODER DIN X DECODER A0 EEPROM SERIAL MUX DOUT/ACKNOWLEDGE DOUT Figure 1 BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 2-19 BL24C128A 128K bits (16,384×8) DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the BL24C128A. Eight 128K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The BL24C128A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2. WP Pin Status BL24C128A At VCC Full(128K)Array At GND Normal Read/Write Operations Table 2 Functional Description 1. Memory Organization BL24C128A, 128K SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 128K requires a 14-bit data word address for random word addressing. 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. SDA SCL DATA STABLE DATA CHANGE DATA STABLE Figure 2. Data Validity START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 3-19 BL24C128A 128K bits (16,384×8) SDA SCL START STOP Figure 3. Start and Stop Definition ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE Figure 4. Output Acknowledge STANDBY MODE: The BL24C128A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 4-19 BL24C128A 128K bits (16,384×8) 3. Device Addressing The 128K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5) MSB 1 LSB 0 1 0 A2 A1 A0 R/W Figure 5: Device Address The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The 128K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. DATA SECURITY: The BL24C128A has a hardware data protection scheme that allows the user protect the entire memory when the WP pin is at VCC. to write 4. Write Operations BYTE WRITE: A write operation requires two 8-bit data words address following the device address word and acknowledgment. Upon receipt of every 8-bit address, the EEPROM will respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6). S T A R T DEVICE ADDRESS W R I T E FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA SDA LINE M S B L R A S / C BWK L A S C B K L A S C B K L A S C B K Note.1*=DON'T’T CARE bits Figure 6: Byte Write BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 5-19 BL24C128A 128K bits (16,384×8) PAGE WRITE: The 128K EEPROM is capable of a 64-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7). S T A R T DEVICE ADDRESS W R I T E FIRST WORD ADDRESS SECOND WORD ADDRESS DATA(n) DATA(n+1) S T O P DATA(n+1) SDA LINE M S B L R A S / C BWK L A S C B K L A S C B K A C K A C K A C K Note.1*=DON'T CARE bits Figure 6: Page Write The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. WRITE IDENTIFICATION PAGE: The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:  Device type identifier = 1011b  MSB address bits B15/B6 are don't care except for address bit B10 which must be "0". LSB address bits B5/B0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 6-19 BL24C128A 128K bits (16,384×8) 5. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8). S T A R T DEVICE ADDRESS R E A D S T O P DATA SDA LINE M S B L R A S / C BWK NO ACK Figure 8: Current Address Read RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9) S T A R T DEVICE ADDRESS W R I T E S T A R T 1st,2nd WORD ADDRESS DEVICE ADDRESS R E A D DATA(n) S T O P SDA LINE M S B L R A S / C BWK L A S C B K A C K NO ACK DUMMY WRITE Note.1*=DON'T CARE bits Figure 9: Random Read BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 7-19 BL24C128A 128K bits (16,384×8) SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10). DEVICE ADDRESS R E A D DATA(n) DATA(n+1) DATA(n+2) DATA(n+x) S T O P SDA LINE R A / C WK A C K A C K A C K NO ACK Figure 10: Sequential Read READ IDENTIFICATION PAGE: The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing a Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B15/B6 are don't care, the LSB address bits B5/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes) LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: Device type identifier = 1011b Address bit B10 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 8-19 BL24C128A 128K bits (16,384×8) Electrical Characteristics Absolute Maximum Stress Ratings： ⚫ ⚫ ⚫ ⚫ ⚫ DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Input / Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to VCC+0.3V Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40℃ to +85℃ Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65℃ to +150℃ Electrostatic pulse (Human Body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8000V Comments： Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V (unless otherwise noted) Parameter Symbol Min Typ Max Unit Condition Supply Voltage VCC1 1.7 - 5.5 V @400KHz Supply Voltage VCC2 2.5 - 5.5 V @1MHz Supply Current VCC=5.0V ICC1 - 0.14 0.3 mA READ at 400KHZ Supply Current VCC=5.0V ICC2 - 0.28 0.5 mA WRITE at 400KHZ Supply Current VCC=5.0V ISB1 - 0.03 0.5 μA VIN=VCC or VSS Input Leakage Current IL1 - 0.10 1.0 μA VIN=VCC or VSS Output Leakage Current ILO - 0.05 1.0 μA VOUT=VCC or VSS Input Low Level VIL1 -0.3 - VCC×0.3 V VCC=1.7V to 5.5V Input High Level VIH1 VCC×0.7 - VCC+0.3 V VCC=1.7V to 5.5V Output Low Level VCC=1.7V VOL1 - - 0.2 V IOL=0.15mA Output Low Level VCC=5.0V VOL2 - - 0.4 V IOL=3.0mA Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Min Typ Max Unit Condition Input/Output Capacitance(SDA) CI/O - - 8 pF VIO=0V Input Capacitance(A0,A1,A2,SCL) CIN - - 6 pF VIN=0V BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 9-19 BL24C128A 128K bits (16,384×8) AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Parameter Symbol 1.7V≤VCC﹤2.5V 2.5V≤VCC﹤5.5V Min Typ Max Min Typ Max Units Clock Frequency,SCL fSCL - - 400 - - 1000 kHz Clock Pulse Width Low tLOW 1.3 - - 0.5 - - μs Clock Pulse Width High tHIGH 0.6 - - 0.26 - - μs Noise Suppression Time tI - - 50 - - 50 ns Clock Low to Data Out Valid tAA - - 0.9 - - 0.45 μs Time the bus must be free before a new transmission can start tBUF 1.3 - - 0.5 - - μs Start Hold Time tHD:STA 0.6 - - 0.25 - - μs Start Setup Time tSU:STA 0.6 - - 0.25 - - μs Data In Hold Time tHD:DAT 0 - - 0 - - μs Data in Setup Time tSU:DAT 100 - - 100 - - ns Input Rise Time(1) tR - - 0.3 - - 0.12 μs Input Fall Time(1) tF - - 0.3 - - 0.12 μs Stop Setup Time tSu:STO 0.6 - - 0.25 - - μs Data Out Hold Time tDH 50 - - 50 - - ns Write Cycle Time twR - 1.9 3 - 1.9 3 ms Endurance 1M - - 1M - - Write Cycle 5.0V,25℃,Byte Mode(1) Note: 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.7V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 10-19 BL24C128A 128K bits (16,384×8) Bus Timing tF tHIGH tR tLOW tLOW SCL tSU.DAT tHD.DAT tHD.STA tSU.STA tSU.STO SDA_IN tAA t BUF tDH SDA_OUT Figure 11: SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL ACK SDA Word n tWR(1) STOP CONDITION START CONDITION Figure 12: SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 11-19 BL24C128A 128K bits (16,384×8) Package Information PDIP Outline Dimensions E1 c eA eB COMMON DIMENSIONS (Unit of Measure=mm) D e A2 A b2 L SYMBOL A A2 b b2 c D E1 e eA eB L MIN 3.60 3.20 0.44 0.24 9.05 6.15 7.62 NOM 3.80 3.30 1.52BSC 9.25 6.35 2.54BSC 7.62BSC 3.00BSC MAX 4.00 3.40 0.53 0.32 9.45 6.55 9.30 BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 12-19 BL24C128A 128K bits (16,384×8) SOP C E E1 L Φ COMMON DIMENSIONS (Unit of Measure=mm) B A A1 e D SYMBOL A A1 B C D E1 E e L Φ MIN 1.35 0.10 0.39 0.21 4.70 3.70 5.80 0.50 0" NOM 4.90 3.90 6.00 1.27BSC - MAX 1.75 0.23 0.48 0.26 5.10 4.10 6.20 0.80 8" BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 13-19 BL24C128A 128K bits (16,384×8) TSSOP E1 E L1 End View Top View A b e D Side View A1 L COMMON DIMENSIONS Unit of Measure=mm SYMBOL D E E1 A A1 b e L L1 MIN 2.90 6.20 4.30 0.05 0.21 0.45 NOM 3.00 6.40 4.40 0.65BSC 0.60 1.00REF MAX 3.10 6.60 4.50 1.20 0.15 0.30 0.75 BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 14-19 BL24C128A 128K bits (16,384×8) UDFN D2 D L PIN 1 DOT BY MARKING E E2 PIN #1 IDENTIFICATION CHAMFER TOP VIEW A b e BOTTOM VIEW A3 A1 SIDE VIEW PKG REF A A1 A3 D E b L D2 E2 e COMMON DIMENSION(MM) UT:ULTRA THIN MIN NOM MAX >0.50 0.55 0.60 0.00 0.05 0.15REF 1.95 2.00 2.05 2.95 3.00 3.05 0.20 0.25 0.30 0.20 0.30 0.40 1.25 1.40 1.50 1.15 1.30 1.40 0.50BSC BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 15-19 BL24C128A 128K bits (16,384×8) TSOT23-5 D e1 L2 R1 Θ1(4X) R L(L1) Θ2(4X) E E1 Θ e b Pin 1 0.20 B B SIDE VIEW M TOP VIEW COMMON DIMENSIONS (UNITS OF MEASURE = MILLIMETER) A3 A A2 0.10 SIDE VIEW A1 SYMBOL A A1 A2 A3 c c1 D E E1 e e1 L L1 L2 R R1 Θ Θ1 Θ2 MIN 0.00 0.65 0.35 0.14 0.14 2.85 2.65 1.60 0.90 1.80 0.30 0° 3° 10° NOM 0.75 0.40 0.15 2.95 2.80 1.65 0.95 1.90 0.45 0.575REF 0.258BSC 5° 12° BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn MAX 0.90 0.15 0.85 0.45 0.20 0.16 3.05 2.95 1.70 1.00 2.00 0.60 0.25 0.25 8° 7° 14° 16-19 BL24C128A 128K bits (16,384×8) Marking Diagram PDIP BL24C128A YYWW#ZZ SSSSSP YY: year WW :week ZZ: assembly house SSSSS : Lot ID SOP BL24C128A SSSSSP SSSSS : Lot ID TSSOP BL24C128A SSSSS SSSSS : Lot ID UDFN BL28 YYWW YY: year WW :week TSOT23-5 24C128A SSSSSP SSSSS : Lot ID BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 17-19 BL24C128A 128K bits (16,384×8) Ordering Information BL 24C 128 A-PA R C Feature S: Standard (default, Pb Free RoHS Std.) C: Green (Halogen Free) Packing type R: Tape and Reel Package Type PA: SOP-8L SF: TSSOP-8L DA: PDIP-8L NT: UDFN-8L TC: SOT23-5L RR: TSOT23-5L Version A：A Version Density 02:2k bit 04:4k bit 08:8k bit 16:16k bit 32:32k bit 64:64k bit 128:128k bit 256:256k bit 512:512k bit M1:1M bit M2:2M bit Product Family 24:IIC Interface EEPROM Device Package Shipping (Qty/Packing) BL24C128A SOP8 2500/Tape &Reel BL24C128A TSSOP8L 3000/Tape &Reel BL24C128A UDFN 3000/Tape &Reel BL24C128A TSOT23-5 3000/Tape &Reel BL24C128A 128K bits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 18-19 BL24C128A 128K bits (16,384×8) Revision history Version 1.7 BL24C128A Add Write lockable page in Features Random and sequential Read modes Enhanced ESD/ Latch-up protection UDFN packages Add Table First/Second address Write Identification Page/ Lock Identification Page Read Identification Page Modify DC/AC Electrical Characteristics Version 1.8 BL24C128A Modify the format Version 1.91 BL24C128A Modify AC/DC Electrical Characteristics Version 1.92 BL24C128A Modify Package Information Version 1.93 BL24C128A Modify Package Information Version 1.94 BL24C128A Modify Package Information Version 1.95 BL24C128A Modify AC Electrical Characteristics Version 1.96 BL24C128A Add ID Page Information Version 1.97 BL24C128A 8/17/2018 Add TSOT23-5 Package information Modify Text and structure of documents BL24C128A 128K bits (16,384×8) Belling Proprietary Information. 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