BL34C04A-NTRC

BL34C04A 4K bits (512×8) Features ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ 512-byte Serial Presence Detect EEPROM compatible with JEDEC EE1004 specification Compatible with SMBus serial interface: – up to 1 MHz transfer rate Memory array: – 4 Kbits organized as two banks of 256 bytes each – Each page is composed of two 128-byte blocks Software data protection for each 128-byte block Hardware write protection Write: – Byte Write within 3 ms – ⚫ ⚫ ⚫ ⚫ 16 bytes Page Write within 3 ms Schmitt Trigger, Filtered Inputs for Noise Suppression Single supply voltage: – 1.7 V to 3.6 V High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Enhanced ESD/latch-up protection – HBM 6000V Description The BL34C04A is a 512-byte EEPROM device designed to operate the SMBus bus in the 1.7 V - 3.6 V voltage range, with a maximum of 1 MHz . ⚫ The BL34C04A includes a 4-Kbit serial EEPROM organized as two banks of 256 bytes each, or 512 bytes of total memory. Each bank is composed of two 128-byte blocks. The device is able to selectively lock the data in any or all of the four 128-byte blocks. Designed specifically for use in DRAM DIMMs (Dual Inline Memory Modules) with Serial Presence Detect, all the information concerning the DRAM module configuration (such as its access speed, its size, its ⚫ organization) can be kept write-protected in one or more memory blocks. ⚫ Individually locking a 128-byte block may be accomplished using a software write protection mechanism in conjunction with a high input voltage VHV on input A0. By sending the device a specific SMBus sequence, each block may be protected from writes until the write protection is electrically reversed using a separate SMBus sequence which also requires VHV on input A0. The write protection for all four blocks is cleared simultaneously Pin Configuration ８-pad DFN A0 1 8 A1 2 A2 3 GND 4 BL34C04A-NT VCC A0 1 8 VCC 7 WP A1 2 7 NC 6 SCL A2 3 6 SCL 5 SDA GND 4 5 SDA BL34C04ANP-NT BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 1-18 BL34C04A 4K bits (512×8) Pin Descriptions Pin Name Type Functions A0-A2 I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write Protect GND P Ground VCC P Power Supply Table 1 Block Diagram Vcc GND WP SCL START STOP LOGIC SDA EN SERIAL CONTROL LOGIC HIGH VOLTAGE PUMP/TIMING LOAD DATA RECOVERY CCMP DEVICE ADDRESS COMPARATOR LOAD INC DATA WORD ADRESS COUNTER A1 A2 BLOCK 1 X DECODER A0 BLOCK 2 BLOCK 3 BLOCK 4 Y DECODER DIN E E P R O M SERIAL MUX DOUT/ACKNOWLEDGE DOUT Figure 1 DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the BL34C04A. Eight 4K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. If SCL is driven low for tTIMEOUT (see Table 8) or longer, the BL34C04A is set back in Standby mode, ready to receive a new START condition. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 2-18 BL34C04A 4K bits (512×8) WRITE PROTECT (WP): The BL34C04A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled. Functional Description 1. Memory addressing To start a communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Type Identifier Code (DTIC) consists of a 4-bit device type identifier, and a 3-bit slave address (A2, A1, A0). To address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. Device type identifier Select address R_W_n Abbr Read SA0 pin b7 b6 b5 b4 b3 b2 b1 1 0 1 0 LSA2 LSA1 LSA0 RSPD b0 1 0 or 1 Write WSPD Set Write Protection, block 0 SWP0 0 0 1 0 VHV Set Write Protection, block 1 SWP1 1 0 0 0 VHV Set Write Protection, block 2 SWP2 1 0 1 0 VHV Set Write Protection, block 3 SWP3 0 0 0 0 VHV Clear All Write Protection CWP 0 1 1 0 VHV Read Protection Status, block 0 RPS0 0 0 1 1 0,1 or VHV Read Protection Status, block 1 RPS1 1 0 0 1 0,1 or VHV Read Protection Status, block 2 RPS2 1 0 1 1 0,1 or VHV Read Protection Status, block 3 RPS3 0 0 0 1 0,1 or VHV Set Page Address to 0 SPA0 1 1 0 0 0,1 or VHV Set Page Address to 1 SPA1 1 1 1 0 0,1 or VHV Read Page Address RPA 1 1 0 1 0,1 or VHV Reserved 0 0 1 1 0 - All other encodings Table 2 Up to eight memory devices can be connected on a single serial bus. Each one is given a unique 3-bit code on the slave address (A2, A1, A0) inputs. When the device select code is received, the device only responds if the slave address is the same as the value on the slave address (A2, A1, A0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 3-18 BL34C04A 4K bits (512×8) 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. SDA SCL DATA STABLE DATA CHANGE DATA STABLE Figure 2. Data Validity START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). SDA SCL START STOP Figure 3. Start and Stop Definition ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 4-18 BL34C04A 4K bits (512×8) SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE Figure 4. Output Acknowledge STANDBY MODE: The BL34C04A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. DATA SECURITY: The BL34C04A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 5-18 BL34C04A 4K bits (512×8) 3. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete ( Figure 5). S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE M S B L R A S / C BWK L A S C B K L A S C B K Figure 5. Byte Write If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. PAGE WRITE: The Page write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory. A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6). S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS DATA(1) DATA(n) DATA(n+1) S T O P DATA(n+1) SDA LINE M S B L R A S / C BWK L A S C B K L A S C B K A C K A C K A C K Figure 6. Page Write The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 16 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 6-18 BL34C04A 4K bits (512×8) address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. 4. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7). S T A R T DEVICE ADDRESS R E A D S T O P DATA SDA LINE M S B L R A S / C BWK NO ACK Figure 7. Current Address Read RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8) S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS S T A R T DEVICE ADDRESS R E A D DATA(n) S T O P SDA LINE M S B L R A S / C BWK L A S C B K A C K NO ACK DUMMY WRITE Figure 8. Random Read BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 7-18 BL34C04A 4K bits (512×8) SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9). DEVICE ADDRESS R E A D DATA(n) DATA(n+1) DATA(n+2) DATA(n+x) S T O P SDA LINE R A / C WK A C K A C K A C K NO ACK Figure 9. Sequential Read BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 8-18 BL34C04A 4K bits (512×8) 5. Setting the write protection There are four independent memory blocks, and each block may be independently protected. The memory blocks are: The device has three software commands for setting, clearing, or interrogating the write-protection status. ⚫ Block 0 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 0 ⚫ Block 1 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 0 ⚫ Block 2 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 1 ⚫ Block 3 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 1 The level of write protection (set or cleared), that has been defined using these instructions, remains defined even after a power cycle. ⚫ SWPn: Set Write Protection for block n ⚫ CWP: Clear Write Protection for all blocks ⚫ RPSn: Read Protection status for block n The DTICs of the SWP, CWP and RPS instructions are defined in Table 2. 6. Set and clear the write protection (SWPn and CWP) If the software write protection has been set with the SWPn instruction, it may be cleared again with a CWP instruction. SWPn acts on a single block as specified in the SWPn command, but CWP clears the write protection for all blocks. When decoded, SWPn and CWPn trigger a write cycle lasting tW (see Table 8). The DTICs of the SWP and CWP instructions are defined in Table 2. 7. Read the protection status (RPSn) The serial bus master issues an RPSn command specifying which block to report upon. If the software write protection has not been set, the device replies to the data byte with an Ack. If it has been set, the device replies to the data byte with a NoAck. The DTIC of the RPSn instruction is defined in Table 2. 8. Set the page address (SPAn) The SPAn command selects the lower 256 bytes (SPA0) or upper 256 bytes (SPA1). After a cold or warm poweron reset, the page address is always 0, selecting the lower 256 bytes. The DTIC of the SPAn instruction is defined in Table 2. 9. Read the page address (RPA) The RPA command determines if the currently selected page is 0 (device returns Ack) or 1 (device returns NoAck). The DTIC of the RPA instruction is defined in Table 2. Use within a DDR4 DRAM module In the application, the BL34C04A is soldered directly in the printed circuit module. The three slave address inputs (A2, A1, A0) must be connected to GND or VCC directly (that is without using a serial resistor) through the DRAM module connector (see Table 3). The pull-up resistor on SDA is connected on the SMBus of the motherboard. The Write Protect (WP) of the BL34C04A can be left unconnected. However, connecting it to GND is recommended, to maintain full read and write access. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 9-18 BL34C04A 4K bits (512×8) DIMM position A2 A1 A0 0 VSS VSS VSS 1 VSS VSS VCC 2 VSS VCC VSS 3 VSS VCC VCC 4 VCC VSS VSS 5 VCC VSS VCC 6 VCC VCC VSS 7 VCC VCC VCC Table 3 1. Programming the BL34C04A The situations in which the BL34C04A is programmed can be considered under two headings: ⚫ when the DDR4 DRAM is isolated (not inserted on the PCB motherboard) ⚫ when the DDR4 DRAM is inserted on the PCB motherboard Isolated DRAM module: With a specific programming equipment, it is possible to define the BL34C04A content, using Byte and Page write instructions, and the write-protection SWP(n) and CWP instructions. To issue the SWP(n) and CWP instructions, the signal applied on SA0 must be driven to VHV during the whole instruction. DRAM module inserted in the application motherboard: Table 4 and Table 5 show how the Ack bits can be used to identify the write-protection status. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 10-18 BL34C04A 4K bits (512×8) Status Instruction Ack SWPn Ack Data byte Ack Write cycle (tW) NoAck Not significant NoAck Not significant NoAck No CWP Ack Not significant Ack Not significant Ack Yes Page or byte write in protected block Ack Address Ack Data NoAck No SWPn or CWP Ack Not significant Ack Not significant Ack Yes Page or byte write Ack Address Ack Data Ack Yes Protected Not Protected Address Table 4 SWPn Status Instruction Ack Address Ack Data byte Ack Set RPSn NoAck Not significant NoAck Not significant NoAck Not set RPSn Ack Not significant NoAck Not significant NoAck Table 5 DRAM module slot number 7 A2 A1 A0 SCL SDA A0 SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA Rpull-up VCC DRAM module slot number 6 A2 A1 VCC GND DRAM module slot number 5 A2 A1 A0 VCC GND VCC A1 A0 DRAM module slot number 4 A2 VCC GND DRAM module slot number 3 A2 A1 GND A0 VCC DRAM module slot number 2 A2 A1 A0 GND VCC GND A1 A0 DRAM module slot number 1 A2 GND VCC DRAM module slot number 0 A2 A1 A0 GND SCL SDA Line Line From the motherboard I2C master control Figure 10 BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 11-18 BL34C04A 4K bits (512×8) Electrical Characteristics Absolute Maximum Stress Ratings： ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Input / Output Voltage . . . . . . . . . . . . . GND-0.3V to VCC+0.3V Voltage on Pin A0. . . . . . . . . . . . . . . . . . . . .. . . . -0.5V to +10V Operating Ambient Temperature . . . . . . . . . . . -40℃ to +130℃ Storage Temperature . . . . . . . . . . . . . . . . . . . . .-65℃ to +150℃ Electrostatic pulse (Human Body model) . . . . . . . . . . . . . 6000V Comments: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 12-18 BL34C04A 4K bits (512×8) DC Electrical Characteristics Applicable over recommended operating range from: TA = 0℃ to +95℃, VCC = +1.7V to +5.5V (unless otherwise noted) Table 7 DC characteristics Symbol Parameter Test condition (in addition to those in Table 8) Min Max Unit ILI Input leakage current (SCL,SDA, A0, A1, A2) VIN = GND or VCC - ±2 μA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: GND or VCC - ±2 μA ICC Supply current (read) fc = 400 kHz or 1 MHz - 1 mA ICC0 Supply current (write) During tW, VIN = GND or VCC - 1 (1) mA Device not selected (2), VIN = GND or VCC, VCC ≥ 2.2 V - 2 μA Device not selected (2), VIN = GND or VCC, VCC < 2.2 V - 1 μA ICC1 Standby supply current VIL Input low voltage (SCL, SDA, WP) - -0.45 0.3 x VCC V VIH Input high voltage (SCL, SDA, WP) - 0.7 x VCC VCC+1 V V VHV A0 high voltage detect VCC < 2.2 V 7 10 V VCC ≥ 2.2 V VCC+4.8 V 10 V VOL Output low voltage IOL = 0.15 mA - 0.2 V IOL = 3 mA - 0.4 V VPOR Power on reset threshold - - VPDR Power down reset threshold - 0.7 (2) 1.4 - (1) V V 1. Measured during characterization, not tested in production. 2. The device is not selected after a power-up, after a read command (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command). BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 13-18 BL34C04A 4K bits (512×8) Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Min Typ Max Unit Condition Input/Output Capacitance(SDA) CI/O - - 8 pF VIO=0V Input Capacitance(A0,A1,A2,SCL) CIN - - 6 pF VIN=0V AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Table 8 AC characteristics VCC ≥ 2.2 V VCC < 2.2 V Symbol Parameter 100 kHz 400 kHz 1000 kHz Min. Max. Min. Max. Min. Max. Unit fSCL fC Clock frequency 10 100 10 400 10 1000 kHz tHIGH tCHCL Clock pulse width high time 4000 - 600 - 260 - ns tLOW(1) tCLCH Clock pulse width low time 4700 - 1300 - 500 - ns Detect clock low timeout 25 35 25 35 25 35 ms tTIMEOUT (2) tR(3) tXH1XH2 SDA rise time - 1000 20 300 - 120 ns tF(3) tQL1QL2 SDA(out) fall time - 300 20 300 - 120 ns tSU:DAT tDXCH Data in setup time 250 - 100 - 50 - ns tHD:DI tCLDX Data in hold time 0 - 0 - 0 - ns tHD:DAT tCLQX Data out hold time 200 3450 200 900 0 350 ns tSU:STA(4) tCHDL Start condition setup time 4700 - 600 - 260 - ns tHD:STA tDLCL Stop condition hold time 4000 - 600 - 260 - ns tSU:STO tCHDH Stop condition setup time 4000 - 600 - 260 - ns tBUF tDHDL Time between Stop Condition and next Start Condition 4700 - 1300 - 500 - ns tW Write time - 3 - 3 - 3 ms tPOFF (3) Time ensuring a Reset when VCC drops below VPDR(min) 100 - 100 - 100 - μs tINIT (3) Time from VCC(min) to the first command 0 - 0 - 0 - μs 1. Initiate clock stretching, which is an optional SMBus bus feature. 2. A timeout condition can only be ensured if SCL is driven low for tTIMEOUT(Max) or longer; then the BL34C04A is set in Standby mode and is ready to receive a new START condition. If SCL is driven low for less than tTIMEOUT(Min), the BL34C04A internal state remains unchanged. 3. Measured during characterization, not tested in production. 4. To avoid spurious START and STOP conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 14-18 BL34C04A 4K bits (512×8) Bus Timing tHIGH tF tR tLOW tLOW SCL tSU.DAT tHD.DAT tHD.STA tSU.STA tSU.STO SDA_IN tAA t BUF tDH SDA_OUT Figure 11. SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL ACK SDA Word n tWR(1) STOP CONDITION START CONDITION Figure 12. SCL: Serial Clock, SDA: Serial Data I/O Notes: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 15-18 BL34C04A 4K bits (512×8) Package Information UDFN D2 D L PIN 1 DOT BY MARKING E E2 PIN #1 IDENTIFICATION CHAMFER TOP VIEW A b e BOTTOM VIEW A3 A1 SIDE VIEW PKG REF A A1 A3 D E b L D2 E2 e COMMON DIMENSION(MM) UT:ULTRA THIN MIN NOM MAX 0.50 0.55 0.60 0.00 0.05 0.15REF 1.95 2.00 2.05 2.95 3.00 3.05 0.20 0.25 0.30 0.20 0.30 0.40 1.25 1.40 1.50 1.15 1.30 1.40 0.50BSC Marking Diagram UDFN BL34C04A BL34C04ANP BLE4 YYWW BLE4 YYWW YY: year WW :week BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 16-18 BL34C04A 4K bits (512×8) Ordering Information BL 34C 04 A NP-NT R C Feature S: Standard (default, Pb Free RoHS Std.) C: Green (Halogen Free) Packing type R: Tape and Reel Package Type NT: UDFN-8L Blank：Normal Version NP：Without WP pin Version A：A Version Density 04:4k bit Product Family 34:Serial Presence Detect (SPD) EEPROM BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 17-18 BL34C04A 4K bits (512×8) Revision history Version 1.00 BL34C04A Initial version Version 1.01 BL34C04A Modify feature information Modify Absolute Maximum Stress Ratings Version 1.02 BL34C04A Add Marking Diagram Modify DC/AC Electrical Characteristics Version 1.03 BL34C04A Modify recommended operating temperature to 0℃ to +95℃. Modify DC/AC Electrical Characteristics Version 1.04 BL34C04A 9/7/2018 Add BL34C04ANP information BL34C04A 4K bits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2017 Belling All Rights Reserved www.belling.com.cn 18-18