BL9193-ADBAPRN

BL9193 300mA Ultra tra-low Noise, Ultra tra-Fast CMOS LDO LDO Regul Regula ulator Hand-Held Instruments PCMCIA Cards MP3/MP4/MP5 Players Portable Information Appliances FEATURES Ultra-low Noise for RF Application Ultra-Fast Response in Line/Load Transient Quick Start-Up (Typically 50µS) 1.2V, IOUT=0mA IOUT=200mA, 130 VOUT=2.8V Dropout Voltage VDROP IOUT=300mA, 210 VOUT=2.8V VIN=3.6V to 5.5V (Note 7) 0.05 ∆VLINE Line Regulation IOUT=1mA (Note 8) ∆VLOAD 1mA 25mΩ on the BL9193 output ensures stability. The BL9193 still works well with output capacitor of other types due to the wide stable ESR range. Output capacitor of PPMIC BU BL9193 Rev 2.2 1/2011 larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the BL9193 and returned to a clean analog ground. Bypass Capacitor and Low Noise Connecting a 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor connection between the BP pin and GND pin be direct and PCB traces should be as short as possible. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. Enable Function The BL9193 features an LDO regulator enable/disable function. To assure the LDO regulator will switch on; the EN turn on control level must be greater than 1.2 volts. The LDO regulator will go into the shutdown mode when the voltage on the EN pin falls below 0.4 volts. For to protect the www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2011 Belling All Rights Reserved 7 BL9193 300mA Ultra tra-low Noise, Ultra tra-Fast CMOS LDO LDO Regul Regula ulator system, the BL9193 have a quick discharge function. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. Programming the BL9193 Adjustable LDO regulator The output voltage of the BL9193 adjustable regulator is programmed using an external resistor divider as show in Figure as below. The output voltage is calculated using equation as below:  R1  VOUT = VREF × 1+  R2    Where: VREF=1.23V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50uA divider current. Lower value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and thus erroneously decrease/increases VOUT. The recommended design procedure is to choose R2=30.1kΩ to set the divider current at 50uA, C1=22pF for stability, and then calculate using Equation as below: VOUT  R1 =  VREF −1 × R2 In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. The suggested value of this capacitor for several resistor ratios is shown in the table below. OUTPUT VOLTAGE PROGRAMMING GUIDE BL9193 Rev 2.4 3/2017 OUTPUT VOLTAGTE 1.8V 2.5V 3.3V 3.6V R1 R2 C1 13.9 kΩ 31.6 kΩ 51 kΩ 59 kΩ 30.1 kΩ 30.1 kΩ 30.1 kΩ 30.1 kΩ 22pF 22pF 22pF 22pF BL9193 Adjustable LDO regulator Programming VIN 1 VIN VOUT 5 VOUT 1uF 1uF 2 R1 GND C1 BL9193 -ADJ 3 EN FB 4 R2 Thermal Considerations Thermal protection limits power dissipation in BL9193. When the operation junction temperature exceeds 165°C, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turns on again after the junction temperature cools by 30°C. For continue operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: PD = (VIN−VOUT) ×IOUT + VIN×IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula： PD(MAX) = ( TJ(MAX) − TA ) /θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2011 Belling All Rights Reserved 8 BL9193 300mA Ultra tra-low Noise, Ultra tra-Fast CMOS LDO LDO Regul Regula ulator ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of BL9193, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance (θJA is layout dependent) for SOT-23-5 package is 250°C/W, SC-705 package is 333°C/W, on standard JEDEC 51-3 thermal test board. The maximum power dissipation at TA= 25°C can be calculated by following formula: PD(MAX) = (125°C−25°C)/333 = 300mW (SC-70-5) PD(MAX) = (125°C−25°C)/250 = 400mW (SOT-23-5) The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. It is also useful to calculate the junction of temperature of the BL9193 under a set of TJ=TA+PD×θJA=40°C+0.15W×250°C/W =40°C+37.5°C=77.5°C