TISP61089ASDR-S

TISP61089D, TISP61089SD, TISP61089AD, TISP61089ASD DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS TISP61089 Gated Protector Series Overvoltage Protection for Negative Rail SLICs 2/10 Overshoot Voltage Specified Dual Voltage-Tracking Protectors - ‘61089 for Battery Voltages to ....... -75 V - ‘61089A for Battery Voltages to... -100 V - Low Gate Triggering Current...... < 5 mA - High Holding Current .............. > 150 mA Element IPP = 100 A, 2/10 V Diode SCR 8 12 Additional Information Click these links for more information: PRODUCT TECHNICAL INVENTORY SAMPLES SELECTOR LIBRARY Package Options - Surface Mount 8-pin Small-Outline Line Feed-Thru Connection (D) Shunt Version Connection (SD) Rated for GR-1089-CORE and K.44 Impulses CONTACT Agency Recognition Description Impulse Wave Shape Voltage Current IPPSM A 2/10 10/700 10/1000 2/10 5/310 10/1000 120 40 30 UL File Number: E215609 ............UL Recognized Component D Package Top View and Device Symbol for Feed-Thru Pin-Out (Tip) K1 1 8 K1 (Tip) (Gate) G 2 7 A (Ground) NC 3 6 A (Ground) (Ring) K2 4 5 K2 (Ring) NC - No internal connection Terminal typical application names shown in parenthesis MD6XBDa K1 K1 A G A K2 K2 SD6XAEB D Package Top View and Device Symbol for Shunt (SD) Pin-Out K1 (Tip) K1 1 8 NC (Gate) G 2 7 A (Ground) NC 3 6 A (Ground) (Ring) K2 4 5 A G NC A MD6XBE NC - No internal connection Terminal typical application names shown in parenthesis K2 SD6XAU NOVEMBER 1995 – REVISED JULY 2019 WARNING Cancer and Reproductive Harm www.P65Warnings.ca.gov *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series How to Order Device Package Carrier Order As Device Package Carrier Order As TISP61089 D (Small-Outline) R† TISP61089DR-S TISP61089A D (Small-Outline) R† TISP61089ADR-S TISP61089S D (Small-Outline) R† TISP61089SDR-S TISP61089AS D (Small-Outline) R† TISP61089ASDR-S † Carrier R is Embossed Tape Reeled † Carrier R is Embossed Tape Reeled Description These ‘61089 parts are all dual forward-conducting buffered p-gate thyristor (SCR) overvoltage protectors. They are designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The ‘61089 limits voltages that exceed the SLIC supply rail voltage. The ‘61089 parameters are specified to allow equipment compliance with Telcordia (formally Bellcore) GR-1089-CORE and ITU-T recommendations K.20, K.21 and K.45. The SLIC line driver section is typically powered from 0 V (ground) and a negative (battery) voltage. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. The protection voltage will then track the negative supply voltage and the overvoltage stress on the SLIC is minimized. Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state condition. As the overvoltage subsides the high holding current of ‘61089 SCR helps prevent d.c. latchup. The ‘61089 is intended to be used with a series resistance of at least 25 Ω and a suitable overcurrent function for Telcordia compliance. Power fault conditions require a series overcurrent element which either interrupts or reduces the circuit current before the ‘61089 current rating is exceeded. For equipment compliant to ITU-T recommendations K.20 or K.21 or K.45 only, the series resistor value is set by the coordination requirements. For coordination with a 400 V limit GDT, a minimum series resistor value of 10 Ω is recommended. The ‘61089 buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The regular pin-out for surface mount and through-hole packages is a feed through configuration. Connection to the SLIC is made via the ‘61089, Ring through pins 4 - 5 and Tip through pins 1 - 8. A non-feed-through surface mount (D) package is available. This shunt (SD) version pin-out does not make duplicate connections to pin 5 and pin 8 which increases package creepage distance from ground of the other connections from about 0.7 mm to over 3 mm. High voltage ringing SLICs, with battery voltages below -100 V and down to -155 V, can be protected by the TISP61089B device. Details of this device are in the TISP61089B data sheet. NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series Absolute Maximum Ratings, -40 °C ≤ TJ ≤ 85 °C (Unless Otherwise Noted) Rating Symbol 61089 Repetitive peak off-state voltage, VGK = 0 ‘61089A 61089 Repetitive peak gate-cathode voltage, VKA = 0 ‘61089A Value Unit -100 VDRM V -120 -85 VGKRM V -120 Non-repetitive peak on-state pulse current (see Notes 1 and 2) 30 10/1000 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 5/320 s (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 s) IPPSM A 40 1.2/50 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 100 2/10 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 120 Non-repetitive peak on-state current, VGG = -75 V, 50 Hz to 60 Hz (see Notes 1 and 2) 0.1 s 11 1s 4.8 ITSM 5s A 2.7 0.95 300 s 0.93 900 s Non-repetitive peak gate current, 1/2 s pulse, cathodes commoned (see Notes 1 and 2) Operating free-air temperature range Junction temperature Storage temperature range IGSM +40 A TA -40 to +85 C TJ -40 to +150 C Tstg -40 to +150 C NOTES: 1. Initially the protector must be in thermal equilibrium with -40 C TJ 85 C. The surge may be repeated after the device returns to its initial conditions. Gate voltage ranges are -20 V to -75 V for the ‘61089 and -20 V to -100 V for the ‘61089A. 2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Above 85 C, derate linearly to zero at 150 C lead temperature. Recommended Operating Conditions Component CG RS Min Typ Gate decoupling capacitor 100 220 Max Unit Series resistor for GR-1089-CORE first-level surge survival 25 Ω Series resistor for GR-1089-CORE first-level and second-level surge survival 40 Ω nF Series resistor for GR-1089-CORE intra-building port surge survival 8 Ω Series resistor for K.20, K.21 and K.45 coordination with a 400 V primary protector 10 Ω NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series Electrical Characteristics, TJ = 25 °C (Unless Otherwise Noted) Parameter ID V(BO) VGK(BO) VF Test Conditions Off-state current Breakover voltage Min Typ TJ = 25 °C VD = VDRM , VGK = 0 TJ = 85 °C 2/10 μs, IPP = -56 A, RS = 45 Ω, VGG = -48 V, CG = 220 nF 2/10 μs, IPP = -100 A, RS = 50 Ω, VGG = -48 V, CG = 220 nF -57 1.2/50 μs, I PP = -53 A, RS = 47 Ω, VGG = -48 V, C G = 220 nF 1.2/50 μs, IPP = -96 A, RS = 52 Ω, VGG = -48 V, C G = 220 nF -60 2/10 μs, IPP = -56 A, RS = 45 Ω, VGG = -48 V, CG = 220 nF 9 Gate-cathode impulse 2/10 μs, IPP = -100 A, RS = 50 Ω, VGG = -48 V, CG = 220 nF 12 breakover voltage 1.2/50 μs, I PP = -53 A, RS = 47 Ω, VGG = -48 V, C G = 220 nF 12 1.2/50 μs, IPP = -96 A, RS = 52 Ω, VGG = -48 V, C G = 220 nF 16 Forward voltage IF = 5 A, tw = 200 μs 6 8 voltage 1.2/50 μs, I PP = 53 A, RS = 47 Ω, VGG = -48 V, C G = 220 nF 8 Holding current IT = -1 A, di/dt = 1A/ms, VGG = -48 V IGKS Gate reverse current VGG = VGK = VGKRM, VKA = 0 IGT Gate trigger current 1.2/50 μs, IPP = 96 A, RS = 52 Ω, VGG = -48 V, C G = 220 nF VGT QGS CKA voltage Gate switching charge Cathode-anode offstate capacitance -50 μA V V 3 2/10 μs, IPP = 100 A, RS = 50 Ω, VGG = -48 V, CG = 220 nF Gate-cathode trigger μA -64 2/10 μs, IPP = 56 A, RS = 45 Ω, VGG = -48 V, CG = 220 nF IH Unit -5 -60 Peak forward recovery VFRM Max V V 12 -150 mA TJ = 25 °C -5 μA TJ = 85 °C -50 μA IT = -3 A, tp(g) ≥ 20 μs, VGG = -48 V 5 mA IT = -3 A, tp(g) ≥ 20 μs, VGG = -48 V 2.5 V 1.2/50 μs, IPP = -53 A, RS = 47 Ω, VGG = -48 V, C G = 220 nF f = 1 MHz, Vd = 1 V, IG = 0, (see Note 3) 0.1 μC VD = -3 V 100 pF VD = -48 V 50 pF NOTES: 3. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. Thermal Characteristics Paramete r Test Conditions Min Typ Max Unit 120 °C/W TA = 25 °C, EIA/JESD51-3 RθJA Junction to free air thermal resistance PCB, EIA/JESD51-2 D Package environment, PTOT = 1.7 W NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series Parameter Measurement Information +i Quadrant I IPPSM Forward Conduction Characteristic IFSM (= |ITSM|) IF VF VGK(BO) VGG -v ID +v IH V(BO) IT ITSM Quadrant III IPPSM Switching Characteristic -i PM6XAAC Figure 1. Voltage-Current Characteristic Unless Otherwise Noted, All Voltages are Referenced to the Anode NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series Thermal Information PEAK NON-RECURRING AC vs CURRENT DURATION ITSM — Peak Non-Recurrent 50 Hz Current — A 20 TI61AFA RING AND TIP TERMINALS: Equal ITSM values applied simultaneously GROUND TERMINAL: Current twice ITSM value 15 10 8 7 6 5 4 EIA /JESD51 Environment and PCB, TA = 25 °C 3 VGG = -80 V VGG = -60 V 2 1.5 1 0.8 0.7 0.6 0.5 0.01 VGG = -100 V 0.1 1 10 100 t — Current Duration — s 1000 Figure 2. Non-repetitive Peak On-State Current against Duration (Gate Voltage Ranges are -20 V to -75 V for the '61089 and -20 V to -100 V for the '61089A) NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series APPLICATIONS INFORMATION Gated Protectors This section covers three topics. First, it is explained why gated protectors are needed. Second, the voltage limiting action of the protector is described. Third, an example application circuit is described. Purpose of Gated Protectors Fixed voltage thyristor overvoltage protectors have been used since the early 1980s to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. As the SLIC was usually powered from a fixed voltage negative supply rail, the limiting voltage of the protector could also be a fixed value. The TISP1072F3 is a typical example of a fixed voltage SLIC protector. SLICs have become more sophisticated. To minimize power consumption, some designs automatically adjust the supply voltage, VBAT, to a value that is just sufficient to drive the required line current. For short lines the supply voltage would be set low, but for long lines, a higher supply voltage would be generated to drive sufficient line current. The optimum protection for this type of SLIC would be given by a protection voltage which tracks the SLIC supply voltage. This can be achieved by connecting the protection thyristor gate to the SLIC supply, Figure 3. This gated (programmable) protection arrangement minimizes the voltage stress on the SLIC, no matter what value of supply voltage. TIP WIRE RSa 40 600 SLIC '61089 Th4 GENERATOR SOURCE RESISTANCE RSb 40 600 SWITCHING M ODE POWER SUPPLY Tx Th5 RING WIRE AC GENERATOR 0 - 600 V rms C1 220 nF IG C2 ISLIC IBAT VBAT D1 AI6XAGB Figure 3. ‘61089 Buffered Gate Protector Operation of Gated Protectors Figures 4 and 5 show how the ’61089 device limits negative and positive overvoltages. Positive overvoltages (Figure 5) are clipped by the antiparallel diodes in the ’61089 protector and the resulting current is diverted to ground. Negative overvoltages (Figure 4) are initially clipped close to the SLIC negative supply rail value (VBAT). If sufficient current is available from the overvoltage, then the protector (Th5) will crowbar into a low voltage on-state condition. As the overvoltage subsides the high holding current of the crowbar prevents d.c. latchup. The protection voltage will be the sum of the gate supply (VBAT) and the peak gate-cathode voltage (VGK(BO)). The protection voltage will be increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (IG) is the same as the cathode current (IK). Rates of 70 A/μs can cause inductive voltages of 0.7 V in 2.5 cm of printed wiring track. To minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking should be minimized. Inductive voltages in the protector cathode wiring will also increase the protection voltage. These voltages can be minimized by routing the SLIC connection through the protector as shown in Figure 3. Application Circuit Figure 6 shows a typical ’61089 part SLIC card protection circuit. The incoming line conductors, Ring (R) and Tip (T), connect to the relay matrix via the series overcurrent protection. Fusible resistors, fuses and positive temperature coefficient (PTC) thermistors can be used for overcurrent protection. Resistors will reduce the prospective current from the surge generator for both the ’61089 device and the ring/test NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series APPLICATIONS INFORMATION Application Circuit (Continued) protector. The TISP7xxxF3 protector has the same protection voltage for any terminal pair. This protector is used when the ring generator configuration may be ground or battery-backed. For dedicated ground-backed ringing generators, the TISP3xxxF3 gives better protection as its inter-conductor protection voltage is twice the conductor to ground value. Relay contacts 3a and 3b connect the line conductors to the SLIC via the ’61089 protector. The protector gate reference voltage comes from the SLIC negative supply (VBAT). A 220 nF gate capacitor sources the high gate current pulses caused by fast rising impulses. SLIC PROTEC TOR SLIC PROTEC TOR SLIC IF Th5 IK '61089 '61089 VBAT TIP WIRE VBAT C1 220 nF AI6XAHC AI6XAIC Figure 4. Negative Overvoltage Condition OVERCURRENT PROTEC TION Th5 IG C1 220 nF SLIC RING/TEST PROTEC TION Figure 5. Positive Overvoltage Condition TEST RELAY RING RELAY Th1 RSa SLIC RELAY S3a SLIC PROTEC TOR SLIC Th4 S2a S1a Th3 RING WIRE RSb Th5 Th2 TISP 3xxxF3 OR 7xxxF3 S3b S1b '61089 S2b C1 220 nF TEST EQUIPMENT RING GENERATOR VBAT AI6XAJC Figure 6. Typical Application Circuit NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089 Gated Protector Series MECHANICAL DATA Device Symbolization Code Devices will be coded as below. Device Symbolization Code TISP61089DR-S P61089 TISP61089SDR-S 61089S TISP61089ADR-S 61089A TISP61089ASDR-S 1089AS Asia-Pacific: Tel: +886-2 2562-4117 • Email: asiacus@bourns.com EMEA: Tel: +36 88 885 877 • Email: eurocus@bourns.com The Americas: Tel: +1-951 781-5500 • Email: americus@bourns.com www.bourns.com “TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in the U.S. Patent and Trademark Office. “Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries. NOVEMBER 1995 – REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. Legal Disclaimer Notice This legal disclaimer applies to purchasers and users of Bourns® products manufactured by or on behalf of Bourns, Inc. and P[ZHɉSPH[LZJVSSLJ[P]LS`¸)V\YUZ¹ Unless otherwise expressly indicated in writing, Bourns® products and data sheets relating thereto are subject to change ^P[OV\[UV[PJL