BS616LV4016ECP70

BSI FEATURES Very Low Power/Voltage CMOS SRAM 256K X 16 bit BS616LV4016 • Wide Vcc operation voltage : 2.4V ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 25mA (@55ns) operating current I -grade: 27mA (@55ns) operating current C-grade: 17mA (@70ns) operating current I -grade: 18mA (@70ns) operating current 0.45uA (Typ.) CMOS standby current • High speed access time : -55 55ns (Max.) at Vcc = 2.7~3.6V / 85oC -70 70ns (Max.) at Vcc = 2.4~3.6V / 85oC • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin DESCRIPTION The BS616LV4016 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.45uA at 3.0V/25oC and maximum access time of 55ns at 2.7V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV4016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4016 is available in DICE form , JEDEC standard 44-pin TSOP Type II package and 48-ball BGA package. PRODUCT FAMILY PRODUCT FAMILY BS616LV4016DC BS616LV4016EC BS616LV4016AC BS616LV4016DI BS616LV4016EI BS616LV4016AI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) 55ns: 2.7~3.6V 70ns: 2.4~3.6V ( I CCSB1 , Max ) POWER DISSIPATION Operating STANDBY ( I CC , Max ) PKG TYPE DICE Vcc = 3.0V Vcc = 3.0V 55ns 70ns +0 C to +70 C O O 2.4V ~ 3.6V 55 / 70 6.0uA 25mA 17mA -40 C to +85 C O O 2.4V ~ 3.6V 55 / 70 8.0uA 27mA 18mA TSOP2-44 BGA-48-0608 DICE TSOP2-44 BGA-48-0608 PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12 BLOCK DIAGRAM A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 2048 BS616LV4016EC BS616LV4016EI 2048 DQ0 16 Data Input Buffer 16 Column I/O . . . . DQ15 . . . . Write Driver Sense Amp 128 Column Decoder 16 Data Output 16 Buffer CE WE OE UB LB Vcc Gnd Control 14 Address Input Buffer A11 A10 A9 A8 A7 A6 A5 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV4016 1 Revision 1.1 Jan. 2004 BSI PIN DESCRIPTIONS BS616LV4016 Name A0-A17 Address Input CE Chip Enable Input Function These 18 address inputs select one of the 262,144 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled CE H X L L L WE X X X H H OE X X X H L LB X H H X L Read H L L Write L L X H L UB X H H X L L H L L H D0~D7 High Z High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , I CCSB1 ICCSB , I CCSB1 ICC ICC ICC ICC ICC ICC ICC ICC R0201-BS616LV4016 2 Revision 1.1 Jan. 2004 BSI ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with BS616LV4016 OPERATING RANGE UNITS V O O RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O Vcc 2.4V ~ 3.6V 2.4V ~ 3.6V C to +70 C to +85 O C Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C -40 O OC W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME VIL PARAMETER Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current Output Leakage Current Output Low Voltage TEST CONDITIONS Vcc=3.0V MIN. TYP.(1) MAX. -0.3 -0.8 UNITS V VIH IIL ILO VOL Vcc=3.0V 2.0 ---- ----- Vcc+0.3 V uA uA V Vcc = Max, V IN = 0V to Vcc Vcc = Max, CE = V IH , or OE,= V IH VI/O = 0V to Vcc Vcc = Max, I OL = 2.0mA Vcc=3.0V 1 1 0.4 VOH (5) Output High Voltage Operating Power Supply Current Standby Current-TTL (4) Vcc = Min, I OH = -1.0mA CE=VIL ,I DQ= 0mA, F=Fmax (3) Vcc=3.0V 2.4 -- -18 27 1.0 V ICC 70ns Vcc=3.0V 55ns -- -- mA ICCSB CE = V IH, I DQ= 0mA CE ≧ Vcc-0.2V, V IN ≧ Vcc - 0.2V or VIN ≦0.2V Vcc=3.0V -- -- mA ICCSB1 Standby Current-CMOS Vcc=3.0V -- 0.45 8 uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. IccSB1_max. is 6uA @Vcc=3.0V during 0oC~70oC. 5. Icc_Max. is 25mA(@55ns) / 17mA(@70ns) at Vcc=3.0V/ 0~70oC. R0201-BS616LV4016 3 Revision 1.1 Jan. 2004 BSI DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR ICCDR tCDR tR (3) BS616LV4016 TEST CONDITIONS CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V See Retention Waveform PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time O MIN. TYP. 1.5 -0 TRC (2) (1) MAX. -1.7 --- UNITS V uA ns ns -0.15 --- 1. Vcc = 1.5V, TA = + 25 C 2. tRC = Read Cycle Time 3. IccDR(Max.) is 1.2uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE R0201-BS616LV4016 4 Revision 1.1 Jan. 2004 BSI AC TEST CONDITIONS (Test Load and Input/Output Reference) BS616LV4016 KEY TO SWITCHING WAVEFORMS Vcc / 0V WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL , AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 55ns CYCLE TIME : 70ns (Vcc = 2.4~3.6V) DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change (Vcc = 2.7~3.6V) MIN. TYP. MAX. UNIT -ns ns ns ns ns ns ns ns ns ns ns ns MIN. TYP. MAX. tAVAX tAVQV tELQV tBA tGLQV t E1LQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX NOTE : tRC tAA tACS tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 55 --(LB,UB) --10 (LB,UB) 10 5 -(LB,UB) --10 ------------- -55 55 30 30 ---30 30 25 -- 70 ----10 10 5 ---10 ------------- 70 70 35 35 ---35 35 30 -- 1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle. R0201-BS616LV4016 5 Revision 1.1 Jan. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616LV4016 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t (5) CLZ t BDO t CHZ (5) READ CYCLE3 (1,4) t RC ADDRESS t OE AA t OE CE t OH t OLZ t CLZ (5) t ACS t OHZ (5) (1,5) t CHZ t BA LB,UB t BE D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS616LV4016 t BDO 6 Revision 1.1 Jan. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 55ns BS616LV4016 CYCLE TIME : 70ns (Vcc = 2.4~3.6V) DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (Vcc = 2.7~3.6V) MIN. TYP. MAX. MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW 55 55 0 55 30 (CE,WE) (LB,UB) 0 25 -25 0 -5 ------------- -------25 --25 -- 70 70 0 70 35 0 30 -30 0 -5 ------------- -------30 --30 -- NOTE : 1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t WR OE (3) t CW CE (5) (10) t BW LB,UB t AW WE (3) t AS (4,11) t WP (2) t OHZ D OUT t t DW DH D IN R0201-BS616LV4016 7 Revision 1.1 Jan. 2004 BSI WRITE CYCLE2 (1,6) BS616LV4016 t WC ADDRESS t CW CE (5) (10) t BW LB,UB t AW WE t WR t WP (2) (3) t AS (4,11) t WHZ D OUT t OW t DW t DH (8,9) (7) (8) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. TCW is measured from the later of CE going low to the end of write. 11. The parameter is guaranteed but not 100% tested. R0201-BS616LV4016 8 Revision 1.1 Jan. 2004 BSI ORDERING INFORMATION BS616LV4016 BS616LV4016 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608 D: DICE Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS616LV4016 9 Revision 1.1 Jan. 2004 BSI PACKAGE DIMENSIONS (continued) 0.25 ± 0.05 NOTES: BS616LV4016 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. SIDE VIEW D 0.1 D1 N 48 D 8.0 E 6.0 D1 5.25 E1 3.75 SOLDER BALL 0.35 ± 0.05 e VIEW A 48 mini-BGA (6 x 8mm) E ± 0.1 E1 R0201-BS616LV4016 10 Revision 1.1 Jan. 2004