BS616LV8010FI-70

BSI FEATURES Very Low Power/Voltage CMOS SRAM 512K X 16 bit (Single CE Pin) DESCRIPTION BS616LV8010 • Vcc operation voltage : 2.7~3.6V • Very low power consumption : Vcc = 3.0V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 1.5uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV8010 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA at 3V/25oC and maximum access time of 55ns at 3V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV8010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8010 is available in 48B BGA and 44L TSOP2 packages. PRODUCT FAMILY PRODUCT FAMILY BS616LV8010EC BS616LV8010FC BS616LV8010EI BS616LV8010FI OPERATING TEMPERATURE +0 C to +70 C -40 O C to +85O C O O Vcc RANGE 2.7V ~ 3.6V 2.7V ~ 3.6V SPEED ( ns ) 55ns : 3.0~3.6V 70ns : 2.7~3.6V ( I CCSB1, Max ) POWER DISSIPATION STANDBY Operating ( ICC , Max ) PKG TYPE TSOP2-44 BGA-48-0912 TSOP2-44 BGA-48-0912 Vcc=3V Vcc=3V 55ns Vcc=3V 70ns 55 / 70 55 / 70 5uA 10uA 30mA 31mA 24mA 25mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13 BLOCK DIAGRAM A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096 BS616LV8010EC BS616LV8010EI 4096 D0 16 Data Input Buffer 16 Column I/O 1 2 OE UB D10 D11 D12 D13 NC . A8 3 A0 A3 A5 A17 VSS A 14 A12 A9 4 A1 A4 A6 A7 A16 A 15 A 13 A 10 5 A2 CE D1 D3 D4 D5 WE A 11 6 NC D0 D2 V CC V SS D6 D7 NC A B C D E F G H LB D8 D9 V SS V CC D14 D15 A 18 . . . . D15 . . . . Write Driver Sense Amp 256 Column Decoder 16 Data Output 16 Buffer CE WE OE UB LB Vcc Vss Control 16 Address Input Buffer A11 A10 A9 A8 A7 A6 A5 A18 48-Ball CSP top View Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616LV8010 1 Revision 1.1 Jan. 2004 BSI PIN DESCRIPTIONS BS616LV8010 Function These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. Name A0-A18 Address Input CE Chip Enable Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground OE Output Enable Input LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Vss TRUTH TABLE MODE Not selected (Power Down) Output Disabled CE H X L L L WE X X X H H OE X X X H L LB X H H X L Read H L L Write L L X H L UB X H H X L L H L L H D0~D7 High Z High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , I CCSB1 ICCSB , I CCSB1 ICC ICC ICC ICC ICC ICC ICC ICC ABSOLUTE MAXIMUM SYMBOL VTERM TBIAS TSTG PT IOUT Terminal Voltage Respect to GND RATINGS(1) RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 PARAMETER with UNITS V O O OPERATING RANGE AMBIENT RANGE TEMPERATURE Commercial Industrial 0 O C to +70O C -40 C to +85 C O O Vcc 2.7V ~ 3.6V 2.7V ~ 3.6V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input CIN VIN=0V 10 pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Capacitance RATINGS may cause permanent damage to the device. This is a Input/Output CDQ VI/O=0V 12 pF stress rating only and functional operation of the device at these Capacitance or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute 1. This parameter is guaranteed and not 100% tested. maximum rating conditions for extended periods may affect reliability. R0201-BS616LV8010 2 Revision 1.1 Jan. 2004 BSI DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC (4) BS616LV8010 TEST CONDITIONS Vcc=3.0V Vcc=3.0V PARAMETER Guaranteed Input Low Voltage (3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current MIN. TYP. -0.5 2.0 ---2.4 -------------- (1) MAX. 0.8 Vcc+0.3 1 1 0.4 -31 25 1 10 UNITS V V uA uA V V mA mA uA Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH , or OE = VIH , VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = VIL ,IDQ = 0mA ,F = Fmax(2) CE = VIH ,I DQ = 0mA CE ≧ Vcc -0.2V, VIN ≧ Vcc - 0.2V or VIN≦ 0.2V 55ns 70ns Vcc=3.0V Vcc=3.0V Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current - TTL Standby Current - CMOS Vcc=3.0V Vcc=3.0V ICCSB ICCSB1 (5) Vcc=3.0V 1.5 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 30mA(@55ns) / 24mA(@70ns) during 0~70oC operation. 5.IccsB1 is 5uA at Vcc=3.0V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR ICCDR tCDR tR (3) PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time TEST CONDITIONS CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V See Retention Waveform MIN. 1.5 -0 TRC (2) TYP. (1) -0.8 --- MAX. -2.5 --- UNITS V uA ns ns 2. tRC = Read Cycle Time 1. Vcc = 1.5V, TA = + 25OC 3. IccDR(Max.) is 1.3uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE R0201-BS616LV8010 3 Revision 1.1 Jan. 2004 BSI AC TEST CONDITIONS (Test Load and Input/Output Reference) BS616LV8010 KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load , AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time (1) CYCLE TIME : 70ns CYCLE TIME : 55ns MIN. TYP. MAX. Vcc = 2.7~3.6V MIN. TYP. MAX. Vcc = 3.0~3.6V UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tAVQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX tRC tAA t ACS tBA tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 70 -(CE) (LB,UB) ------------- -70 70 35 35 ---35 35 30 -- 55 ----10 5 5 ---10 ------------- -55 55 30 30 ---30 30 25 -- ---10 5 5 ---10 Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z (CE) (LB,UB) (CE) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z Data Hold from Address Change NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle . R0201-BS616LV8010 4 Revision 1.1 Jan. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616LV8010 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t (5) CLZ t BDO t (5) CHZ READ CYCLE3 (1,4) ADDRESS t RC t OE AA t CE OE t OH t t t (5) CLZ OLZ ACS t t OHZ CHZ (5) (1,5) LB,UB t BE t t BA BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL . 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS616LV8010 5 Revision 1.1 Jan. 2004 BSI WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME BS616LV8010 85oC ) CYCLE TIME : 70ns CYCLE TIME : 55ns Vcc = 2.7~3.6V Vcc = 3.0~3.6V AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time MIN. TYP. MAX. MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WHOX t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW 70 70 0 70 35 (CE,WE) 0 30 -30 0 -5 ------------- -------30 --30 -- 55 55 0 55 30 0 25 -25 0 -5 ------------- -------25 --25 -- Date Byte Control to End of Write (LB,UB) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t ADDRESS WC t WR OE (3) t CW CE (5) (11) t LB,UB (5) BW t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS616LV8010 Revision 1.1 Jan. 2004 6 BSI WRITE CYCLE2 (1,6) BS616LV8010 t WC ADDRESS (11) CE (5) t t CW BW LB,UB (5) t WE AW t WP t WR (3) (2) t AS (4,10) t WHZ D OUT t t DW t OW (7) (8) DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616LV8010 7 Revision 1.1 Jan. 2004 BSI ORDERING INFORMATION BS616LV8010 Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC BS616LV8010 X X PACKAGE F :BGA-48-0912 E :TSOP2-44 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS 0.25 ± 0.05 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. SIDE VIEW D 0.1 3.375 D1 N 48 D 12.0 E 9.0 D1 5.25 E1 3.75 e 0.75 SOLDER BALL 0.35± 0.05 e VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS616LV8010 2.625 E ± 0.1 E1 8 Revision 1.1 Jan. 2004 BSI PACKAGE DIMENSIONS (continued) BS616LV8010 TSOP2-44 R0201-BS616LV8010 9 Revision 1.1 Jan. 2004