BS616LV8012BC

BSI FEATURES Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION BS616LV8012 • Very low operation voltage : 2.4~5.5V • Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current I-grade : 25mA (Max.) operating current 0.5uA (Typ.) CMOS standby current Vcc = 5.0V C-grade: 45mA (Max.) operating current I-grade : 50mA (Max.) operating current 3uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc=3V -10 100ns (Max.) at Vcc=3V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2,CE1 and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV8012 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.5uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable(CE1), active HIGH chip enable (CE2), active LOW output enable(OE) and three-state output drivers. The BS616LV8012 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8012 is available in 48-pin BGA package. PRODUCT FAMILY SPEED (ns) Vcc=3V PRODUCT FAMILY OPERATING TEMPERATURE +0 C to +70 C -40 O C to +85 O C O O Vcc RANGE 2.4V ~ 5.5V 2.4V ~ 5.5V POWER DISSIPATION STANDBY Operating (ICCSB1, Max) (ICC, Max) PKG TYPE Vcc=3V Vcc=5V Vcc=3V Vcc=5V BS616LV8012BC BS616LV8012BI 70 / 100 70 / 100 3uA 6uA 30uA 100uA 20mA 25mA 45mA 50mA BGA-48-0810 BGA-48-0810 PIN CONFIGURATIONS 1 A B C D E F G H LB D8 D9 VSS 2 OE UB D10 D11 3 A0 A3 A5 A17 VSS A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 D1 D3 D4 D5 WE A11 6 CE2 D0 D2 VCC VSS D6 D7 BLOCK DIAGRAM A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096 4096 D0 16 Data Input Buffer 16 Column I/O VCC D14 D15 A 18 D12 D13 NC . A8 . . . . D15 CE2 CE1 WE OE UB LB . . . . Write Driver Sense Amp 256 Column Decoder 16 Data Output 16 Buffer 16 Control Address Input Buffer NC A11 A10 A9 A8 A7 A6 A5 A18 Vcc Vss 48-Ball CSP top View Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616LV8012 1 Revision 2.4 April 2002 BSI PIN DESCRIPTIONS BS616LV8012 Function These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground Name A0-A18 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Vss TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read CE1 H X L L CE2 X L H H WE X X H H OE X X H L LB X X X L H L L Write L H L X H L UB X X X L L H L L H D0~D7 High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , I CCSB1 ICCSB , I CCSB1 ICC ICC ICC ICC ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70O C -40 C to +85 C O O Vcc 2.4V ~ 5.5V 2.4V ~ 5.5V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input CIN VIN=0V 10 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Capacitance RATINGS may cause permanent damage to the device. This is a Input/Output CDQ VI/O=0V 12 stress rating only and functional operation of the device at these Capacitance or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute 1. This parameter is guaranteed and not tested. maximum rating conditions for extended periods may affect reliability. pF pF R0201-BS616LV8012 2 Revision 2.4 April 2002 BSI DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC ICCSB PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH , or CE2 = V iL , or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL= 2mA Vcc = Min, IOH= -1mA Vcc= max, CE1 = VIL and CE2 = VIH, IDQ = 0mA, F = Fmax(3) Vcc= max, CE1 = VIH or CE2 = VIL, IDQ = 0mA Vcc= max,CE1 Vcc-0.2V, or CE2 0.2V, VIN Vcc - 0.2V or VIN 0.2V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V BS616LV8012 TEST CONDITIONS Vcc=3V Vcc=5V Vcc=3V Vcc=5V MIN. TYP. -0.5 -- (1) MAX. 0.8 0.8 Vcc+0.2 Vcc+0.2 1 1 0.4 0.4 --20 45 1 2 3 UNITS -0.5 2.0 2.2 ----2.4 2.4 ------- -------------0.5 3 V V uA uA V V mA mA ICCSB1 Standby Current-CMOS uA 30 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL VDR ICCDR tCDR tR PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE1 VIN CE1 VIN TEST CONDITIONS Vcc - 0.2V or CE2 0.2V Vcc - 0.2V or VIN 0.2V Vcc - 0.2V or CE2 0.2V Vcc - 0.2V or VIN 0.2V MIN. TYP. 1.5 -0 TRC (2) (1) MAX. -2 --- UNITS V uA ns ns -0.2 --- See Retention Waveform 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE1≥ Vcc - 0.2V tR VIH CE1 LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc Vcc VDR 1.5V Vcc t CDR tR CE2 0.2V CE2 R0201-BS616LV8012 VIL VIL 3 Revision 2.4 April 2002 BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc WAVEFORM BS616LV8012 KEY TO SWITCHING WAVEFORMS INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED 1404 Ω OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC TEST LOADS AND WAVEFORMS 1269 Ω 1269 Ω 3.3V OUTPUT 3.3V OUTPUT , 100PF INCLUDING JIG AND SCOPE 5PF 1404 Ω INCLUDING JIG AND SCOPE DOES NOT APPLY FIGURE 1A THEVENIN EQUIVALENT 667 Ω FIGURE 1B OUTPUT 1.73V ALL INPUT PULSES Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=3V) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) (LB,UB) (CE1) (CE2) (LB,UB) BS616LV8012-70 MIN. TYP. MAX. BS616LV8012-10 MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tAVQV tELQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX tRC tAA t ACS1 t ACS2 tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 70 -----10 10 10 0 0 0 10 -------------- -70 70 70 35 35 ---35 35 30 -- 100 -----15 15 15 0 0 0 15 -------------- -100 100 100 50 50 ---40 40 35 -- Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z (CE2,CE1) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z Output Disable to Address Change NOTE : 1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle . tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle . R0201-BS616LV8012 4 Revision 2.4 April 2002 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616LV8012 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE2 t t ACS2 ACS1 CE1 t D OUT (5) CLZ (5) t CHZ READ CYCLE3 (1,4) ADDRESS t RC t OE AA t CE2 OE t OH t t t t (5) CLZ ACS2 CE1 OLZ ACS1 t t OHZ CHZ (5) (1,5) LB,UB t BE t t BA BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616LV8012 5 Revision 2.4 April 2002 BSI WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME BS616LV8012 DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time BS616LV8012-70 MIN. TYP. MAX. BS616LV8012-10 MIN. TYP. MAX. AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=3V) UNIT ns ns ns ns ns ns ns ns ns ns ns ns t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WHOX t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW 70 70 0 70 35 (CE2,CE1,WE) 0 30 0 30 0 0 5 ------------- -------30 --30 -- 100 100 0 100 50 0 40 0 40 0 0 10 ------------- -------40 --40 -- Date Byte Control to End of Write (LB,UB) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active NOTE : 1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC t WR OE (3) CE2 (5) t CW CE1 (5) (11) t LB,UB (5) BW t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS616LV8012 Revision 2.4 April 2002 6 BSI WRITE CYCLE2 (1,6) BS616LV8012 t WC ADDRESS CE2 (11) CE1 (5) t t CW BW LB,UB (5) t WE AW t WP t WR (3) (2) t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS616LV8012 7 Revision 2.4 April 2002 BSI ORDERING INFORMATION BS616LV8012 BS616LV8012 XX -- Y Y SPEED 70:70ns 10: 100ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE B :BGA - 48 PIN(8x10mm) PACKAGE DIMENSIONS 0.05 0.25 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. SIDE VIEW D 0.1 D1 N 48 D 10.0 E 8.0 D1 5.25 E1 3.75 e 0.75 SOLDER BALL 0.35 0.05 e E1 VIEW A 48 mini-BGA (8 x 10mm) R0201-BS616LV8012 E 0.1 8 Revision 2.4 April 2002 BSI REVISION HISTORY Revision 2.2 2.3 2.4 BS616LV8012 Description 2001 Data Sheet release Date Apr. 15, 2001 Note Modify Standby Current (Typ. and Jun. 29, 2001 Max.) Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 50uA to 100uA. April,10,2002 R0201-BS616LV8012 9 Revision 2.4 April 2002