BS616LV8025

BSI FEATURES Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable DESCRIPTION BS616LV8025 • Very low operation voltage : 4.5 ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 45mA (Max.) operating current I-grade : 50mA (Max.) operating current 3uA (Typ.) CMOS standby current • High speed access time : -55 55ns (Max.) at Vcc= 5.0V -70 70ns (Max.) at Vcc= 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin The BS616LV8025 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 3uA and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV8025 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8025 is available in 48-pin BGA type. PRODUCT FAMILY SPEED (ns) Vcc=5V PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE (I CCSB1 , Max) POWER DISSIPATION STANDBY Operating (I CC , Max) PKG TYPE Vcc=5V Vcc=5V BS616LV8025BC BS616LV8025BI +0 O C to +70O C 4.5V ~ 5.5V -40 O C to +85O C 4.5V ~5.5V 55/70 55/70 30uA 100uA 45mA 50mA BGA -48-0810 BGA -48-0810 PIN CONFIGURATIONS 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 A18 2 OE UB D10 D11 D12 D13 CIO . A8 3 A0 A3 A5 A17 VSS A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 D1 D3 D4 D5 6 CE2 D0 D2 VCC VSS D6 D7 SAE. BLOCK DIAGRAM A15 A14 A13 A12 A11 A10 A9 A8 A17 A7 A6 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096 4096 D0 16(8) Data Input Buffer 16(8) Column I/O . . . . D15 CE1 CE2 WE OE UB LB CIO Vdd GND . . . . Write Driver 16(8) Sense Amp 256(512) Column Decoder 16(8) Data Output Buffer 16(18) Control Address Input Buffer WE A11 A16 A0 A1 A2 A3 A4 A5 A18 (SAE) 48-Ball CSP top View Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616LV8025 1 Revision 2.4 April 2002 BSI PIN DESCRIPTIONS BS616LV8025 Name A0-A18 Address Input SAE Address Input CIO x8/x16 select input Function These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. This address input incorporate with the above 19 address inputs select one of the 1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH. This input selects the organization of the SRAM. 524,288 x 16-bit words configuration is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is LOW. CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Vss Lower byte and upper byte data input/output control pins. The chip is deselected when both LB and UB pins are HIGH. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground R0201-BS616LV8025 2 Revision 2.4 April 2002 BSI TRUTH TABLE MODE CE1 H X Output Disable L CE2 X L H X X OE WE CIO LB X X H X X L Read from SRAM ( WORD mode ) L H L H H H L L Write to SRAM ( WORD mode ) L H X L H H L Read from SRAM ( BYTE Mode ) Write to SRAM ( BYTE Mode ) L H L H L X UB X X X X H L L H L L X A-1 X X X SAE BS616LV8025 D0~7 D8~15 VCC Current Fully Standby X High-Z High-Z ICCSB, ICCSB1 H High-Z Dout High-Z Dout Din X Din Dout High-Z High-Z Dout Dout X Din Din High-Z ICC ICC ICC ICC L H X L L X X A-1 Din X ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 C to +85 C O O Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ VIN=0V VI/O=0V 10 12 pF pF 1. This parameter is guaranteed and not tested. R0201-BS616LV8025 3 Revision 2.4 April 2002 BSI DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC BS616LV8025 TEST CONDITIONS Vcc=5V Vcc=5V PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL MIN. TYP. (1) MAX. -0.5 2.2 ---2.4 --------0.8 Vcc+0.2 1 1 0.4 -45 UNITS V V uA uA V V mA Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH , or CE2 = ViL, or OE = VIH, VI/O = 0V to Vcc Vcc= max, IOL = 2mA Vcc= Min, IOH = -1mA Vcc= max, CE1 = VIL and CE2 = VIH, IDQ = 0mA, F = Fmax(3) Vcc= max, CE1 = VIH or CE2 = VIL, IDQ = 0mA Vcc= max,CE1 Vcc-0.2V, or Vcc - 0.2V CE2 0.2V, VIN 0.2V or VIN Vcc=5V Vcc=5V Vcc=5V ICCSB Vcc=5V -- -- 2 mA ICCSB1 Standby Current-CMOS Vcc=5V -- 3 30 uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/ tRC . R0201-BS616LV8025 4 Revision 2.4 April 2002 BSI DATA RETENTION CHARACTERISTICS ( TA = 0oC to +70oC ) SYMBOL VDR BS616LV8025 TEST CONDITIONS CE1 VIN CE1 VIN Vcc - 0.2V or CE2 0.2V , Vcc - 0.2V or VIN 0.2V Vcc - 0.2V or CE2 0.2V, Vcc - 0.2V or VIN 0.2V PARAMETER Vcc for Data Retention MIN. 1.5 TYP. (1) -- MAX. -- UNITS V ICCDR Data Retention Current Chip Deselect to Data Retention Time -- 0.2 2 uA tCDR tR 0 See Retention Waveform TRC (2) --- --- ns ns Operation Recovery Time 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VIH Vcc VDR 1.5V Vcc t CDR CE1 Vcc - 0.2V tR VIH CE1 LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc Vcc VDR 1.5V Vcc t CDR tR CE2 0.2V CE2 VIL VIL R0201-BS616LV8025 5 Revision 2.4 April 2002 BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc WAVEFORM BS616LV8025 KEY TO SWITCHING WAVEFORMS INPUTS MUST BE STEADY MAY CHANGE FROM H TO L 1928 Ω OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC TEST LOADS AND WAVEFORMS 5.0V OUTPUT 100PF INCLUDING JIG AND SCOPE 1928 Ω 5.0V OUTPUT MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY 5PF 1020 Ω INCLUDING JIG AND SCOPE , 1020 Ω FIGURE 1A THEVENIN EQUIVALENT 667 Ω FIGURE 1B OUTPUT 1.73V ALL INPUT PULSES Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=5V ) READ CYCLE JEDEC PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time (CE1) (CE2) Chip Select Access Time Data Byte Control Access Time (LB,UB) Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) Data Byte Control to Output Low Z (LB,UB) Output Enable to Output in Low Z Chip Deselect to Output in High Z (CE2,CE1) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z Output Disable to Output Address Change BS616LV8025-55 MIN. TYP. MAX. 55 55 55 55 30 30 10 10 10 0 0 0 10 10 10 10 0 0 0 10 BS616LV8025-70 MIN. TYP. MAX. 70 70 70 70 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT PARAMETER NAME tAVAX tAVQV tE1LQV tE2LQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXQX tRC tAA tACS1 tACS2 tBA(1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 30 30 25 35 35 30 NOTE : 1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle . tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle . R0201-BS616LV8025 6 Revision 2.4 April 2002 BSI READ CYCLE1 (1,2,4) ADDRESS BS616LV8025 t RC t AA t OH t OH D OUT READ CYCLE2 (1,3,4) CE2 t t ACS2 ACS1 CE1 t D OUT (5) CLZ (5) t CHZ READ CYCLE3 (1,4) ADDRESS t RC t OE AA t CE2 OE t OH t t t t (5) CLZ ACS2 CE1 OLZ ACS1 t t OHZ CHZ (5) (1,5) LB,UB t BE t t BA BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616LV8025 7 Revision 2.4 April 2002 BSI AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=5V) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width (CE2, CE1, WE) Write Recovery Time Data Byte Control to End of Write(LB,UB) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active BS616LV8025-55 MIN. 55 55 0 55 30 0 25 0 25 0 0 5 TYP. MAX. BS616LV8025 BS616LV8025-70 MIN. 70 70 0 70 35 0 30 0 30 0 0 5 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tCW tAS tAW tWP tWR tBW (1) tWHZ tDW tDH tOHZ tOW 25 30 25 30 NOTE : 1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t ADDRESS WC t WR OE (3) CE2 (5) t CW CE1 (5) (11) t LB,UB (5) BW t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS616LV8025 8 Revision 2.4 April 2002 BSI WRITE CYCLE2 (1,6) BS616LV8025 t WC ADDRESS CE2 (11) CE1 (5) t t CW BW LB,UB (5) t WE AW t WP t WR (3) (2) t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS616LV8025 9 Revision 2.4 April 2002 BSI ORDERING INFORMATION BS616LV8025 BS616LV8025 XX -- Y Y SPEED 55: 55ns 70: 70ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE B :BGA - 48 PIN(8x10mm) PACKAGE DIMENSIONS 0.05 0.25 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. SIDE VIEW D 0.1 D1 N 48 D 10.0 E 8.0 D1 5.25 E1 3.75 e 0.75 SOLDER BALL 0.35 0.05 e VIEW A 48 mini-BGA (8 x 10mm) R0201-BS616LV8025 E 0.1 E1 10 Revision 2.4 April 2002 BSI REVISION HISTORY Revision 2.2 2.3 2.4 BS616LV8025 Description 2001 Data Sheet release Date Apr. 15, 2001 Note Modify Standby Current (Typ. and Jun. 29, 2001 Max.) Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 50uA to 100uA. April,12,2002 R0201-BS616LV8025 11 Revision 2.4 April 2002