BS616UV1010DC10

Ultra Low Power CMOS SRAM 64K X 16 bit Pb-Free and Green package materials are compliant to RoHS BS616UV1010 n FEATURES Ÿ Wide VCC low operation voltage : 1.9V ~ 3.6V Ÿ Ultra low power consumption : VCC = 2.0V Operation current : 15mA (Max.) at 100ns 1.0mA (Max.) at 1MHz Standby current : 0.01uA (Typ.) at 25 OC VCC = 3.0V Operation current : 20mA (Max.) at 100ns 2.0mA (Max.) at 1MHz Standby current : 0.02uA (Typ.) at 25OC Ÿ High speed access time : -10 100ns (Max.) Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ I/O Configuration x8/x16 selectable by LB and UB pin. Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V n DESCRIPTION The BS616UV1010 is a high performance, ultra low power CMOS Static Random Access Memory organized as 65,536 by 16 bits and operates form a wide range of 1.9V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.01uA at 2.0V/25OC and maximum access time of 100ns at 2.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616UV1010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV1010 is available in DICE form, JEDEC standard 44-pin TSOP II and 48-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY BS616UV1010DC BS616UV1010AC BS616UV1010EC BS616UV1010AI BS616UV1010EI Industrial -40OC to +85OC 1.5uA 1.0uA 2.0mA 20mA 1.0mA 15mA Commercial +0OC to +70OC 1.0uA 0.5uA 1.5mA 18mA 0.8mA 13mA OPERATING TEMPERATURE STANDBY (ICCSB1, Max) Operating (ICC, Max) PKG TYPE VCC=2.0V fMax. VCC=3.0V VCC=2.0V VCC=3.0V 1MHz fMax. 1MHz DICE BGA-48-0608 TSOP II-44 BGA-48-0608 TSOP II-44 n PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC n BLOCK DIAGRAM A8 A13 A15 A14 A12 A7 A6 A5 A4 2048 DQ0 . . . . . . DQ15 16 . . . . . . Data Input Buffer 16 128 Column Decoder 7 Control Address Input Buffer 16 Column I/O Write Driver Sense Amp Address Input Buffer 9 Row Decoder 512 x 2048 512 Memory Array BS616UV1010EC BS616UV1010EI 16 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 NC 2 OE UB D10 D11 D12 D13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE D1 D3 D4 D5 WE A11 6 NC D0 D2 VCC VSS D6 D7 NC Data Output Buffer CE WE OE UB LB VCC VSS A11 A9 A3 A2 A1 A0 A10 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS616UV1010 1 Revision 2.6 May. 2006 BS616UV1010 n PIN DESCRIPTIONS Name A0-A15 Address Input CE Chip Enable Input Function These 16 address inputs select one of the 65,536 x 16-bit in the RAM CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. Lower byte and upper byte data input/output control pins. WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input DQ0-DQ15 Data Input/Output Ports VCC VSS There 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground n TRUTH TABLE MODE Chip De-selected (Power Down) CE H X L WE X X H H OE X X H H LB X H L X L UB X H X L L L H L L H IO0~IO7 High Z High Z High Z High Z DOUT High Z DOUT DIN X DIN IO8~IO15 High Z High Z High Z High Z DOUT DOUT High Z DIN DIN X VCC CURRENT ICCSB, ICCSB1 ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC ICC Output Disabled L Read L H L H L L Write L L X H L NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BS616UV1010 2 Revision 2.6 May. 2006 BS616UV1010 n ABSOLUTE MAXIMUM RATINGS SYMBOL VTERM TBIAS TSTG PT IOUT (1) n OPERATING RANGE UNITS V O PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5(2) to 5.0 -40 to +125 -60 to +150 1.0 20 RANG Commercial Industrial AMBIENT TEMPERATURE 0OC to + 70OC -40OC to + 85OC VCC 1.9V ~ 3.6V 1.9V ~ 3.6V C C O W mA n CAPACITANCE (1) (TA = 25 C, f = 1.0MHz) O SYMBOL PAMAMETER CONDITIONS MAX. UNITS CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. 1. This parameter is guaranteed and not 100% tested. n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC ICC1 ICCSB ICCSB1(5) PARAMETER Power Supply VCC=2.0V VCC=3.0V O O TEST CONDITIONS MIN. 1.9 -0.3(2) 1.4 2.2 -- TYP.(1) -- MAX. 3.6 0.6 0.8 UNITS V Input Low Voltage -- V Input High Voltage VCC=2.0V VCC=3.0V -- VCC+0.3(3) V Input Leakage Current VIN = 0V to VCC VI/O = 0V to V CC, CE= VIH or OE = VIH V CC = Max, IOL = 0.1mA V CC = Max, IOL = 2.0mA VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V -- 1 uA Output Leakage Current -- -- 1 0.2 0.4 uA Output Low Voltage -1.6 2.4 -- -- V Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current – TTL V CC = Min, IOH = -0.1mA V CC = Min, IOH = -1.0mA CE = VIL, IIO = 0mA, f = FMAX(4) CE = VIL, IIO = 0mA, f = 1MHz CE = VIH, IIO = 0mA CE≧ VCC-0.2V VIN≧ V CC-0.2V or VIN≦ 0.2V -- -15 20 V -- mA -- -- 1.0 2.0 mA -- -0.01 0.02 0.5 1.0 mA Standby Current – CMOS -- 1.0 1.5 uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC(MIN.). 5. ICC (MAX.) is 13mA/18mA at VCC=2.0V/3.0V and TA=70OC. 6. ICCSB1(MAX.) is 0.5uA/1.0uA at VCC=2.0V/3.0V and TA=70OC. R0201-BS616UV1010 3 Revision 2.6 May. 2006 BS616UV1010 n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL VDR ICCDR (3) O O PARAMETER VCC for Data Retention TEST CONDITIONS CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V MIN. 1.5 TYP. (1) -- MAX. -- UNITS V Data Retention Current Chip Deselect to Data Retention Time -- 0.01 0.5 uA tCDR tR 0 See Retention Waveform tRC (2) -- -- ns Operation Recovery Time -- -- ns 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 0.2uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (CE Controlled) Data Retention Mode VCC VIH VCC VDR≧1.5V VCC tCDR CE≧VCC - 0.2V tR VIH CE n AC TEST CONDITIONS (Test Load and Input/Output Reference) n KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “L” TO “H” CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE “OFF” STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 10% 90% 90% 10% →← Rise Time: 1V/ns →← Fall Time: 1V/ns 1. Including jig and scope capacitance. R0201-BS616UV1010 4 Revision 2.6 May. 2006 BS616UV1010 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARAMETER NAME PARANETER NAME CYCLE TIME : 100ns DESCRIPTION MIN. Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Data Byte Control to Output High Z Output Enable to Output High Z Data Hold from Address Change (CE) (LB, UB) (CE) (LB, UB) (CE) (LB, UB) 100 ----15 15 15 ---15 TYP. ------------M AX. -100 100 100 50 ---40 40 35 -ns ns ns ns ns ns ns ns ns ns ns ns UNITS O O tAVAX tAVQX tELQV tBLQV tGLQV tELQX tBLQX tGLQX tEHQZ tBHQZ tGHQZ tAVQX tRC tAA tACS tBA tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH DOUT tAA tOH R0201-BS616UV1010 5 Revision 2.6 May. 2006 BS616UV1010 READ CYCLE 2 CE tACS tBA LB, UB tBE DOUT tCLZ (5) (1,3,4) tCHZ tBDO (5) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE tCLZ LB, UB (5) tOH tOLZ tOHZ tCHZ tBA tBE tBDO (5) (1,5) DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS616UV1010 6 Revision 2.6 May. 2006 BS616UV1010 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARAMETER NAME PARANETER NAME CYCLE TIME : 100ns DESCRIPTION MIN. Write Cycle Time Address Set up Time Address Valid to End of Write Chip Select to End of Write Data Byte Control to End of Write Write Pulse Width Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE, WE) (CE) (LB, UB) 100 0 100 100 100 50 0 -40 0 -10 TYP. ------------M AX. -------40 --40 -ns ns ns ns ns ns ns ns ns ns ns ns UNITS O O tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tAS tAW tCW tBW tWP tWR tWHZ tDW tDH tOHZ tOW n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1 OE tCW CE (5) (11) (3) tBW LB, UB tAW WE tAS tOHZ DOUT tDH tDW DIN (4,10) (3) tWR2 tWP (2) R0201-BS616UV1010 7 Revision 2.6 May. 2006 BS616UV1010 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW (11) CE (5) LB, UB (12) tBW tAW (3) WE tAS tWHZ DOUT (4,10) tWP (2) tWR2 tOW tDW tDH (8,9) (7) (8) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write. 12. The change of Read/Write cycle must accompany with CE or address toggled. R0201-BS616UV1010 8 Revision 2.6 May. 2006 BS616UV1010 n ORDERING INFORMATION Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does BS616UV1010 X X Z Y Y not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. SPEED 10: 100ns n PACKAGE DIMENSIONS n PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE A: BGA-48-0608 E: TSOP II-44 TSOP II-44 R0201-BS616UV1010 9 Revision 2.6 May. 2006 BS616UV1010 PACKAGE DIMENSIONS (continued) NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.2 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 48 mini-BGA (6 x 8mm) E1 R0201-BS616UV1010 10 Revision 2.6 May. 2006 BS616UV1010 n Revision History Revision No. 2.5 2.6 History Add Icc1 characteristic parameter Change I-grade operation temperature range - from –25OC to –40OC Draft Date Jan. 13, 2006 May. 25, 2006 Remark R0201-BS616UV1010 11 Revision 2.6 May. 2006