BS616UV2011

BSI FEATURES Ultra Low Power/Voltage CMOS SRAM 128K X 16 bit DESCRIPTION BS616UV2011 • Ultra low operation voltage : 1.8 ~ 3.6V • Ultra low power consumption : Vcc = 2.0 V C-grade: 15mA (Max.) operating current I-grade: 20mA (Max.) operating current 0.08uA (Typ.) CMOS standby current Vcc = 3.0 V C-grade: 20mA (Max.) operating current I -grade: 25mA (Max.) operating current 0.1uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 2.0V -10 100ns (Max.) at Vcc = 2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616UV2011 is a high performance, Ultra low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.08uA and maximum access time of 70/100ns in 2.0V operation. Easy memory expansion is provided by an active LOW chip enable(CE), active LOW output enable(OE) and three-state output drivers. The BS616UV2011 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV2011 is available in DICE form, JEDEC standard 44-pin TSOP Type II package , JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) Vcc= 2.0V 70/100 ( I CCSB1, Max ) POWER DISSIPATION STANDBY Operating ( I CC , Max ) PKG TYPE DICE TSOP2-44 TSOP1-48 BGA-48-0608 DICE TSOP2-44 TSOP1-48 BGA-48-0608 Vcc= 2.0V 0.5uA Vcc= 3.0V 0.7uA Vcc= 2.0V 15mA Vcc= 3.0V 20mA BS616UV2011DC BS616UV2011EC BS616UV2011TC BS616UV2011AC BS616UV2011DI BS616UV2011EI BS616UV2011TI BS616UV2011AI +0 C to +70 C O O 1.8V ~ 3.6V -40O C to +85OC 1.8V ~ 3.6V 70/100 1uA 1.5uA 20mA 25mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC BLOCK DIAGRAM A8 A13 A15 A16 A14 A12 A7 A6 A5 A4 2048 DQ0 16 Data Input Buffer 16 Column I/O Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 BS616UV2011EC BS616UV2011EI 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 N.C. 2 OE UB D10 D11 D12 D13 N.C. A8 3 A0 A3 A5 N.C. N.C. A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE D1 D3 D4 D5 WE A11 6 N.C. D0 D2 VCC VSS D6 D7 N.C. . . . . DQ15 . . . . Write Driver Sense Amp 128 Column Decoder 16 Data Output 16 Buffer CE WE OE UB LB Vcc Gnd Control 14 Address Input Buffer A11 A9 A3 A2 A1 A0 A10 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616UV2011 48-ball BGA top view 1 Revision 2.5 April 2002 BSI PIN DESCRIPTIONS BS616UV2011 Name A0-A16 Address Input CE Chip Enable Input Function These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read CE H L L WE X H H OE X H L LB X X L H L L Write L L X H L UB X X L L H L L H DQ0~DQ7 High Z High Z Dout High Z Dout Din X Din DQ8~DQ15 High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC R0201-BS616UV2011 2 Revision 2.5 April 2002 BSI ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with BS616UV2011 OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 O C to +85 O C Vcc 1.8V ~ 3.6V 1.8V ~ 3.6V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not tested. DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current Standby Current TTL CMOS TEST CONDITIONS Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V MIN. TYP. -0.5 1.4 2.0 --Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V (1) MAX. 0.6 0.8 Vcc+0.2 1 1 0.4 -15 20 0.1 0.5 0.5 0.7 UNITS V V uA uA V V mA mA uA ----------0.08 0.1 Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 1mA Vcc = Min, IOH = -0.5mA CE = VIL, IDQ = 0mA, F = Fmax(3) CE = VIH, IDQ = 0mA CE VIN Vcc-0.2V, Vcc - 0.2V or VIN 0.2V -1.6 2.4 ------- Vcc=3.0V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL VDR ICCDR tCDR tR PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE VIN CE VIN TEST CONDITIONS Vcc - 0.2V Vcc - 0.2V or VIN Vcc - 0.2V Vcc - 0.2V or VIN 0.2V 0.2V MIN. 1.5 -0 TRC (2) TYP. (1) -0.05 --- MAX. -0.5 --- UNITS V uA ns ns See Retention Waveform 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time R0201-BS616UV2011 3 Revision 2.5 April 2002 BSI LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode BS616UV2011 VDR ≥ 1.5V Vcc VIH Vcc Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L 1333 Ω OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC TEST LOADS AND WAVEFORMS 2V OUTPUT 100PF INCLUDING JIG AND SCOPE 1333 Ω 2V OUTPUT MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY 5PF 2000 Ω INCLUDING JIG AND SCOPE , 2000 Ω FIGURE 1A THEVENIN EQUIVALENT 800 Ω FIGURE 1B OUTPUT 1.2V ALL INPUT PULSES Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Output Disable to Address Change BS616UV2011-70 MIN. TYP. MAX. BS616UV2011-10 MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tAVQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX tRC tAA tACS (1) tBA 70 -(CE) (LB,UB) (CE) (LB,UB) (CE) (LB,UB) ---10 10 10 0 0 0 10 ------------- -70 70 35 35 ---35 35 30 -- 100 ----15 15 15 0 0 0 15 ------------- -100 100 50 50 ---40 40 35 -- tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH NOTE : 1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle. R0201-BS616UV2011 4 Revision 2.5 April 2002 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616UV2011 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t (5) CLZ t BDO t CHZ (5) READ CYCLE3 (1,4) t RC ADDRESS t OE AA t OE CE t OH t OLZ t CLZ (5) t ACS t OHZ (5) (1,5) t CHZ t BA LB,UB t BE D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . t BDO 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616UV2011 Revision 2.5 April 2002 5 BSI AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active BS616UV2011 BS616UV2011-70 MIN. TYP. MAX. BS616UV2011-10 MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WHOX t WC t CW t AS t AW t WP t WR t BW(1) t WHZ t DW t DH t OHZ t OW 70 70 0 70 35 (CE,WE) (LB,UB) 0 30 0 30 0 0 5 ------------- -------30 --30 -- 100 100 0 100 50 0 40 0 40 0 0 10 ------------- -------40 --40 -- NOTE : 1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t WR OE (3) t CW CE (5) (11) t BW LB,UB t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t t DW DH D IN R0201-BS616UV2011 6 Revision 2.5 April 2002 BSI WRITE CYCLE2 (1,6) BS616UV2011 t WC ADDRESS t CW CE (5) (11) t BW LB,UB t AW WE t WR t WP (2) (3) t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616UV2011 7 Revision 2.5 April 2002 BSI ORDERING INFORMATION BS616UV2011 BS616UV2011 XX -- Y Y SPEED 70: 70ns 10: 100ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP 2 - 44 PIN T: TSOP 1 - 48 PIN A: BGA - 48 PIN(6x8mm) D: DICE PACKAGE DIMENSIONS TSOP2-44 R0201-BS616UV2011 8 Revision 2.5 April 2002 BSI PACKAGE DIMENSIONS 12 (2X) HD C L 1 48 12 (2X) UNIT SYMBOL BS616UV2011 24 25 "A" D Seating Plane y 12 (2x) A A1 A2 b b1 c c1 D E e HD L L1 y INCH 0.0433 0.004 0.004 0.002 0.039 0.002 0.009 0.002 0.008 0.001 0.004 ~ 0.008 0.004 ~ 0.006 0.645 0.004 0.472 0.004 0.020 0.004 0.708 0.008 0.0236 0.006 0.0315 0.004 0.004 Max. 0~ 8 MM 1.10 0.10 0.10 0.05 1.00 0.05 0.22 0.05 0.20 0.03 0.10 ~ 0.21 0.10 ~ 0.16 16.40 0.10 12.00 0.10 0.50 0.10 18.00 0.20 0.60 0.15 0.80 0.10 0.1 Max. 0~ 8 b E e A A2 GAUGE PLANE A 0.254 A1 24 25 SEATING PLANE 12 (2x) WITH PLATING A L L1 b "A" DETAIL VIEW c c1 BASE METAL b1 SECTION A-A 1 48 TSOP1-48PIN A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 NC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 47 46 A16 NC VSS IO15 IO7 IO14 IO6 IO13 IO5 IO12 IO4 VCC IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 /OE VSS /CE A0 9 10 13 16 17 Pkg Type : 48TSOP(I)-12x18mm 37 27 24 25 0 R0201-BS616UV2011 9 Revision 2.5 April 2002 BSI PACKAGE DIMENSIONS (continued) NOTES: BS616UV2011 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 48 mini-BGA (6 x 8) E1 R0201-BS616UV2011 10 Revision 2.5 April 2002 BSI REVISION HISTORY Revision 2.2 2.3 2.4 2.5 BS616UV2011 Description 2001 Data Sheet release Modify Standby Current (Typ. and Max.) Date Apr. 15, 2001 Jun. 29, 2001 Note Modify CSP Pin Configuration Sep. 12, 2001 Pin number : E3 “ VSS ” rename to “ N.C. “ Modify some AC parameters April,12,2002 R0201-BS616UV2011 11 Revision 2.5 April 2002