BS616UV2019AI85

Ultra Low Power CMOS SRAM 128K X 16 bit Pb-Free and Green package materials are compliant to RoHS BS616UV2019 n FEATURES Ÿ Wide VCC low operation voltage : C-grade : 1.8V ~ 3.6V I-grade : 1.9V ~ 3.6V Ÿ Ultra low power consumption : VCC = 2.0V Operation current : 10mA (Max.) at 85ns 1mA (Max.) at 1MHz Standby current : 0.2uA (Typ.) at 25 OC VCC = 3.0V Operation current : 13mA (Max.) at 85ns 2mA (Max.) at 1MHz Standby current : 0.3uA (Typ.) at 25 OC Ÿ High speed access time : -85 85ns (Max.) -10 100ns (Max.) Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ I/O Configuration x8/x16 selectable by LB and UB pin. Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V n DESCRIPTION The BS616UV2019 is a high performance, ultra low power CMOS Static Random Access Memory organized as 131,072 by 16 bits and operates form a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.2uA at 2.0V/25OC and maximum access time of 85ns at 85OC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616UV2019 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV2019 is available in DICE form, JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY BS616UV2019DC BS616UV2019AC BS616UV2019TC BS616UV2019AI BS616UV2019TI OPERATING TEMPERATURE STANDBY (ICCSB1, Max) Operating (ICC, Max) PKG TYPE VCC=2.0V fMax. VCC=3.0V VCC=2.0V VCC=3.0V 1MHz fMax. 1MHz Commercial +0OC to +70OC Industrial -40OC to +85OC DICE 3.0uA 2.0uA 1.5mA 11mA 0.8mA 8mA BGA-48-0608 TSOP I-48 BGA-48-0608 TSOP I-48 5.0uA 3.0uA 2.0mA 13mA 1.0mA 10mA n PIN CONFIGURATIONS A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 NC UB LB NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 NC 2 OE UB D10 D11 D12 D13 NC A8 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6 NC D0 D2 VCC VSS D6 D7 NC A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0 n BLOCK DIAGRAM A6 A7 A8 A9 A10 A11 A15 A14 A13 A12 Address Input Buffer 10 Row Decoder 1024 Memory Array 1024 x 2048 BS616UV2019TC BS616UV2019TI 2048 DQ0 . . . . . . DQ15 16 . . . . . . 16 Data Input Buffer 16 128 Column Decoder 7 Control Address Input Buffer 16 Column I/O Write Driver Sense Amp 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE D1 D3 D4 D5 WE A11 Data Output Buffer CE2,CE WE OE UB LB VCC VSS A16 A0 A1 A2 A3 A4 A5 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS616UV2019 1 Revision 1.3 May. 2006 BS616UV2019 n PIN DESCRIPTIONS Name A0-A16 Address Input CE Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input Function These 17 address inputs select one of the 262,144 x 16 bit in the RAM CE is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. (48B BGA ignore CE2 pin) The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. Lower byte and upper byte data input/output control pins. OE Output Enable Input LB and UB Data Byte Control Input DQ0-DQ15 Data Input/Output Ports VCC VSS 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground n TRUTH TABLE MODE Chip De-selected (Power Down) CE H X X L CE2(1) X L X H H WE X X X H H OE X X X H H LB X X H L X L UB X X H X L L L H L L H DQ0~DQ7 DQ8~DQ15 VCC CURRENT High Z High Z High Z High Z High Z DOUT High Z DOUT DIN X DIN High Z High Z High Z High Z High Z DOUT DOUT High Z DIN DIN X ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC ICC Output Disabled L Read L H H L H L L Write L H L X H L 1. 48BGA ignore CE2 condition. 2. H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BS616UV2019 2 Revision 1.3 May. 2006 BS616UV2019 n ABSOLUTE MAXIMUM RATINGS SYMBOL VTERM TBIAS TSTG PT IOUT (1) n OPERATING RANGE UNITS V O PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5(2) to 5.0 -40 to +125 -60 to +150 1.0 20 RANG Commercial Industrial AMBIENT TEMPERATURE 0OC to + 70OC -40OC to + 85OC VCC 1.8V ~ 3.6V 1.9V ~ 3.6V C C O W mA n CAPACITANCE (1) (TA = 25 C, f = 1.0MHz) O SYMBOL PAMAMETER CONDITIONS MAX. UNITS CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. 1. This parameter is guaranteed and not 100% tested. n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER Power Supply VCC=2.0V O O TEST CONDITIONS MIN. 1.9 -0.3(2) 1.4 2.2 -- TYP.(1) -- MAX. 3.6 0.6 0.8 UNITS V Input Low Voltage VCC=3.0V VCC=2.0V -- V Input High Voltage VCC=3.0V -- VCC+0.3(3) V Input Leakage Current VIN = 0V to VCC CE= VIH or CE2(7) = VIL VI/O = 0V to V CC, CE= VIH or CE2(7) = VIL or OE = VIH V CC = Max, IOL = 0.1mA V CC = Max, IOL = 2.0mA VCC=2.0V -- 1 uA Output Leakage Current -- -- 1 0.2 0.4 uA Output Low Voltage -VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V -- V Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current – TTL V CC = Min, IOH = -0.1mA V CC = Min, IOH = -1.0mA CE = VIL and CE2(7) = VIH, IIO = 0mA, f = FMAX(4) CE = VIL and CE2(7) = VIH, IIO = 0mA, f = 1MHz CE = VIH or CE2(7) = VIL, IIO = 0mA CE≧ VCC-0.2V or CE2(7)≦ 0.2V, VIN≧ V CC-0.2V or VIN≦ 0.2V 1.6 2.4 -- -- -10 13 V -- mA VCC=3.0V VCC=2.0V -VCC=3.0V VCC=2.0V -- 1.0 2.0 mA -VCC=3.0V VCC=2.0V -0.2 0.3 0.5 1.0 mA Standby Current – CMOS -VCC=3.0V 3.0 5.0 uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICC (MAX.) is 8mA/11mA at VCC=2.0V/3.0V and TA=70OC. 6. ICCSB1(MAX.) is 2.0uA/3.0uA at VCC=2.0V/3.0V and TA=70OC. 7. 48B BGA ignore CE2 condition. R0201-BS616UV2019 3 Revision 1.3 May. 2006 BS616UV2019 n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL VDR ICCDR (3) O O PARAMETER VCC for Data Retention TEST CONDITIONS CE≧VCC-0.2V or CE2(4)≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE≧VCC-0.2V or CE2(4)≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V MIN. 1.5 TYP. (1) -- MAX. -- UNITS V Data Retention Current Chip Deselect to Data Retention Time -- 0.1 1.0 uA tCDR tR 0 See Retention Waveform tRC (2) -- -- ns Operation Recovery Time -- -- ns 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 0.7uA at TA=70OC. 4. 48B BGA ignore CE2 condition n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled) Data Retention Mode VCC VIH VCC VDR≧1.5V VCC tCDR CE≧VCC - 0.2V tR VIH CE n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) Data Retention Mode VCC VDR≧1.5V VCC tCDR tR CE2≦0.2V CE2 VIL VIL n AC TEST CONDITIONS (Test Load and Input/Output Reference) n KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “L” TO “H” CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE “OFF” STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 10% 90% 90% 10% →← Rise Time: 1V/ns →← Fall Time: 1V/ns 1. Including jig and scope capacitance. R0201-BS616UV2019 4 Revision 1.3 May. 2006 BS616UV2019 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 85ns CYCLE TIME : 100ns (VCC=1.9~3.6V) (VCC=1.9~3.6V) MIN. TYP. M AX. MIN. TYP. M AX. 85 -(CE) (CE2) (LB, UB) ----(CE) (CE2) (LB, UB) 15 15 15 15 (CE) (CE2) ----15 ----------------85 85 85 85 40 ----35 35 35 30 -100 -----15 15 15 15 ----15 ----------------100 100 100 100 50 ----40 40 40 35 -O O DESCRIPTION UNITS tAVAX tAVQX tELQV1 tELQV2 tBLQV tGLQV tELQX1 tELQX2 tBLQX tGLQX tEHQZ1 tEHQZ2 tBHQZ tGHQZ tAVQX tRC tAA tACS1 tACS2 tBA tOE tCLZ1 tCLZ2 tBE tOLZ tCHZ1 tCHZ2 tBDO tOHZ tOH Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Chip Select to Output High Z ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Byte Control to Output High Z (LB, UB) Output Enable to Output High Z Data Hold from Address Change n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH DOUT tAA tOH R0201-BS616UV2019 5 Revision 1.3 May. 2006 BS616UV2019 READ CYCLE 2 (1,3,4) CE tACS1 CE2 tCLZ DOUT (6) tACS2 (5,6) tCHZ (5, 6) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE tOLZ tACS1 CE2 tCLZ LB, UB tOHZ (5) tOH tACS2(6) (5,6) tCHZ tBA tBE (1,5,6) tBDO DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 6. 48B BGA ignore this parameters related to CE2. R0201-BS616UV2019 6 Revision 1.3 May. 2006 BS616UV2019 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 85ns (VCC=1.9~3.6V) MIN. Write Cycle Time Address Set up Time Address Valid to End of Write Chip Select to End of Write Data Byte Control to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE, WE) (CE2) (LB, UB) 85 0 85 85 50 40 0 0 -35 0 -10 TYP. -------------M AX. --------35 --35 -CYCLE TIME : 100ns (VCC=1.9~3.6V) MIN. 100 0 100 100 70 50 0 0 -40 0 -10 TYP. -------------M AX. --------40 --40 -ns ns ns ns ns ns ns ns ns ns ns ns ns O O DESCRIPTION UNITS tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX1 tWHAX2 tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tAS tAW tCW tBW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS OE tCW CE (5) (11) tWR1 (3) CE2 (5,12) tCW LB, UB tAW WE tAS tOHZ DOUT (4,10) (11) tBW tWR2 (3) tWP (2) tDH tDW DIN R0201-BS616UV2019 7 Revision 1.3 May. 2006 BS616UV2019 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW (11) CE (5) CE2 (5,12) LB, UB (5) tBW tAW (3) WE tAS tWHZ DOUT (4,10) tWP (2) tWR tOW tDW tDH (8,9) (7) (8) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low or CE2 going high to the end of write. 12. 48B BGA ignore this parameters related to CE2. R0201-BS616UV2019 8 Revision 1.3 May. 2006 BS616UV2019 n ORDERING INFORMATION BS616UV2019 X X Z YY SPEED 85: 85ns 10: 100ns PKG M ATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE A: BGA-48-0608 T: TSOP I-48 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS HD 12°(2X) 12°(2X) UNIT SYMBO L INCH 0.0433±0.004 0.004±0.002 0.039±0.002 0.009±0.002 0.008±0.001 0.004 ~ 0.008 0.004 ~ 0.006 0.645±0.004 0.472±0.004 0.020±0.004 0.708±0.008 0.0236±0.006 0.0315± 0.004 Max. 0°~8° MM 1.10±0.10 0.10±0.05 1.00±0.05 0.22±0.05 0.20±0.03 0.10 ~ 0.21 0.10 ~ 0.16 16.40±0.10 11.80±0.10 0.50±0.10 18.00±0.20 0.60±0.15 0.80±0.10 0.1 Max. 0°~8° 1 4 8 e b E 2 4 2 5 "A" D Seating Plane 12°(2x) y A A1 A2 b b1 c c1 D E e HD L L1 y θ A A2 GAUGE PLANE A A1 2 4 2 5 SEATING PLANE 12°(2x) WITH PLATING A L L1 θ b "A" DETAIL VIEW cc 1 BASE METAL b1 SECTION A-A 1 4 8 TSOP I-48 Pin R0201-BS616UV2019 9 Revision 1.3 May. 2006 BS616UV2019 n PACKAGE DIMENSIONS (continued) 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.2 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 48 mini-BGA (6 x 8mm) E1 R0201-BS616UV2019 10 Revision 1.3 May. 2006 BS616UV2019 n Revision History Revision No. 1.2 1.3 History Add Icc1 characteristic parameter Change I-grade operation temperature range - from –25OC to –40OC Draft Date Jan. 13, 2006 May. 25, 2006 Remark R0201-BS616UV2019 11 Revision 1.3 May. 2006