BS616UV2019TC-10

BSI FEATURES Ultra Low Power/Voltage CMOS SRAM 128K X 16 bit BS616UV2019 • Wide Vcc operation voltage : C-grade: 1.8V~3.6V I-grade: 1.9V~3.6V (Vcc_min.=1.65V at 25oC) • Ultra low power consumption : Vcc = 2.0V C-grade: 8mA (Max.) operating current I -grade: 10mA (Max.) operating current 0.20uA (Typ.) CMOS standby current Vcc = 3.0V C-grade: 11mA (Max.) operating current I -grade: 13mA (Max.) operating current 0.30uA (Typ.) CMOS standby current • High speed access time : -85 85ns (Max.) -10 100ns (Max.) • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin • Data retention supply voltage as low as 1.0V DESCRIPTION The BS616UV2019 is a high performance, ultra low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.2uA at 2.0V /25oC and maximum access time of 85ns at 85oC. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable(OE) and three-state output drivers. The BS616UV2019 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV2019 is available in DICE form, JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package. PRODUCT FAMILY PRODUCT FAMILY BS616UV2019DC BS616UV2019TC BS616UV2019AC BS616UV2019DI BS616UV2019TI BS616UV2019AI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) C-grade:1.8~3.6V I-grade:1.9~3.6V ( ICCSB1, Max ) Vcc=3.0V POWER DISSIPATION STANDBY Operating ( ICC, Max ) Vcc=2.0V Vcc=3.0V Vcc=2.0V PKG TYPE DICE TSOP1-48 BGA-48-0608 DICE TSOP1-48 BGA-48-0608 +0 O C to +70 O C -40 O C to +85 O C 1.8V ~3.6V 1.9V ~ 3.6V 85/100 85/100 3.0uA 2.0uA 11mA 8mA 10mA 5.0uA 3.0uA 13mA PIN CONFIGURATIONS A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 NC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 47 46 A16 NC VSS IO15 IO7 IO14 IO6 IO13 IO5 IO12 IO4 VCC IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 /OE VSS /CE A0 BLOCK DIAGRAM A8 A13 A15 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 9 10 13 16 17 BS616UV2019TC BS616UV2019TI 37 2048 DQ0 16 Data Input Buffer 16 Column I/O 27 24 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 N.C. 2 OE UB D10 D11 D12 D13 N.C. A8 3 A0 A3 A5 N.C. N.C. A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE D1 D3 D4 D5 WE A11 6 N.C. D0 D2 VCC VSS D6 D7 N.C. 25 . . . . DQ15 . . . . Write Driver Sense Amp 128 Column Decoder 16 Data Output 16 Buffer CE2 ,CE WE OE UB LB Vcc Gnd Control 14 Address Input Buffer A11 A9 A3 A2 A1 A0 A10 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616UV2019 1 Revision 1.1 Jan. 2004 BSI PIN DESCRIPTIONS BS616UV2019 Name A0-A16 Address Input CE Chip Enable 1 Input CE2 Chip Enable 2 Input Function These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. (48B BGA ignore CE2 pin) The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. WE Write Enable Input OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read CE H X X L L CE2 (1) X L X H H WE X X X H H OE X X X H L LB X X H X L H L L Write L H L X H L 1. 48B BGA ignore CE2 condition. UB X X H X L L H L L H D0~D7 High Z High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , I CCSB1 ICCSB , I CCSB1 ICCSB , I CCSB1 ICC ICC ICC ICC ICC ICC ICC R0201-BS616UV2019 2 Revision 1.1 Jan. 2004 BSI ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current BS616UV2019 OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 O C to +85 O C Vcc 1.8V ~ 3.6V 1.9V ~ 3.6V C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC ICCSB ICCSB1 (5) PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current 　TTL TEST CONDITIONS Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V MIN. TYP. -0.3 1.4 2.0 ---Vcc-0.2 2.4 ------(6) (1) MAX. 0.6 0.8 Vcc+0.3 1 1 0.2 0.4 -10 13 0.1 0.5 3.0 5.0 UNITS V V uA uA V V mA mA uA ----------0.20 0.30 Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH , or CE2(4) = VIL, or OE = VIH, VI/O = 0V to VCC Vcc=2.0V I OL = 0.1mA ; Vcc=Max Vcc=3.0V I OL = 2.0mA ; Vcc=Max IOH = -0.1mA ; Vcc=Min IOH = -1.0mA ; Vcc=Min CE = VIL CE2 = V (4) IH Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V ,IDQ = 0mA, F = Fmax(3) CE = VIH (4) , IDQ = 0mA or CE2 = VIL CE ≧Vcc-0.2V, or CE2 ≦ 0.2V,(4) Standby Current　CMOS VIN ≧Vcc - 0.2V or VIN ≦ 0.2V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. 4. 48B BGA ignore CE2 condition. 5.IccsB1 is 2.0uA/3.0uA at Vcc=2.0V/3.0V and TA=70oC. 6. VIL = -1.5V for pulse width less than 30ns DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR ICCDR tCDR tR (4) PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time TEST CONDITIONS CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3) VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3) VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V See Retention Waveform MIN. 1.0 -0 TRC (2) TYP. (1) -0.1 --- MAX. -1.0 --- UNITS V uA ns ns 1. Vcc = 1.0V, TA = + 25OC 3. 48B BGA ignore CE2 condition. R0201-BS616UV2019 2. tRC = Read Cycle Time 4. IccDR is 0.7uA at TA=70oC. 3 Revision 1.1 Jan. 2004 BSI LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode BS616UV2019 VDR ≥ 1.0V Vcc VIH Vcc Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CL = 100pF+1TTL CL = 30pF+1TTL , AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE ( 48B BGA ignore CE2 condition) JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 100ns (Vcc = 1.9~3.6V) CYCLE TIME : 85ns (Vcc = 1.9~3.6V) MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns MIN. TYP. MAX. tAVAX tAVQV tELQV tBA tGLQV t E1LQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX tRC tAA tACS1 , 2 tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH 100 -(CE,CE2) (LB,UB) (CE,CE2) (LB,UB) (CE,CE2) (LB,UB) ---15 15 15 ---15 ------------- -100 100 50 50 ---40 40 35 -- 85 ----15 15 15 ---15 ------------- -85 85 40 40 ---35 35 30 -- NOTE : 1. tBA is 50ns/40ns (@speed=100ns/85ns) with address toggle. ; tBA is 100ns/85ns (@speed=100ns/85ns) without address toggle. R0201-BS616UV2019 4 Revision 1.1 Jan. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS616UV2019 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE2 tACS2(6) t ACS1 CE t D OUT (5,6) CLZ t CHZ(5,6) READ CYCLE3 (1,4) ADDRESS t RC t OE AA t CE2 OE t OH t t t t (5,6) CLZ ACS2(6) CE OLZ ACS1 t t OHZ CHZ (5) (1,5,6) LB,UB t BE t t BA BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. 6. 48B BGA ignore this parameters related to CE2 . R0201-BS616UV2019 5 Revision 1.1 Jan. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE ( 48B BGA ignore CE2 condition) JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (Vcc = 1.9~3.6V) BS616UV2019 CYCLE TIME : 100ns MIN. TYP. MAX. CYCLE TIME : 85ns (Vcc = 1.9~3.6V) MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW 100 (CE,CE2) 100 0 100 50 (CE,CE2,WE) (LB,UB) 0 40 -40 0 -10 ------------- -------40 --40 -- 85 85 0 85 40 0 35 -35 0 -10 ------------- -------35 --35 -- NOTE : 1. tBW is 40ns/35ns (@speed=100ns/85ns) with address toggle. ; tBW is 100ns/85ns (@speed=100ns/85ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC t WR OE (3) CE2 (5,12) t CW CE (5) (11) t LB,UB (5) BW t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS616UV2019 6 Revision 1.1 Jan. 2004 BSI WRITE CYCLE2 (1,6) BS616UV2019 t WC ADDRESS CE2 (5,12) (11) CE (5) t t CW BW LB,UB (5) t WE AW t WP t WR (3) (2) t AS (4,10) t WHZ D OUT t t DW t OW (7) (8) DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE going low to the end of write. 12. 48B BGA ignore this parameters related to CE2 . R0201-BS616UV2019 7 Revision 1.1 Jan. 2004 BSI ORDERING INFORMATION BS616UV2019 BS616UV2019 X X Z YY SPEED 85: 85ns 10: 100ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE T: TSOP1-48 A: BGA-48-0608 D: DICE Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 48 mini-BGA (6 x 8) R0201-BS616UV2019 E1 8 Revision 1.1 Jan. 2004 BSI PACKAGE DIMENSIONS C L 1 48 12°(2X) 12°(2X) HD UNIT SYMBOL b E e BS616UV2019 INCH 0.0433±0.004 A A1 0.004±0.002 A2 0.039±0.002 b 0.009±0.002 b1 0.008±0.001 c 0.004 ~ 0.008 c1 0.004 ~ 0.006 D 0.645±0.004 E 0.472±0.004 0.020±0.004 e HD 0.708±0.008 L 0.0236±0.006 L1 0.0315±0.004 y 0.004 Max. 0°~ 8° θ MM 1.10±0.10 0.10±0.05 1.00±0.05 0.22±0.05 0.20±0.03 0.10 ~ 0.21 0.10 ~ 0.16 16.40±0.10 11.80±0.10 0.50±0.10 18.00±0.20 0.60±0.15 0.80±0.10 0.1 Max. 0°~ 8° 24 25 "A" D Seating Plane y 12°(2x) A A2 GAUGE PLANE A 0.254 A1 24 25 SEATING PLANE 12°(2x) WITH PLATING A L L1 b "A" DETAIL VIEW c c1 BASE METAL b1 SECTION A-A 1 48 TSOP1-48PIN 0 R0201-BS616UV2019 9 Revision 1.1 Jan. 2004