BS62LV2005

BSI FEATURES Very Low Power/Voltage CMOS SRAM 256K X 8 bit DESCRIPTION BS62LV2005 • Wide Vcc operation voltage : 4.5V ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns(Max.) at Vcc = 5.0V -55 55ns(Max.) at Vcc = 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2, CE1, and OE options The BS62LV2005 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.6uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2005 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2005 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP. PRODUCT FAMILY PRODUCT FAMILY BS62LV2005TC BS62LV2005STC BS62LV2005SC BS62LV2005TI BS62LV2005STI BS62LV2005SI OPERATING TEMPERATURE Vcc RANGE SPEED (ns) Vcc=5.0V POWER DISSIPATION STANDBY Operating (ICCSB1 , Max) (ICC , Max) PKG TYPE TSOP-32 STSOP-32 SOP -32 TSOP-32 STSOP-32 SOP -32 Vcc=5.0V Vcc=5.0V +0 O C to +70O C -40 O C to +85O C 4.5V ~ 5.5V 55 / 70 6uA 35mA 4.5V ~ 5.5V 55 / 70 25uA 40mA PIN CONFIGURATIONS A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BLOCK DIAGRAM OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A13 A17 A15 A16 A14 A12 A7 A6 A5 A4 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62LV2005 • BS62LV2005TC BS62LV2005STC BS62LV2005TI BS62LV2005STI 1 2 3 4 5 6 7 BS62LV2005SC 8 BS62LV2005SI 9 10 11 12 13 14 15 16 Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 Control Address Input Buffer 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 • 8 Data Output Buffer 8 CE1 CE2 WE OE Vdd Gnd A11 A9 A8 A3 A2 A1 A0 A10 1 Revision 2.4 April 2002 BSI PIN DESCRIPTIONS BS62LV2005 Function These 18 address inputs select one of the 262,144 x 8-bit words in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. Name A0-A17 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports Vcc Gnd These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT Not selected (Power Down) Output Disabled Read Write X X H H L H X L L L X L H H H X X H L X High Z High Z D OUT D IN I CCSB, I CCSB1 I CC I CC I CC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 C to +70 C -40 C to +85 C O O O O Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL CIN PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VIN=0V VI/O=0V 6 8 pF pF CDQ 1. This parameter is guaranteed and not tested. R0201-BS62LV2005 R0201-BS62LV2005 2 Revision 2.4 April 2002 BSI DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 BS62LV2005 TEST CONDITIONS Vcc=5.0V PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS MIN. -0.5 2.2 -- TYP. (1) --------0.6 MAX. 0.8 Vcc+0.2 1 1 0.4 -35 2 6 UNITS V V uA uA V V mA mA uA Vcc=5.0V Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1= V , CE2= V or OE = VIH, VI/O = 0V to Vcc IH IL, -Vcc=5.0V Vcc=5.0V Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE1 = VIL, or CE2 = VIH, IDQ = 0mA, F = Fmax(3) CE1 = VIH, or CE2 = VIL, (3) IDQ = 0mA, F = Fmax CE1 Vcc-0.2V, CE2 0.2V, VIN Vcc-0.2V or VIN 0.2V -2.4 ---- Vcc=5.0V Vcc=5.0V Vcc=5.0V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL VDR ICCDR tCDR tR PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE1 VIN CE1 VIN TEST CONDITIONS Vcc - 0.2V, CE2 Vcc - 0.2V or VIN Vcc - 0.2V, CE2 Vcc - 0.2V or VIN 0.2V, 0.2V 0.2V, 0.2V MIN. 1.5 -0 TRC (2) TYP. (1) -0.01 --- MAX. -1 --- UNITS V uA ns ns See Retention Waveform 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode VDR ≥ 1.5V Vcc VIH Vcc Vcc t CDR CE1 ≥ Vcc - 0.2V tR VIH CE1 LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc Vcc VDR 1.5V Vcc t CDR tR CE2 0.2V CE2 R0201-BS62LV2005 VIL VIL 3 Revision 2.4 April 2002 BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc WAVEFORM INPUTS BS62LV2005 KEY TO SWITCHING WAVEFORMS OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MUST BE STEADY MAY CHANGE FROM H TO L 1928 Ω AC TEST LOADS AND WAVEFORMS 5.0V OUTPUT 100PF INCLUDING JIG AND SCOPE 1928 Ω 5.0V OUTPUT MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY , 5PF 1020Ω INCLUDING JIG AND SCOPE 1020 Ω FIGURE 1A THEVENIN EQUIVALENT 667 Ω ALL INPUT PULSES FIGURE 1B OUTPUT 1.73V Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change (CE1) (CE2) (CE1) (CE2) (CE1) (CE2) BS62LV2005-55 MIN. TYP. MAX. BS62LV2005-70 MIN. TYP. MAX. UNIT tAVAX tAVQV tE1LQV tE2HOV tGLQV tE1LQX tE2HOX tGLQX tE1HQZ tE2HQZ tGHQZ tAXOX tRC tAA t ACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH 55 ----10 10 10 0 0 0 10 ------------- -55 55 55 30 ---30 30 25 -- 70 ----10 10 10 0 0 0 10 ------------- -70 70 70 35 ---35 35 30 -- ns ns ns ns ns ns ns ns ns ns ns ns R0201-BS62LV2005 R0201-BS62LV2005 4 Revision 2.4 April 2002 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS62LV2005 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE1 t ACS1 CE2 t t (5) CLZ ACS2 t CHZ1, t (5) CHZ2 D OUT READ CYCLE3 (1,4) t RC ADDRESS t OE AA t OE CE1 t OH t OLZ t CLZ1 (5) t ACS1 t OHZ (5) (1,5) t CHZ1 CE2 t ACS2 t (5) CLZ2 t CHZ2 (2,5) D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62LV2005 R0201-BS62LV2005 5 Revision 2.4 April 2002 BSI AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1 , WE) (CE2) BS62LV2005-55 MIN. TYP. MAX. BS62LV2005 BS62LV2005-70 MIN. TYP. MAX. UNIT tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLOZ tDVWH tWHDX tGHOZ tWHQX tWC tCW tAS tAW tWP t WR1 t WR2 tWHZ tDW tDH tOHZ tOW 55 55 0 55 30 0 0 0 25 0 0 5 ------------- -------25 --25 -- 70 70 0 70 35 0 0 0 30 0 0 5 ------------- -------30 --30 -- ns ns ns ns ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC t WR1 OE (3) t CW CE1 (5) (11) CE2 (5) t WE t CW AW (11) t WR2 (2) (3) t AS (4,10) t WP t OHZ D OUT t t DW DH D IN Revision 2.4 April 2002 R0201-BS62LV2005 R0201-BS62LV2005 6 BSI WRITE CYCLE2 (1,6) BS62LV2005 t WC ADDRESS t CW (5) (11) CE1 CE2 (5) t WE t CW AW (11) t WR2 (2) t WP (3) t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV2005 7 Revision 2.4 April 2002 BSI ORDERING INFORMATION BS62LV2005 BS62LV2005 XX YY SPEED 70: 70ns 55: 55ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) S: SOP PACKAGE DIMENSIONS STSOP - 32 R0201-BS62LV2005 8 Revision 2.4 April 2002 BSI PACKAGE DIMENSIONS (continued) BS62LV2005 TSOP - 32 WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV2005 9 Revision 2.4 April 2002 BSI REVISION HISTORY Revision 2.2 2.3 2.4 BS62LV2005 Description 2001 Data Sheet release Modify Standby Current (Typ. and Max.) Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. Date Apr. 15, 2001 Jun. 29, 2001 April,11,2002 Note R0201-BS62LV2005 10 Revision 2.4 April 2002