BS62LV2006STC

BSI FEATURES Very Low Power/Voltage CMOS SRAM 256K X 8 bit BS62LV2006 • Wide Vcc operation voltage : 2.4V~5.5V • Very low power consumption : Vcc = 3.0V C-grade : 22mA (@55ns) operating current I- grade : 23mA (@55ns) operating current C-grade : 17mA (@70ns) operating current I- grade : 18mA (@70ns) operating current 0.3uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 53mA (@55ns) operating current I- grade : 55mA (@55ns) operating current C-grade : 43mA (@70ns) operating current I- grade : 45mA (@70ns) operating current 1.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2, CE1, and OE options DESCRIPTION The BS62LV2006 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.3uA at 3.0V /25oC and maximum access time of 55ns at 3.0V /85oC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2006 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP. PRODUCT FAMILY PRODUCT FAMILY BS62LV2006DC BS62LV2006TC BS62LV2006STC BS62LV2006SC BS62LV2006DI BS62LV2006TI BS62LV2006STI BS62LV2006SI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) 55ns :3.0~5.5V 70ns :2.7~5.5V ( ICCSB1, Max ) Vcc=3.0V POWER DISSIPATION STANDBY Operating ( ICC, Max ) Vcc=5.0V Vcc=3.0V 70ns Vcc=5.0V 70ns PKG TYPE DICE TSOP-32 STSOP-32 SOP-32 DICE TSOP-32 STSOP-32 SOP-32 +0 O C to +70 O C 2.4V ~5.5V 55/70 3.0uA 10uA 17mA 43mA -40 O C to +85 O C 2.4V ~ 5.5V 55/70 5.0uA 30uA 18mA 45mA PIN CONFIGURATIONS BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A13 A17 A15 A16 A14 A12 A7 A6 A5 A4 • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BS62LV2006TC BS62LV2006STC BS62LV2006TI BS62LV2006STI A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 BS62LV2006SC 8 BS62LV2006SI 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 Control Address Input Buffer 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV2006 • 8 Data Output Buffer 8 CE1 CE2 WE OE Vdd Gnd A11 A9 A8 A3 A2 A1 A0 A10 1 Revision 1.1 Jan. 2004 BSI PIN DESCRIPTIONS BS62LV2006 Function These 18 address inputs select one of the 262,144 x 8-bit words in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. Name A0-A17 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports Vcc Gnd These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT Not selected (Power Down) Output Disabled Read Write X X H H L H X L L L X L H H H X X H L X High Z High Z D OUT D IN I CCSB, I CCSB1 I CC I CC I CC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM TBIAS TSTG PT I OUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 C to +85 C O O Vcc 2.4V ~ 5.5V 2.4V ~ 5.5V C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not 100% tested. R0201-BS62LV2006 2 Revision 1.1 Jan. 2004 BSI DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC (5) ICCSB BS62LV2006 TEST CONDITIONS Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL MIN. TYP. (1) MAX. -0.5 2.0 2.2 --Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V UNITS V V uA uA V V mA mA -----------0.3 1.0 0.8 Vcc+0.3 Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH or CE2=VIL or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2.0mA Vcc = Min, IOH = -1.0mA Vcc=Max,CE1=VIL, CE2=VIH IDQ = 0mA, F = Fmax(2) Vcc = Max, CE1 = VIH or CE2=VIL IDQ = 0mA Vcc = Max, CE1≧Vcc-0.2V or CE2≦0.2V ;VIN≧ Vcc - 0.2V or VIN≦0.2V 70ns 70ns 1 1 0.4 -18 45 0.5 1.0 5 30 -2.4 ------- Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V ICCSB1(4) Standby Current-CMOS Vcc=5.0V uA 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 5. Icc_MAX. is 23mA(@3V) / 55mA(@5V) under 55ns operation. 4. IccsB1_MAX. is 3uA / 10uA at Vcc=3V / 5V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) SYMBOL VDR ICCDR (3) PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time TEST CONDITIONS CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V See Retention Waveform MIN. 1.5 -0 TRC (2) TYP. (1) -0.1 --- MAX. -1.0 --- UNITS V uA ns ns tCDR tR 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.7uA at TA=70oC. LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode VDR ≥ 1.5V Vcc VIH Vcc Vcc t CDR CE1 ≥ Vcc - 0.2V tR VIH CE1 LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc Vcc VDR ≧ 1.5V Vcc t CDR tR CE2 ≦ 0.2V CE2 R0201-BS62LV2006 VIL VIL 3 Revision 1.1 Jan. 2004 BSI AC TEST CONDITIONS (Test Load and Input/Output Reference) BS62LV2006 KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CL = 100pF+1TTL CL = 30pF+1TTL , AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Chip Deselect to Output in High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 55ns (Vcc = 3.0~5.5V) CYCLE TIME : 70ns (Vcc = 2.7~5.5V) MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns MIN. TYP. MAX. tAVAX tAVQV tE1LQV tE2HOV tGLQV t E1LQX tE2HOX tGLQX tE1HQZ tE2HQZ tGHQZ tAXOX tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH 55 -(CE1) (CE2) (CE1) (CE2) (CE1) (CE2) ---10 10 5 ---10 ------------- -55 55 55 30 ---30 30 25 -- 70 ----10 10 5 ---10 ------------- -70 70 70 35 ---35 35 30 -- R0201-BS62LV2006 4 Revision 1.1 Jan. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS62LV2006 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 CE1 (1,3,4) t CE2 (5) CLZ ACS1 t t ACS2 t CHZ1, t (5) CHZ2 D OUT (1,4) READ CYCLE3 t RC ADDRESS t OE AA t CE1 OE t OH t t (5) CLZ1 OLZ t ACS1 t OHZ (5) (1,5) t CHZ1 CE2 t t (5) CLZ2 ACS2 t (2,5) CHZ2 D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV2006 5 Revision 1.1 Jan. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 55ns BS62LV2006 CYCLE TIME : 70ns (Vcc = 2.7~5.5V) DESCRIPTION Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Write recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (Vcc = 3.0~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHOX t WC t CW t AS t AW t WP t WR1 t WR2 t WHZ t DW t DH t OHZ t OW 55 55 0 55 30 (CE1,WE) (CE2) 0 0 -25 0 -5 ------------- -------25 --25 -- 70 70 0 70 35 0 0 -30 0 -5 ------------- -------30 --30 -- SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC t OE (3) W R1 t CW CE1 (5) (11) CE2 (5) t CW t AW (11) t WR2 (2) (3) WE t AS (4,10) t WP t OHZ D OUT t DH t DW D IN R0201-BS62LV2006 6 Revision 1.1 Jan. 2004 BSI WRITE CYCLE2 (1,6) BS62LV2006 t WC ADDRESS (11) (5) t CW CE1 CE2 (5) t WE t CW AW (11) t WR2 (2) t WP (3) t AS (4,10) t WHZ D OUT t t DW t OW (7) (8) DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV2006 7 Revision 1.1 Jan. 2004 BSI ORDERING INFORMATION BS62LV2006 BS62LV2006 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) D: DICE Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS STSOP - 32 R0201-BS62LV2006 8 Revision 1.1 Jan. 2004 BSI PACKAGE DIMENSIONS (continued) BS62LV2006 TSOP - 32 WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV2006 9 Revision 1.1 Jan. 2004