BS62LV2006STCG55

Very Low Power CMOS SRAM 256K X 8 bit Pb-Free and Green package materials are compliant to RoHS BS62LV2006 n FEATURES Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 23mA (Max.) 2mA (Max.) Standby current : 0.1uA (Typ.) VCC = 5.0V Operation current : 55mA (Max.) 10mA (Max.) Standby current : 0.6uA (Typ.) Ÿ High speed access time : -55 55ns (Max.) at VCC : 3.0~5.5V -70 70ns (Max.) at VCC : 2.7~5.5V Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE2, CE1 and OE options Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V at 55ns at 1MHz at 25 OC at 55ns at 1MHz at 25OC n DESCRIPTION The BS62LV2006 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.1uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2006 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP, 8mmx20mm TSOP and 36-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY BS62LV2006DC BS62LV2006HC BS62LV2006SC BS62LV2006STC BS62LV2006TC BS62LV2006HI BS62LV2006SI BS62LV2006STI BS62LV2006TI Industrial -40OC to +85OC 20uA 2.0uA 10mA 30mA 55mA 2mA 10mA 23mA Commercial +0OC to +70OC 6.0uA 0.7uA 9mA 29mA 53mA 1.5mA 9mA 22mA OPERATING TEMPERATURE STANDBY (ICCSB1, Max) Operating (ICC, Max) PKG TYPE VCC=3V 10MHz fMax. VCC=5.0V VCC=3.0V 1MHz VCC=5V 10MHz fMax. 1MHz DICE BGA-36-0608 SOP-32 STSOP-32 TSOP-32 BGA-36-0608 SOP-32 STSOP-32 TSOP-32 n PIN CONFIGURATIONS n BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A7 A12 A14 A16 A17 A15 A11 A8 A9 A13 • BS62LV2006TC BS62LV2006TI BS62LV2006STC BS62LV2006STI 1 2 A1 A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Address Input Buffer 10 Row Decoder 1024 Memory Array 1024 x 2048 2048 DQ0 DQ1 DQ2 DQ3 8 Data Input Buffer 8 256 Column Decoder 8 Control Address Input Buffer 8 Column I/O Write Driver Sense Amp A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 • 3 CE2 4 A3 5 A6 6 A8 BS62LV2006SC BS62LV2006SI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 A A0 DQ4 DQ5 DQ6 DQ7 8 Data Output Buffer B DQ4 A2 WE A4 A7 DQ0 C DQ5 NC A5 DQ1 D VSS VCC E VCC VSS CE2 CE1 WE OE VCC GND F DQ6 NC A17 DQ2 A6 A5 A10 A4 A3 A2 A1 A0 G DQ7 OE CE1 A16 A15 DQ3 H A9 A10 A11 A12 A13 A14 36-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS62LV2006 1 Revision 1.3 May. 2006 BS62LV2006 n PIN DESCRIPTIONS Name A0-A17 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input Function These 18 address inputs select one of the 262,144 x 8-bit in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. There 8 bi-directional ports are used to read data from or write data into the RAM. OE Output Enable Input DQ0-DQ7 Data Input/Output Ports VCC GND Power Supply Ground n TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write CE1 H X L L L CE2 X L H H H WE X X H H L OE X I/O OPERATION High Z VCC CURRENT ICCSB, ICCSB1 ICC ICC ICC X H L X High Z DOUT DIN n ABSOLUTE MAXIMUM RATINGS SYMBOL VTERM TBIAS TSTG PT IOUT (1) n OPERATING RANGE UNITS V O PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5(2) to 7.0 -40 to +125 -60 to +150 1.0 20 RANG Commercial Industrial AMBIENT TEMPERATURE 0OC to + 70OC -40OC to + 85OC VCC 2.4V ~ 5.5V 2.4V ~ 5.5V C C O W mA n CAPACITANCE (1) (TA = 25 C, f = 1.0MHz) O SYMBOL PAMAMETER CONDITIONS MAX. UNITS CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV2006 1. This parameter is guaranteed and not 100% tested. 2 Revision 1.3 May. 2006 BS62LV2006 n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER Power Supply Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current – TTL Standby Current – CMOS VCC = Max, VIN = 0V to VCC V CC = Max, CE1= VIH, CE2= VIL, or OE = VIH, V I/O = 0V to V CC V CC = Max, IOL = 2.0mA V CC = Min, IOH = -1.0mA CE1 = VIL, CE2 = VIH, IDQ = 0mA, f = FMAX(4) CE1 = VIL, CE2 = VIH, IDQ = 0mA, f = 1MHz CE1 = VIH, or CE2 = VIL, IDQ = 0mA CE1≧ VCC-0.2V or CE2≦ 0.2V, VIN≧ V CC-0.2V or VIN≦ 0.2V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V O O TEST CONDITIONS MIN. 2.4 -0.5(2) 2.2 ---2.4 --------- TYP.(1) -------------0.1 0.6 MAX. 5.5 0.8 VCC+0.3(3) 1 1 0.4 -23 55 2 10 0.5 1.0 2.0 20 UNITS V V V UA UA V V mA mA mA uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICC (MAX.) is 22mA/53mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 0.7uA/6.0uA at VCC=3.0V/5.0V and TA=70OC. n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL VDR ICCDR(3) tCDR tR PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time O O TEST CONDITIONS CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V MIN. 1.5 -0 TYP. (1) -0.05 --- MAX. -1.0 --- UNITS V uA ns ns See Retention Waveform tRC (2) 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCRD(Max.) is 0.5uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled) Data Retention Mode VDR≧1.5V VCC VIH VCC VCC tCDR CE1≧VCC - 0.2V tR VIH CE1 R0201-BS62LV2006 3 Revision 1.3 May. 2006 BS62LV2006 n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) Data Retention Mode VCC VCC VDR≧1.5V VCC tCDR tR CE2≦0.2V CE2 VIL VIL n AC TEST CONDITIONS (Test Load and Input/Output Reference) n KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “L” TO “H” CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE “OFF” STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 10% 90% 90% 10% →← Rise Time : 1V/ns →← Fall Time : 1V/ns 1. Including jig and scope capacitance. n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. M AX. 55 -(CE1) (CE2) ---(CE1) (CE2) 10 10 5 (CE1) (CE2) ---10 -------------55 55 55 30 ---30 30 25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. M AX. 70 ----10 10 5 ---10 -------------70 70 70 35 ---35 35 30 -- O O DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Chip Select to Output High Z Output Enable to Output High Z Data Hold from Address Change UNITS ns ns ns ns ns ns ns ns ns ns ns ns tAVAX tAVQX tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAVQX tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH R0201-BS62LV2006 4 Revision 1.3 May. 2006 BS62LV2006 n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH DOUT tAA tOH READ CYCLE 2 CE1 (1,3,4) tACS1 CE2 tCLZ DOUT (5) tACS2 tCHZ1, tCHZ2 (5) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE1 tCLZ1 CE2 tCLZ2 DOUT (5) (5) tOH tOLZ tACS1 tOHZ tCHZ1 (5) (1,5) tACS2 tCHZ2 (2,5) NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS62LV2006 5 Revision 1.3 May. 2006 BS62LV2006 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1, WE) (CE2) 55 55 0 55 30 0 0 -25 0 -5 TYP. ------------M AX. -------25 --25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. 70 70 0 70 35 0 0 -30 0 -5 TYP. ------------M AX. -------30 --30 -ns ns ns ns ns ns ns ns ns ns ns ns O O DESCRIPTION UNITS tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tCW tAS tAW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1 OE tCW CE1 (5) (11) (3) CE2 (5) tAW WE tAS tOHZ DOUT (4,10) tCW (11) tWR2 (2) (3) tWP tDH tDW DIN R0201-BS62LV2006 6 Revision 1.3 May. 2006 BS62LV2006 WRITE CYCLE 2 ADDRESS tCW (11) (1,6) tWC CE1 (5) CE2 (5) tAW WE tAS tWHZ DOUT (4,10) tCW (11) (2) tWP tWR2 (3) tOW tDW tDH (8,9) (7) (8) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV2006 7 Revision 1.3 May. 2006 BS62LV2006 n ORDERING INFORMATION BS62LV2006 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE H: BGA-36-0608 S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS W ITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV2006 8 Revision 1.3 May. 2006 BS62LV2006 n PACKAGE DIMENSIONS (continued) n STSOP - 32 TSOP - 32 R0201-BS62LV2006 9 Revision 1.3 May. 2006 BS62LV2006 PACKAGE DIMENSIONS (continued) NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.2 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 36 mini-BGA (6 x 8mm) E1 R0201-BS62LV2006 10 Revision 1.3 May. 2006 BS62LV2006 n Revision History Revision No. 1.2 History Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 30uA to 20uA at 5.0V 5.0uA to 2.0uA at 3.0V C-grade from 10uA to 6.0uA at 5.0V 3.0uA to 0.7uA at 3.0V Change I-grade operation temperature range - from –25OC to –40OC Draft Date Jan. 13, 2006 Remark 1.3 May. 25, 2006 R0201-BS62LV2006 11 Revision 1.3 May. 2006