BS62LV256DC

BSI FEATURES Very Low Power/Voltage CMOS SRAM 32K X 8 bit DESCRIPTION BS62LV256 • Wide Vcc operation voltage : 2.4V ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.01uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.4uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc=3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options The BS62LV256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.01uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable (OE) and three-state output drivers. The BS62LV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV256 is available in the DICE form, JEDEC standard 28pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm TSOP (normal type). PRODUCT FAMILY PRODUCT FAMILY BS62LV256SC BS62LV256TC BS62LV256PC BS62LV256JC BS62LV256DC BS62LV256SI BS62LV256TI BS62LV256PI BS62LV256JI BS62LV256DI OPERATING TEMPERATURE Vcc RANGE SPEED (ns) Vcc= 3.0V POWER DISSIPATION STANDBY Operating (ICCSB1, Max) Vcc= Vcc= 5.0V 3.0V (ICC, Max) Vcc= Vcc= 5.0V 3.0V PKG TYPE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE 0 O C to +70 O C 2.4V ~ 5.5V 70 1uA 0.2uA 35mA 20mA -40 C to +85 C O O 2.4V ~ 5.5V 70 2uA 0.4uA 40mA 25mA PIN CONFIGURATIONS BLOCK DIAGRAM 28 27 26 25 24 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 A5 A6 A7 A12 A14 A13 A8 A9 A11 512 Column I/O Write Driver Sense Amp 64 Column Decoder 12 CE WE OE Vdd Gnd A4 A3 A2 A1 A0 A10 Control Address Input Buffer Buffer Address Input • 1 2 3 4 5 10 11 12 13 14 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND BS62LV256SC 6 BS62LV256SI 23 7 BS62LV256PC 22 8 BS62LV256PI 21 BS62LV256JC 9 BS62LV256JI 20 19 18 17 16 15 18 Row Decoder 512 Memory Array 512 x 512 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BS62LV256TC BS62LV256TI 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 8 Data Output Buffer 8 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62LV256 • 1 Revision 2.2 April 2001 BSI PIN DESCRIPTIONS BS62LV256 Function These 15 address inputs select one of the 32768 x 8-bit words in the RAM CE is active LOW. Chip enables must be active when data read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground Name A0-A14 Address Input CE Chip Enable Input WE Write Enable Input OE Output Enable Input DQ0 – DQ7 Data Input/Output Ports Vcc Gnd TRUTH TABLE MODE Not selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 C to +85 C O O Vcc 2.4V ~ 5.5V 2.4V ~ 5.5V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL CIN PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VIN=0V VI/O=0V 6 8 pF pF CDQ 1. This parameter is guaranteed and not tested. R0201-BS62LV256 2 Revision 2.2 April 2001 BSI DC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 BS62LV256 TEST CONDITIONS Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS MIN. -0.5 2.0 2.2 --Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V TYP. (1) ----------0.01 0.4 M AX. 0.8 Vcc+0.2 1 1 0.4 -20 35 1 2 0.2 1.0 UNITS V V uA uA V V mA mA uA Vcc = Max, V IN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = VIL, IDQ = 0mA, F = Fmax(3) CE = VIH, IDQ = 0mA CE VIN Vcc-0.2V, Vcc - 0.2V or VIN -2.4 ------- Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V 0.2V Vcc=5.0V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL VDR ICCDR tCDR tR PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE VIN CE VIN TEST CONDITIONS Vcc - 0.2V Vcc - 0.2V or VIN Vcc -0.2V Vcc - 0.2V or VIN 0.2V 0.2V MIN. 1.5 -0 TRC (2) TYP. (1) -0.01 --- MAX. -0.20 --- UNITS V uA ns ns See Retention Waveform 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE R0201-BS62LV256 3 Revision 2.2 April 2001 BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc WAVEFORM INPUTS MUST BE STEADY BS62LV256 KEY TO SWITCHING WAVEFORMS OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC TEST LOADS AND WAVEFORMS 3.3V OUTPUT 100PF INCLUDING JIG AND SCOPE MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY 1269 Ω 3.3V OUTPUT 1269 Ω , 5PF 1404 Ω INCLUDING JIG AND SCOPE 1404 Ω FIGURE 1A THEVENIN EQUIVALENT 667 Ω ALL INPUT PULSES FIGURE 1B OUTPUT 1.73V Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC and Vcc=3.0V) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change MIN. BS62LV256 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH 70 ---10 10 0 0 10 ---------- -70 70 50 --35 30 -- R0201-BS62LV256 4 Revision 2.2 April 2001 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS62LV256 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t t D OUT (5) CLZ ACS t CHZ (5) READ CYCLE3 (1,4) t RC ADDRESS t OE AA t OE CE t OH t OLZ t ACS t CLZ (5) t OHZ (5) (1,5) t CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62LV256 5 Revision 2.2 April 2001 BSI AC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC and Vcc=3.0V) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End ot Write to Output Active (CE , WE) MIN. BS62LV256 BS62LV256 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLOZ tDVWH tWHDX tGHOZ tWHQX tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW 70 70 0 70 50 0 -40 0 0 5 ------------ ------30 --30 -- SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t OE (3) WR t CW CE (5) (11) t AW WE t AS (4,10) t WP (2) t OHZ D OUT t t DW DH D IN R0201-BS62LV256 6 Revision 2.2 April 2001 BSI WRITE CYCLE2 (1,6) BS62LV256 t WC ADDRESS t CW (5) (11) CE t WE AW t WP (2) t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62LV256 7 Revision 2.2 April 2001 BSI ORDERING INFORMATION BS62LV256 BS62LV256 XX YY SPEED 70: 70ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE J: SOJ S: SOP P: PDIP T: TSOP (8mm x 13.4mm) D: DICE PACKAGE DIMENSIONS 0.020 0.005X45 θ WITH PLATING b c c1 BASE METAL b1 SOP - 28 R0201-BS62LV256 8 Revision 2.2 April 2001 BSI PACKAGE DIMENSIONS (continued) 12 (2x) 12 (2x) BS62LV256 UNIT SYMBOL INCH 0.0433 0.004 0.0045 0.0026 0.039 0.002 0.009 0.002 0.008 0.001 0.004 ~ 0.008 0.004 ~ 0.006 0.465 0.004 0.315 0.004 0.022 0.004 0.528 0.008 0.0197 +0.008 - 0.004 0.0315 0.004 0.004 Max. 0~ 8 MM 1.10 0.10 0.115 0.065 1.00 0.05 0.22 0.05 0.20 0.03 0.10 ~ 0.21 0.10 ~ 0.16 11.80 0.10 8.00 0.10 0.55 0.10 13.40 0.20 0.50 +0.20 - 0.10 0.80 0.10 0.1 Max. 0~ 8 A A1 A2 b b1 c c1 D E e HD L L1 y 0 HD c L 1 28 E b e Seating Plane y 14 15 12 (2X) "A" D GAUGE PLANE A2 A A 0.254 0 A1 14 15 SEATING PLANE A 12 (2X) L "A" DATAIL VIEW L1 WITH PLATING 1 28 b c c1 BASE METAL b1 SECTION A-A TSOP - 28 PDIP - 28 R0201-BS62LV256 9 Revision 2.2 April 2001 BSI PACKAGE DIMENSIONS (continued) BS62LV256 SOJ - 28 R0201-BS62LV256 10 Revision 2.2 April 2001 BSI REVISION HISTORY Revision 2.2 BS62LV256 Description 2001 Data Sheet release Date Apr. 15, 2001 Note R0201-BS62LV256 11 Revision 2.2 April 2001