BS62LV4006PCP70

Very Low Power CMOS SRAM 512K X 8 bit Pb-Free and Green package materials are compliant to RoHS BS62LV4006 n FEATURES Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 30mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.25uA (Typ.) at 25 OC VCC = 5.0V Operation current : 70mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25OC Ÿ High speed access time : -55 55ns (Max.) at VCC=3.0~5.5V -70 70ns (Max.) at VCC=2.7~5.5V Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V n DESCRIPTION The BS62LV4006 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.25uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV4006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4006 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 600mil Plastic DIP, 400 mil TSOP II, 8mmx13.4mm STSOP and 8mmx20mm TSOP package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY BS62LV4006DC BS62LV4006EC BS62LV4006HC BS62LV4006PC BS62LV4006SC BS62LV4006STC BS62LV4006TC BS62LV4006EI BS62LV4006HI BS62LV4006PI BS62LV4006SI BS62LV4006STI BS62LV4006TI OPERATING TEMPERATURE STANDBY (ICCSB1, Max) Operating (ICC, Max) PKG TYPE VCC=3V 10MHz fMax. VCC=5.0V VCC=3.0V 1MHz VCC=5V 10MHz fMax. 1MHz Commercial +0OC to +70OC 10uA 2.0uA 9mA 43mA 68mA 1.5mA 18mA 29mA Industrial -40OC to +85OC 20uA 4.0uA 10mA 45mA 70mA 2mA 20mA 30mA DICE TSOP II-32 BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 TSOP II-32 BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 n PIN CONFIGURATIONS n BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A12 A14 A16 A18 A15 A17 A13 A8 A9 A11 • BS62LV4006TC BS62LV4006TI BS62LV4006STC BS62LV4006STI 1 2 A1 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Address Input Buffer 10 Row Decoder 1024 Memory Array 1024 x 4096 4096 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 8 Data Input Buffer 8 256 Column Decoder 9 8 Column I/O Write Driver Sense Amp 3 NC 4 A3 5 A6 6 A8 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 • BS62LV4006EC BS62LV4006EI BS62LV4006SC BS62LV4006SI BS62LV4006PC BS62LV4006PI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 A A0 B DQ4 A2 WE A4 A7 DQ0 Data Output Buffer C DQ5 NC A5 DQ1 D VSS VCC CE WE Control Address Input Buffer E VCC VSS OE VCC GND A7 A6 A5 A4 A3 A2 A1 A0 A0 F DQ6 A18 A17 DQ2 G DQ7 OE CE A16 A15 DQ3 H A9 A10 A11 A12 A13 A14 36-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS62LV4006 1 Revision 1.4 May. 2006 BS62LV4006 n PIN DESCRIPTIONS Name A0-A18 Address Input CE Chip Enable Input Function These 19 address inputs select one of the 524,288 x 8-bit in the RAM CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. There 8 bi-directional ports are used to read data from or write data into the RAM. WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports VCC GND Power Supply Ground n TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write CE H L L L WE X H H L OE X H L X I/O OPERATION High Z High Z DOUT DIN VCC CURRENT ICCSB, ICCSB1 ICC ICC ICC n ABSOLUTE MAXIMUM RATINGS SYMBOL VTERM TBIAS TSTG PT IOUT (1) n OPERATING RANGE UNITS V O PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5(2) to 7.0 -40 to +125 -60 to +150 1.0 20 RANG Commercial Industrial AMBIENT TEMPERATURE 0OC to + 70OC -40OC to + 85OC VCC 2.4V ~ 5.5V 2.4V ~ 5.5V C C O W mA n CAPACITANCE (1) (TA = 25 C, f = 1.0MHz) O SYMBOL PAMAMETER CONDITIONS MAX. UNITS CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV4006 1. This parameter is guaranteed and not 100% tested. 2 Revision 1.4 May. 2006 BS62LV4006 n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER Power Supply Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current – TTL Standby Current – CMOS VCC = Max, VIN = 0V to VCC V CC = Max, CE= VIH, or OE = VIH, VI/O = 0V to V CC V CC = Max, IOL = 2.0mA V CC = Min, IOH = -1.0mA CE = VIL, IDQ = 0mA, f = FMAX(4) CE = VIL, IDQ = 0mA, f = 1MHz CE = VIH, IDQ = 0mA CE≧ VCC-0.2V, VIN≧ V CC-0.2V or VIN≦ 0.2V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V O O TEST CONDITIONS MIN. 2.4 -0.5(2) 2.2 ---2.4 ----- TYP.(1) ----------0.25 1.5 MAX. 5.5 0.8 VCC+0.3(3) 1 1 0.4 -30 70 2 10 0.5 1.0 4.0 20 UNITS V V V UA UA V V mA mA mA uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICC (MAX.) is 29mA/68mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 2.0uA/10uA at VCC=3.0V/5.0V and TA=70OC. n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL VDR ICCDR(3) tCDR tR PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time O O TEST CONDITIONS CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V MIN. 1.5 -0 TYP. (1) -0.1 --- MAX. -1.5 --- UNITS V uA ns ns See Retention Waveform tRC (2) 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCRD(Max.) is 1.0uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled) Data Retention Mode VCC VIH VCC VDR≧1.5V VCC tCDR CE≧VCC - 0.2V tR VIH CE R0201-BS62LV4006 3 Revision 1.4 May. 2006 BS62LV4006 n AC TEST CONDITIONS (Test Load and Input/Output Reference) WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “L” TO “H” CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE “OFF” STATE n KEY TO SWITCHING WAVEFORMS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 10% 90% 90% 10% →← Rise Time : 1V/ns →← Fall Time : 1V/ns 1. Including jig and scope capacitance. n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. M AX. 55 ---10 5 --10 ----------55 55 30 --30 25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. M AX. 70 ---10 5 --10 ----------70 70 35 --35 30 -- O O DESCRIPTION UNITS tAVAX tAVQX tE1LQV tGLQV tE1LQX tGLQX tE1HQZ tGHQZ tAVQX tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Output Enable to Output High Z Data Hold from Address Change ns ns ns ns ns ns ns ns ns R0201-BS62LV4006 4 Revision 1.4 May. 2006 BS62LV4006 n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH DOUT tAA tOH READ CYCLE 2 (1,3,4) CE tACS tCLZ DOUT (5) tCHZ (5) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE (5) tOH tOLZ tACS tCLZ tOHZ tCHZ (5) (1,5) DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS62LV4006 5 Revision 1.4 May. 2006 BS62LV4006 n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE, WE) 55 55 0 55 30 0 -25 0 -5 TYP. -----------M AX. ------25 --25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. 70 70 0 70 35 0 -30 0 -5 TYP. -----------M AX. ------30 --30 -ns ns ns ns ns ns ns ns ns ns ns O O DESCRIPTION UNITS tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR OE tCW CE (5) (11) (3) tAW WE tAS tOHZ DOUT tDH tDW DIN (4,10) tWP (2) R0201-BS62LV4006 6 Revision 1.4 May. 2006 BS62LV4006 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW (11) CE (5) tAW WE tAS tWHZ DOUT (4,10) tWP (2) tOW tDW tDH (8,9) (7) (8) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write. R0201-BS62LV4006 7 Revision 1.4 May. 2006 BS62LV4006 n ORDERING INFORMATION BS62LV4006 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE E: TSOP II H: BGA-36-0608 P: PDIP S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS W ITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV4006 8 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV4006 9 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) PDIP - 32 NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.2 Max. BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75 D1 e VIEW A 36 mini-BGA (6 x 8mm) R0201-BS62LV4006 E1 10 Revision 1.4 May. 2006 BS62LV4006 n PACKAGE DIMENSIONS (continued) DIMENSION (MM) MIN. A TX 32 17 DIMENSION (INCH) MAX. 1.20 NOM. MIN. NOM. MAX. 0.047 E1 -XE A1 A2 0.05 0.95 0.30 0.30 0.12 0.10 20.82 11.56 10.03 0.10 1.00 0.40 0.127 20.95 11.76 10.16 1.27 BASIC 0.15 1.05 0.52 0.45 0.21 0.16 21.08 11.96 10.29 0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394 0.004 0.039 0.016 0.005 0.825 0.463 0.400 0.050 BASIC 0.006 0.042 0.020 0.018 0.008 0.006 0.830 0.471 0.405 0.20 b b1 c c1 D 1 YY e b 16 E "X" E1 e L L1 0.40 0.50 0.25 BASIC 0.8 REF 0.60 0.016 0.020 0.010 BASIC 0.031 REF 0.024 D ZD A2 A L2 R R1 ZD 0.12 0.12 0.25 0.005 0.005 0.037 REF 0.010 0.95 REF 0.10 A1 Y -T- SEATING PLANE Y 0.004 0.44 REF RAD R L1 GAGE PLANE b b1 L L2 RAD R1 WITH PLATING BASE METAL NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS. 2. REFREENCE DOCUMENT : JEDEC MS-024 3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. c DETAIL "X" 0.44 REF 0 ° ~ 8° SECTION Y-Y TSOP II - 32 c1 c R0201-BS62LV4006 11 Revision 1.4 May. 2006 BS62LV4006 n Revision History Revision No. 1.2 History To add Icc1 characteristic parameter To improve Iccsb1 spec. I-grade from 60uA to 20uA at 5.0V 10uA to 4.0uA at 3.0V C-grade from 30uA to 10uA at 5.0V 5.0uA to 2.0uA at 3.0V To Add 400 mil TSOP II package type Change I-grade operation temperature range - from –25OC to –40OC Draft Date Jan. 13, 2006 Remark 1.3 1.4 March 20, 2006 May. 25, 2006 R0201-BS62LV4006 12 Revision 1.4 May. 2006