BS62LV4007STC-70

BSI FEATURES Very Low Power/Voltage CMOS SRAM 512K X 8 bit DESCRIPTION BS62LV4007 • Vcc operation voltage : 4.5V ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 68mA (@55ns) operating current I -grade: 70mA (@55ns) operating current C-grade: 58mA (@70ns) operating current I -grade: 60mA (@70ns) operating current 2.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • Three state outputs and TTL compatible The BS62LV4007 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) , and active LOW output enable (OE) and three-state output drivers. The BS62LV4007 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP , PDIP, TSOP II and STSOP package. PRODUCT FAMILY PRODUCT FAMILY BS62LV4007TC BS62LV4007STC BS62LV4007SC BS62LV4007EC BS62LV4007PC BS62LV4007TI BS62LV4007STI BS62LV4007SI BS62LV4007EI BS62LV4007PI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) 55ns :4.5~5.5V 70ns :4.5~5.5V POWER DISSIPATION ( I CCSB1 , Max ) STANDBY Vcc =5.0V Operating ( I CC , Max ) Vcc = 5.0V 55ns Vcc =5.0V 70ns PKG TYPE TSOP - 32 STSOP -32 SOP - 32 TSOP2 - 32 PDIP - 32 TSOP - 32 STSOP - 32 SOP - 32 TSOP2 - 32 PDIP - 32 +0 C to +70 C O O 4.5V ~ 5.5V 55 / 70 30uA 68mA 58mA - 40 O C to +85 C O 4.5V ~ 5.5V 55 / 70 60uA 70mA 60mA PIN CONFIGURATIONS A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 BLOCK DIAGRAM A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 • BS62LV4007SC BS62LV4007SI BS62LV4007EC BS62LV4007EI BS62LV4007PC BS62LV4007PI Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 X 2048 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 CE WE OE Vdd GND A11 A9 A8 A3 A2 A1 A0 A10 Control Address Input Buffer 8 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BS62LV4007TC BS62LV4007STC BS62LV4007TI BS62LV4007STI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 Data Output Buffer 8 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV4007 • 1 Revision 1.1 Jan. 2004 BSI PIN DESCRIPTIONS BS62LV4007 Function These 19 address inputs select one of the 524,288 x 8-bit words in the RAM CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. Name A0-A18 Address Input CE Chip Enable Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports Vcc GND These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with OPERATING RANGE UNITS V O O RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 C to +70 C -40 C to +85 C O O O O Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not 100% tested. R0201-BS62LV4007 2 Revision 1.1 Jan. 2004 BSI DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC (5) BS62LV4007 TEST CONDITIONS Vcc = 5.0 V Vcc = 5.0 V PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL MIN. TYP. -0.5 2.2 --Vcc = 5.0 V Vcc = 5.0 V 55ns 70ns (1) MAX. 0.8 Vcc+0.3 1 1 0.4 -70 60 1.0 UNITS -------- V V uA uA V V mA Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2.0mA Vcc = Min, I OH = -1.0mA CE = VIL, IDQ = 0mA, F=Fmax (2) CE = VIH, IDQ = 0mA CE ≧ Vcc-0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc = 5.0 V -2.4 -- ICCSB (4) Vcc = 5.0 V -- -- mA ICCSB1 Standby Current-CMOS Vcc = 5.0 V -- 2.0 60 uA 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. IccSB1_MAX. is 30uA at Vcc=5.0V and TA=70oC. 5. Icc_MAX. is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and TA=0~70oC. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR PARAMETER Vcc for Data Retention TEST CONDITIONS CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V MIN. 1.5 TYP. (1) -- MAX. -- UNITS V ICCDR tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time -0 0.3 --- 1.3 --- uA ns ns See Retention Waveform TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.8uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM Vcc VIH Vcc ( CE Controlled ) Data Retention Mode VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE R0201-BS62LV4007 3 Revision 1.1 Jan. 2004 BSI AC TEST CONDITIONS (Test Load and Input/Output Reference) BS62LV4007 KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load , AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 55ns (Vcc = 4.5~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns (Vcc = 4.5~5.5V) MIN. TYP. MAX. UNIT t AVAX t AVQV t ELQV t GLQV t ELQX t GLQX t EHQZ t GHQZ t AXOX tRC t AA t ACS tOE tCLZ tOLZ tCHZ tOHZ tOH 55 ---10 10 --10 ---------- -55 55 30 --30 25 -- 70 ---10 10 --10 ---------- -70 70 35 --35 30 -- ns ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t D OUT t OH AA t OH R0201-BS62LV4007 4 Revision 1.1 Jan. 2004 BSI READ CYCLE2 (1,3,4) BS62LV4007 CE t t D OUT (5) CLZ ACS t CHZ (5) READ CYCLE3 (1,4) t RC ADDRESS t OE AA t CE t OH OE t t ACS t (5) CLZ OLZ t OHZ (5) (1,5) t CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV4007 5 Revision 1.1 Jan. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End ot Write to Output Active (CE , WE) CYCLE TIME : 55ns (Vcc = 4.5~5.5V) MIN. TYP. MAX. BS62LV4007 CYCLE TIME : 70ns (Vcc = 4.5~5.5V) MIN. TYP. MAX. UNIT t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t WLOZ t DVWH t WHDX t GHOZ t WHQX t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OHZ t OW 55 55 0 55 30 0 -25 0 -5 ------------ ------25 --25 -- 70 70 0 70 35 0 -30 0 -5 ------------ ------30 --30 -- ns ns ns ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t WR OE (3) t CW CE (5) (11) t AW WE t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS62LV4007 6 Revision 1.1 Jan. 2004 BSI WRITE CYCLE2 (1,6) BS62LV4007 t WC ADDRESS (11) (5) t t AW CW CE t WP (2) WE t AS (4,10) t WHZ D OUT t t DW OW (7) (8) t DH D IN (8,9) NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62LV4007 7 Revision 1.1 Jan. 2004 BSI ORDERING INFORMATION BS62LV4007 Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP E: TSOP 2 ST: Small TSOP T: TSOP P: PDIP BS62LV4007 X X Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV4007 8 Revision 1.1 Jan. 2004 BSI BS62LV4007 TSOP2 - 32 TSOP - 32 R0201-BS62LV4007 9 Revision 1.1 Jan. 2004 BSI PACKAGE DIMENSIONS (continued) BS62LV4007 STSOP - 32 PDIP - 32 R0201-BS62LV4007 10 Revision 1.1 Jan. 2004