BS62LV8006ECP70

BSI FEATURES Very Low Power/Voltage CMOS SRAM 1M X 8 bit GENERAL DESCRIPTION BS62LV8006 • Vcc operation voltage : 4.5V ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 75mA (@55ns) operating current I -grade: 76mA (@55ns) operating current C-grade: 60mA (@70ns) operating current I -grade: 61mA (@70ns) operating current 8.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options The BS62LV8006 is a high performance , very low power CMOS Static Random Access Memory organized as 1,048,576 words by 8 bits and operates from a range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 8.0uA at 5V/25oC and maximum access time of 55ns at 5.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE1) , an active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The BS62LV8006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV8006 is available in 48B BGA and 44L TSOP2 packages. PRODUCT FAMILY PRODUCT FAMILY BS62LV8006EC BS62LV8006FC BS62LV8006EI BS62LV8006FI OPERATING TEMPERATURE +0 C to +70 C -40 O C to +85O C O O Vcc RANGE 4.5V ~ 5.5V 4.5V ~ 5.5V SPEED ( ns ) 55ns : 4.5~5.5V 70ns : 4.5~5.5V ( I CCSB1, Max ) POWER DISSIPATION STANDBY Operating ( ICC , Max ) PKG TYPE TSOP2-44 BGA-48-0912 TSOP2-44 BGA-48-0912 Vcc=5V Vcc=5V 55ns 55 / 70 55 / 70 55uA 110uA 75mA 76mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE1 NC NC DQ0 DQ1 VCC GND DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5 6 A5 A6 A7 OE CE2 A8 NC NC DQ7 DQ6 GND VCC DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14 FUNCTIONAL BLOCK DIAGRAM BS62LV8006EC BS62LV8006EI A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 X 4096 4096 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CE2 WE OE Vdd Gnd 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 512 Column Decoder 18 Control Address Input Buffer 2 3 4 A NC NC OE A0 A1 A2 CE2 B NC A3 A4 CE1 NC NC 8 C D0 NC A5 A6 Data Output Buffer 8 D4 D VSS D1 A17 A7 D5 VCC E VCC D3 D2 VCC A16 D6 VSS F NC A14 A15 NC D7 A11A9 A8 A3 A2 A1 A0A10 A19 G NC NC A12 A13 WE NC H A18 A8 A9 A10 A11 A19 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV8006 1 Revision 2.1 Jan. 2004 BSI PIN DESCRIPTIONS BS62LV8006 Function These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. is Name A0-A19 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports Vcc Gnd These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 C to +70 C -40 C to +85 C O O O O Vcc 4.5V ~ 5.5V 4.5V ~ 5.5V C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 10 12 pF pF 1. This parameter is guaranteed and not 100% tested. R0201-BS62LV8006 2 Revision 2.1 Jan. 2004 BSI DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC(4) ICCSB ICCSB1(5) BS62LV8006 TEST CONDITIONS Vcc=5V PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS MIN. TYP. (1) MAX. -0.5 2.2 ---2.4 -------------8 0.8 Vcc+0.3 1 1 0.4 -76 61 2 110 UNITS V V uA uA V V mA mA uA Vcc=5V Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH or CE2 = VIL or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE1= VIL, CE2= VIH, IDQ = 0mA, F = Fmax(2) 55ns 70ns Vcc=5V Vcc=5V Vcc=5V CE1 = VIH or CE2= VIL, IDQ = 0mA CE1≧Vcc-0.2V or CE2≦0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=5V Vcc=5V 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 75mA@55ns/0~70oC. ; Icc_Max. is 60mA@70ns/0~70oC. 5.IccsB1 is 55uA at Vcc=5.0V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR PARAMETER Vcc for Data Retention TEST CONDITIONS CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V MIN. 1.5 TYP. (1) -- MAX. -- UNITS V ICCDR(3) tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time -0 0.8 -(2) 2.5 --- uA ns ns See Retention Waveform TRC -- 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR(Max.) is 1.3uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode VDR ≥ 1.5V Vcc VIH Vcc Vcc t CDR CE1 ≥ Vcc - 0.2V tR VIH CE1 LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc Vcc VDR ≧ 1.5V Vcc t CDR tR CE2 ≦ 0.2V CE2 VIL VIL R0201-BS62LV8006 3 Revision 2.1 Jan. 2004 BSI AC TEST CONDITIONS (Test Load and Input/Output Reference) BS62LV8006 KEY TO SWITCHING WAVEFORMS Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load , AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 70ns Vcc=4.5~5.5V DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time (CE1) (CE2) CYCLE TIME : 55ns Vcc=4.5~5.5V MIN. TYP. MAX. MIN. TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns tAVAX tAVQV t E1LQV t E2LQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX tRC tAA tACS1 tACS2 tOE tCLZ tOLZ tCHZ tOHZ tOH 70 ----10 10 --10 ----------- -70 70 70 35 --35 30 -- 55 ----10 10 --10 ----------- -55 55 55 30 --30 25 -- Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Data Hold from Address Change R0201-BS62LV8006 4 Revision 2.1 Jan. 2004 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS62LV8006 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE2 t t ACS2 ACS1 CE1 t D OUT (5) CLZ t (5) CHZ READ CYCLE3 (1,4) ADDRESS t RC t OE AA t CE2 OE t OH t t t t (5) CLZ ACS2 CE1 OLZ ACS1 t t OHZ CHZ (5) (1,5) D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV8006 5 Revision 2.1 Jan. 2004 BSI AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE2,CE1 , WE) CYCLE TIME : 70ns (Vcc=4.5~5.5V) BS62LV8006 CYCLE TIME : 55ns (Vcc=4.5~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNIT t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t WLOZ t DVWH t WHDX t GHOZ t WHQX t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OHZ t OW 70 70 0 70 35 0 -30 0 -5 ------------ ------30 --30 -- 55 55 0 55 30 0 -25 0 -5 ------------ ------25 --25 -- ns ns ns ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC t WR OE (3) CE2 (5) t CW CE1 (5) (11) t AW WE (3) t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS62LV8006 6 Revision 2.1 Jan. 2004 BSI WRITE CYCLE2 (1,6) BS62LV8006 t WC ADDRESS CE2 (11) CE1 (5) t CW t WE AW t WP t WR (3) (2) t AS (4,10) t WHZ D OUT t OW t DW t DH (8,9) (7) (8) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS62LV8006 7 Revision 2.1 Jan. 2004 BSI ORDERING INFORMATION BS62LV8006 BS62LV8006 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 F: BGA-48-0912 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS62LV8006 8 Revision 2.1 Jan. 2004 BSI PACKAGE DIMENSIONS (continued) 0.25 ± 0.05 1.4 Max. BS62LV8006 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 3.375 D1 N 48 D 12.0 E 9.0 D1 5.25 E1 3.75 e 0.75 SOLDER BALL 0.35± 0.05 e VIEW A 48 mini-BGA (9mm x 12mm) 2.625 E ± 0.1 E1 R0201-BS62LV8006 9 Revision 2.1 Jan. 2004