BS62UV4000SI

BSI FEATURES Ultra Low Power/Voltage CMOS SRAM 512K X 8 bit DESCRIPTION BS62UV4000 • Ultra low operation voltage : 1.8V ~ 3.6V • Ultra low power consumption : Vcc = 2.0V C-grade: 15mA (Max.) operating current I -grade: 20mA (Max.) operating current 0.2uA (Typ.) CMOS standby current Vcc = 3.0V C-grade: 20mA (Max.) operating current I -grade: 25mA (Max.) operating current 0.25uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 2.0V -10 100ns (Max.) at Vcc = 2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options The BS62UV4000 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.2uA and maximum access time of 70ns in 2.0V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62UV4000 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62UV4000 is available in the JEDEC standard 32 pin SOP , TSOP, TSOP II and STSOP PRODUCT FAMILY PRODUCT FAMILY BS62UV4000TC BS62UV4000STC BS62UV4000SC BS62UV4000EC BS62UV4000PC BS62UV4000TI BS62UV4000STI BS62UV4000SI BS62UV4000EI BS62UV4000PI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) Vcc = 2.0V POWER DISSIPATION ( I CCSB1 , Max ) STANDBY Vcc =3.0V Operating ( I CC , Max ) Vcc = 2.0V Vcc = 2.0V Vcc =3.0V PKG TYPE TSOP - 32 STSOP -32 SOP - 32 TSOP2 - 32 PDIP - 32 TSOP - 32 STSOP - 32 SOP - 32 TSOP2 - 32 PDIP - 32 +0 C to +70 C O O 1.8V ~ 3.6V 70 / 100 1uA 1.5uA 15mA 20mA - 40 O C to +85 C O 1.8V ~ 3.6V 70 / 100 2uA 3uA 20mA 25mA PIN CONFIGURATIONS A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 BS62UV4000SC 9 BS62UV4000SI 10 BS62UV4000EC BS62UV4000EI 11 BS62UV4000PC 12 BS62UV4000PI 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 BLOCK DIAGRAM A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 • Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 X 2048 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 CE WE OE Vdd GND A11 A9 A8 A3 A2 A1 A0 A10 Control Address Input Buffer 8 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BS62UV4000TC BS62UV4000STC BS62UV4000TI BS62UV4000STI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 Data Output Buffer 8 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62UV4000 • 1 Revision 2.4 April 2002 BSI PIN DESCRIPTIONS BS62UV4000 Function These 19 address inputs select one of the 524,288 x 8-bit words in the RAM CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. Name A0-A18 Address Input CE Chip Enable Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports Vcc GND These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE Not selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage Respect to GND with OPERATING RANGE UNITS V O RATING -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 RANGE Commercial Industrial AMBIENT TEMPERATURE 0 O C to +70 O C -40 O C to +85 O C Vcc 1.8V ~ 3.6V 1.8V ~ 3.6V Temperature Under Bias Storage Temperature Power Dissipation DC Output Current C C O W mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V VI/O=0V 6 8 pF pF 1. This parameter is guaranteed and not tested. R0201-BS62UV4000 2 Revision 2.4 April 2002 BSI DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) PARAMETER NAME VIL VIH IIL IOL VOL VOH ICC BS62UV4000 TEST CONDITIONS Vcc = 2.0 V Vcc = 3.0 V Vcc = 2.0 V Vcc = 3.0 V PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL MIN. TYP. -0.5 1.4 2.0 --Vcc = 2.0 V Vcc = 3.0 V Vcc = 2.0 V Vcc = 3.0 V Vcc = 2.0 V Vcc = 3.0 V Vcc = 2.0 V (1) MAX. 0.6 0.8 Vcc+0.2 1 1 0.4 -15 20 0.6 1 1 1.5 UNITS -------- V V uA uA V V mA Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 1mA Vcc = Min, I OH = -0.5mA CE = VIL, IDQ = 0mA, F = Fmax(3) -1.6 2.4 -- ICCSB CE = VIH, IDQ = 0mA CE VIN Vcc-0.2V, Vcc - 0.2V or VIN Vcc = 3.0 V Vcc = 2.0 V -- -0.2 0.25 mA ICCSB1 Standby Current-CMOS 0.2V Vcc = 3.0 V -- uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL VDR PARAMETER Vcc for Data Retention CE VIN CE VIN TEST CONDITIONS Vcc - 0.2V Vcc - 0.2V or VIN Vcc - 0.2V Vcc - 0.2V or VIN 0.2V MIN. 1.5 TYP. (1) -- MAX. -- UNITS V ICCDR tCDR tR Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time 0.2V -0 0.1 --- 1 --- uA ns ns See Retention Waveform TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VIH Vcc VDR ≥ 1.5V Vcc t CDR CE ≥ Vcc - 0.2V tR VIH CE R0201-BS62UV4000 3 Revision 2.4 April 2002 BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0 5ns 0.5Vcc WAVEFORM INPUTS BS62UV4000 KEY TO SWITCHING WAVEFORMS OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MUST BE STEADY MAY CHANGE FROM H TO L 1333 Ω AC TEST LOADS AND WAVEFORMS 2V OUTPUT 100PF INCLUDING JIG AND SCOPE 1333 Ω 2V OUTPUT MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY , 5PF 2000 Ω INCLUDING JIG AND SCOPE 2000 Ω FIGURE 1A THEVENIN EQUIVALENT 800 Ω FIGURE 1B OUTPUT 1.2V ALL INPUT PULSES Vcc GND 10% 90% 90% 10% → ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change BS62UV4000-70 MIN. TYP. MAX. BS62UV4000-10 MIN. TYP. MAX. UNIT t AVAX t AVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ t AXOX tRC t AA t ACS tOE tCLZ tOLZ tCHZ tOHZ tOH 70 ---10 10 0 0 10 ---------- -70 70 35 --35 30 -- 100 ---15 15 0 0 15 ---------- -100 100 50 --40 35 -- ns ns ns ns ns ns ns ns ns R0201-BS62UV4000 4 Revision 2.4 April 2002 BSI SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) BS62UV4000 t RC ADDRESS t D OUT t OH AA t OH READ CYCLE2 (1,3,4) CE t t D OUT (5) CLZ ACS t CHZ (5) READ CYCLE3 (1,4) t RC ADDRESS t OE AA t CE t OH OE t t ACS t (5) CLZ OLZ t OHZ (5) (1,5) t CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62UV4000 5 Revision 2.4 April 2002 BSI AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End ot Write to Output Active (CE , WE) BS62UV4000-70 MIN. TYP. MAX. BS62UV4000 BS62UV4000-10 MIN. TYP. MAX. UNIT t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t WLOZ t DVWH t WHDX t GHOZ t WHQX t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OHZ t OW 70 70 0 70 35 0 -30 0 0 5 ------------ ------30 --30 -- 100 100 0 100 50 0 -40 0 0 10 ------------ ------40 --40 -- ns ns ns ns ns ns ns ns ns ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t WR OE (3) t CW CE (5) (11) t AW WE t AS (4,10) t WP (2) t OHZ D OUT t DH t DW D IN R0201-BS62UV4000 6 Revision 2.4 April 2002 BSI WRITE CYCLE2 (1,6) BS62UV4000 t WC ADDRESS (11) (5) t t AW CW CE t WP (2) WE t AS (4,10) t DH t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62UV4000 7 Revision 2.4 April 2002 BSI ORDERING INFORMATION BS62UV4000 BS62UV4000 XX YY SPEED 70: 70ns 10: 100ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP E: TSOP 2 ST: Small TSOP T: TSOP P: PDIP PACKAGE DIMENSIONS WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62UV4000 8 Revision 2.4 April 2002 BSI BS62UV4000 TSOP2 - 32 TSOP - 32 R0201-BS62UV4000 9 Revision 2.4 April 2002 BSI PACKAGE DIMENSIONS (continued) BS62UV4000 STSOP - 32 PDIP - 32 R0201-BS62UV4000 10 Revision 2.4 April 2002 BSI REVISION HISTORY Revision 2.2 2.3 2.4 BS62UV4000 Description 2001 Data Sheet release Modify Standby Current (Typ. and Max.) Modify some AC parameters Date Apr. 15, 2001 Jun. 29, 2001 April,10,2002 Note R0201-BS62UV4000 11 Revision 2.4 April 2002