SN74LVC1G3157-Q1
SCES463H – JUNE 2003 – REVISED DECEMBER 2021
SN74LVC1G3157-Q1 Automotive Single-Pole Double-Throw Analog Switch
1 Features
3 Description
•
The SN74LVC1G3157-Q1 device is a single-pole
double-throw (SPDT) analog switch designed for
1.65-V to 5.5-V VCC operation.
•
•
•
•
•
•
•
•
•
•
Functional safety-capable
– Documentation available to aid functional safety
system design
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
ESD protection exceeds 2000 V per MIL-STD-883,
method 3015; exceeds 200 V using machine
model (C = 200 pF, R = 0)
1.65-V to 5.5-V VCC operation
Useful for analog and digital applications
Specified break-before-make switching
Rail-to-rail signal handling
High degree of linearity
High speed, typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
Low ON-State resistance, typically ≉6 Ω
(VCC = 4.5 V)
Latch-up performance exceeds 100 mA per JESD
78, Class II
The SN74LVC1G3157 device can handle analog
and digital signals. The device permits signals with
amplitudes of up to VCC (peak) to be transmitted in
either direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
Device Information(1)
PART NUMBER
SN74LVC1G3157-Q1
(1)
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (6)
2.00 mm × 1.25 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Advanced driver assistance systems (ADAS)
B2
1
6
4
S
B1
A
3
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G3157-Q1
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SCES463H – JUNE 2003 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Analog Switch Characteristics.................................... 7
6.8 Typical Characteristics................................................ 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................15
8.1 Overview................................................................... 15
8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................17
11 Layout........................................................................... 18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 18
12 Device and Documentation Support..........................19
12.1 Documentation Support.......................................... 19
12.2 Receiving Notification of Documentation Updates..19
12.3 Support Resources................................................. 19
12.4 Trademarks............................................................. 19
12.5 Electrostatic Discharge Caution..............................19
12.6 Glossary..................................................................19
13 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2019) to Revision H (December 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added functional safety text to the data sheet....................................................................................................1
Changes from Revision F (March 2015) to Revision G (April 2019)
Page
• Changed the automotive Features .................................................................................................................... 1
• Changed the Pin Configuration images.............................................................................................................. 3
• Changed the ESD Ratings table.........................................................................................................................4
Changes from Revision E (April 2008) to Revision F (March 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
2
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5 Pin Configuration and Functions
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
No t to scale
Figure 5-2. DCK Package
6-Pin SC70
Top View
No t to scale
Figure 5-1. DBV Package
6-Pin SOT-23
Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
A
4
I/O
Common terminal
B1
3
I/O
First terminal
B2
1
I/O
Second terminal
GND
2
—
Ground
S
6
I
Select
VCC
5
I
Power supply
(1)
I = input, O = output, GND = ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage(2)
VCC
voltage(2) (3)
MIN
MAX
UNIT
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
VIN
Control input
VI/O
Switch I/O voltage(2) (3) (4) (5)
IIK
Control input clamp current
VIN < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0
–50
mA
II/O
ON-state switch current
VI/O = 0 to VCC
(6)
Continuous current through VCC or GND
θJA
Package thermal impedance(7)
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
±128
mA
±100
mA
DBV package
165
DCK package
258
–65
°C/W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
II, IO, IA, and IBn are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 1C
V(ESD)
(1)
4
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
UNIT
±2000
Other pins
±1000
Corner pins (B2, B1, S,
and A)
±1000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX UNIT
VCC
1.65
5.5
V
VI/O
0
VCC
V
0
5.5
V
VIN
VIH
High-level input voltage, control input
VIL
Low-level input voltage, control input
VCC = 1.65 V to 1.95 V
VCC × 0.75
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC × 0.25
VCC = 2.3 V to 5.5 V
Δt/Δv Input transition rise/fall time
V
VCC × 0.3
VCC = 1.65 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
VCC = 4.5 V to 5.5 V
10
TA
(1)
V
VCC × 0.7
–40
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC1G3157-Q1
THERMAL METRIC(1)
DBV (SOT-23)
DCK (SC70)
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
201.8
233.8
RθJC(top)
Junction-to-case (top) thermal resistance
103.7
107.9
RθJB
Junction-to-board thermal resistance
51.8
52.7
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
12
4.9
51.4
52.4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
ON-state switch
resistance(2)
ON-state switch resistance
over signal range(2) (3)
rrange
See Figure 7-1
and Figure 6-1
ron(flat)
ON-state resistance
(4) (6)
flatness(2)
VCC
VI = 0 V,
IO = 4 mA
VI = 1.65 V,
IO = –4 mA
VI = 0 V,
IO = 8 mA
VI = 2.3 V,
IO = –8 mA
VI = 0 V,
IO = 24 mA
VI = 3 V,
IO = –24 mA
VI = 0 V,
IO = 30 mA
VI = 2.4 V,
IO = –30 mA
VI = 4.5 ,
IO = –30 mA
1.65 V
2.3 V
3V
4.5 V
MIN TYP(1)
MAX UNIT
11
20
15
50
8
12
11
30
7
9.5
9
20
6
7.5
7
12
7
1.65 V
140
IA = –8 mA
2.3 V
45
IA = –24 mA
3V
18
IA = –30 mA
4.5 V
10
VBn = 1.15 V,
IA = –4 mA
1.65 V
0.5
VBn = 1.6 V,
IA = –8 mA
2.3 V
0.1
VBn = 2.1 V,
IA = –24 mA
3V
0.1
VBn = 3.15 V,
IA = –30 mA
4.5 V
0.1
IA = –4 mA
1.65 V
110
IA = –8 mA
2.3 V
26
IA = –24 mA
3V
9
IA = –30 mA
4.5 V
4
0 ≤ VBn ≤ VCC
Ω
Ω
Ω
±1
Ioff (7)
OFF-state switch leakage
current
IS(on)
ON-state switch leakage current VI = VCC or GND, VO = Open (see Figure 7-3)
IIN
Control input current
0 ≤ VIN ≤ VCC
ICC
Supply current
VIN = VCC or GND
5.5 V
ΔICC
Supply-current change
VIN = VCC – 0.6 V
5.5 V
Cin
Control input capacitance S
5V
2.7
pF
Cio(off)
Switch I/O capacitance
5V
5.2
pF
Cio(on)
Switch I/O capacitance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0 ≤ VI, VO ≤ VCC (see Figure 7-2)
Bn
Bn
1.65 V
to 5.5 V
Ω
15
IA = –4 mA
0 ≤ VBn ≤ VCC
(see Figure 7-1 and Figure 6-1)
Difference in on-state resistance
See Figure 7-1
between switches(2) (4) (5)
Δron
6
TEST CONDITIONS
0V
to 5.5 V
±1(1)
±1
5.5 V
5V
A
±0.05
±0.1(1)
±1
±0.05
1
17.3
17.3
±1(1)
μA
μA
μA
10
μA
500
μA
pF
TA = 25°C
Measured by the voltage drop between I/O pins at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
Specified by design
Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
This parameter is characterized, but not tested in production.
Flatness is defined as the difference between the maximum and minimum values of ON-state resistance over the specified range of
conditions.
Ioff is the same as IS(off) (OFF-state switch leakage current).
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-4 and Figure 7-10)
PARAMETER
tpd (1)
ten
FROM
(INPUT)
TO
(OUTPUT)
A or Bn
Bn or A
S
Bn
(2)
tdis (3)
tB-M (4)
(1)
(2)
(3)
(4)
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
MIN
VCC = 3.3 V
± 0.3 V
MAX
2
MIN
MAX
1.2
VCC = 5 V
± 0.5 V
MIN
0.8
UNIT
MAX
0.3
7
24
3.5
14
2.5
7.6
1.7
5.7
3
13
2
7.5
1.5
5.3
0.8
3.8
0.5
0.5
0.5
ns
ns
0.5
ns
tpd is the slower of tPLH or tPHL. Propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch
and the specified load capacitance when driven by an ideal voltage source (zero output impedance).
ten is the slower of tPZL or tPZH.
tdis is the slower of tPLZ or tPHZ.
Specified by design
6.7 Analog Switch Characteristics
TA = 25°C
PARAMETER
Frequency response
(switch on)(1)
Crosstalk
(between switches)(2)
Feedthrough attenuation
(switch off)(2)
FROM
(INPUT)
A or Bn
B1 or B2
A or Bn
Charge injection(3)
Total harmonic distortion
(1)
(2)
(3)
S
TO
(OUTPUT)
Bn or A
B2 or B1
Bn or A
A
A or Bn
Bn or A
TEST CONDITIONS
RL = 50 Ω,
fin = sine wave
(see Figure 7-5)
RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7-6)
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7-7)
CL = 0.1 nF, RL = 1 MΩ
(see Figure 7-8)
VI = 0.5 Vp-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz
(sine wave)
(see Figure 7-9)
VCC
TYP
UNIT
1.65 V
300
2.3 V
300
3V
300
4.5 V
300
1.65 V
–54
2.3 V
–54
3V
–54
4.5 V
–54
1.65 V
–57
2.3 V
–57
3V
–57
4.5 V
–57
3.3 V
3
5V
7
1.65%
0.1%
2.3%
0.025%
3%
0.015%
4.5%
0.01%
MHz
dB
dB
pC
V
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
Specified by design
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6.8 Typical Characteristics
120
VCC = 1.65 V
100
ron − W
80
60
40
VCC = 2.3 V
20
VCC = 3 V
VCC = 4.5 V
0
0
1
2
3
4
5
VI − V
Figure 6-1. Typical Ron as a Function of Input Voltage (VI) for VI = 0 To VCC
8
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7 Parameter Measurement Information
VCC
SW
VCC
S
S
1
VIL
2
VIH
VIL or VIH
1
B1
SW
B2
VO
2
A
VI = VCC or GND
GND
IO
r on +
V
Ť
Ť
VI * VO
W
IO
VI – VO
Figure 7-1. ON-State Resistance Test Circuit
VCC
VIL or VIH
S
SW
VCC
B1
VI
A
1
VIL
2
VIH
1
SW
B2
S
VO
2
A
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 7-2. OFF-State Switch Leakage-Current Test Circuit
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VCC
S
VIL or VIH
SW
VCC
B1
VI
1
VIL
2
VIH
1
SW
B2
S
VO
VO = Open
2
A
A
GND
VI = VCC or GND
Figure 7-3. ON-State Switch Leakage-Current Test Circuit
10
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VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
VM
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VCC/2
VCC/2
VCC/2
VCC/2
VLOAD
2´
2´
2´
2´
VCC
VCC
VCC
VCC
CL
RL
VD
50 pF
50 pF
50 pF
50 pF
500 W
500 W
500 W
500 W
0.3 V
0.3 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10-MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-4. Load Circuit and Voltage Waveforms
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VCC
SW
VCC
S
S
1
VIL
2
VIH
VIL or VIH
1
B1
SW
B2
2
RL
50 Ω
A
GND
fin
VO
50 Ω
Figure 7-5. Frequency Response (Switch On)
TEST CONDITION
S
VCC
VIL or VIH
VIL
20log10(VO2/VI)
VIH
20log10(VO1/VI)
VCC
S
VB1
B1
fin
VB2
A
Analyzer
B2
GND
50 Ω
RL
50 Ω
Figure 7-6. Crosstalk (Between Switches)
VCC
S
VIL or VIH
VCC
B1
SW
S
1
VIL
2
VIH
1
SW
Analyzer
B2
A
GND
fin
2
RL
50 Ω
50 Ω
Figure 7-7. Feedthrough
12
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VCC
VCC
S
1
B1
Logic
Input
RGEN
SW
B2
2
VGE
A
VOUT
GND
RL
CL
RL/CL = 1 MΩ/100 pF
Logic
Input
OFF
ON
OFF
∆VOUT
VOUT
Q = (∆VOUT)(CL)
Figure 7-8. Charge-Injection Test
VCC
VCC
S
VIL or VIH
SW
B1
1
S
1
VIL
2
VIH
10 µF
SW
B2
A
2
VO
RL
10 kΩ
CL
50 pF
GND
fin
VCC/2
600 Ω
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
VCC = 4.50 V, VI = 4.0 VP-P
Figure 7-9. Total Harmonic Distortion
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VCC
VCC
S
B1
VO
VI = VCC/2
B2
A
GND
VS
RL
CL
RL/CL = 50 Ω/35 pF
VO
0.9 y VO
tB-M
Figure 7-10. Break-Before-Make Internal Timing
14
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8 Detailed Description
8.1 Overview
The SN74LVC1G3157-Q1 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to
5.5-V
VCC operation. The SN74LVC1G3157-Q1 device can handle analog and digital signals. The device permits
signals with amplitudes of up to VCC (peak) to be transmitted in either direction.
8.2 Functional Block Diagram
B2
1
6
4
S
B1
A
3
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
These devices are qualified for automotive applications. The 1.65-V to 5.5-V supply operation allows the device
to function in many different systems comprised of different logic levels, allowing rail-to-rail signal switching.
Either the B1 channel or the B2 channel is activated depending upon the control input. If the control input is low,
B1 channel is selected. If the control input is high, B2 channel is selected.
8.4 Device Functional Modes
Table 8-1 lists the ON channel when one of the control inputs is selected.
Table 8-1. Function Table
CONTROL
INPUTS
ON
CHANNEL
L
B1
H
B2
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G3157-Q1 SPDT analog switch is flexible enough for use in a variety of circuits such as analog
audio routing, power-up monitor, memory sharing and so on. For details on the applications, you can also view
SCYB014.
9.2 Typical Application
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
The inputs can be analog or digital, but TI recommends waiting until VCC has ramped to a level in Section 6.3
before applying any signals. Appropriate termination resistors should be used depending on the type of signal
and specification. The Select pin should not be left floating; either pull up or pull down with a resistor that can be
overdriven by a GPIO.
16
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9.2.2 Detailed Design Procedure
Using this circuit idea, a system designer can ensure a component or subsystem power has ramped up before
allowing signals to be applied to its input. This is useful for integrated circuits that do not have overvoltage
tolerant inputs. The basic idea uses a resistor divider on the VCC1 power rail, which is ramping up. The RC
time constant of the resistor divider further delays the voltage ramp on the select pin of the SPDT bus switch.
By carefully selecting values for R1, R2 and C, it is possible to ensure that VCC1 will reach its nominal value
before the path from A to B2 is established, thus preventing a signal being present on an I/O before the device/
system is powered up. To ensure the minimum desired delay is achieved, the designer should use Equation 1 to
calculate the time required from a transition from ground (0 V) to half the supply voltage (VCC1/2).
§ R2
·
u VCC1 ! VIH ¸ of the select pin
Set ¨
R1
R2
©
¹
(1)
Choose Rs and C to achieve the desired delay.
When Vs goes high, the signal will be passed.
9.2.3 Application Curve
Figure 9-2. VS Voltage Ramp
10 Power Supply Recommendations
Most systems have a common 3.3-V or 5-V rail that can supply the VCC pin of this device. If this is not available,
a Switch-Mode-Power-Supply (SMPS) or a Linear Dropout Regulator (LDO) can be used to provide supply to
this device from another voltage rail.
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11 Layout
11.1 Layout Guidelines
TI recommends keeping signal lines as short as possible. TI also recommends incorporating microstrip or
stripline techniques when signal lines are greater than 1 inch in length. These traces must be designed with a
characteristic impedance of either 50 Ω or 75 Ω, as required by the application. Do not place this device too
close to high-voltage switching components, as they may interfere with the device.
11.2 Layout Example
Figure 11-1. Recommended Layout Example
18
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches product overview
• Texas Instruments, SN74LVC1G3157-Q1 Functional Safety, FIT Rate, FMD, and Pin FMA report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
1P1G3157QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CC5O
1P1G3157QDCKRQ1
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C5O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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