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2N7001T
SCES888B – MAY 2018 – REVISED MARCH 2020
2N7001T Single-Bit Dual-Supply Buffered Voltage Signal Converter
1 Features
3 Description
•
•
•
The 2N7001T is a single-bit buffered voltage signal
converter that uses two separate configurable powersupply rails to up or down translate a unidirectional
signal. The device is operational with both VCCA and
VCCB supplies down to 1.65 V and up to 3.60 V. VCCA
defines the input threshold voltage on the A input.
VCCB defines the output drive voltage on the B output.
1
•
•
•
•
•
Up and down translation across 1.65 V to 3.6 V
Operating temperature: –40°C to +125°C
Maximum quiescent current (ICCA + ICCB) of 14 µA
(125°C maximum)
Up to 100 Mbps support across the full supply
range
VCC isolation feature
– If either VCC input is below 100 mV, the output
becomes high-impedance
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 100 mA per JESD
78, Class II
ESD protection exceeds JESD 22
– 2000-V Human body model
– 1000-V Charged-device model
The VCC isolation feature ensures that if either VCCA
or VCCB is less than 100 mV, the output port (B)
enters a high-impedance state.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that is
biased to a specific voltage while the device is
powered down.
MCU/FPGA/processor GPIO translation
Communications modules to processor translation
Push-pull I/O buffering
PACKAGE
BODY SIZE (NOM)
2N7001TDCK
SC70 (5)
2.00 mm × 1.25 mm
2N7001TDPW
X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram and Pin Configuration
VCCA
VCCB
DPW Package
DCK Package
2N7001T
A
B
ESD
ESD
5 VCCA
A 1
GND
B
1
VCCB
2
GND
3
5
VCCA
4
A
3
VCCB 2
4 B
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
2N7001T
SCES888B – MAY 2018 – REVISED MARCH 2020
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information .................. 8
8
Detailed Description .............................................. 9
7.1 Load Circuit and Voltage Waveforms ....................... 8
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2018) to Revision B
•
Changed VILMAX from VCCA × 0.65 to VCCA × 0.35 ................................................................................................................ 5
Changes from Original (May 2018) to Revision A
•
2
Page
Page
Changed from Advanced Information to Production Data ..................................................................................................... 1
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5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
B
1
5
DPW Package
5-Pin X2SON
Transparent Top View
VCCA
A
VCCA
GND
VCCB
2
GND
3
VCCB
4
B
A
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
DCK
DPW
A
4
1
I
Data Input. This pin is referenced to VCCA.
B
1
4
O
Data Output. This pin is referenced to VCCB.
VCCA
5
5
—
Input Supply voltage. 1.65V ≤ VCCA ≤ 3.6 V.
VCCB
2
2
—
Output Supply voltage. 1.65V ≤ VCCB ≤ 3.6 V.
GND
3
3
—
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCCA
Supply voltage, A Port
–0.5
4.2
V
VCCB
Supply voltage, B Port
–0.5
4.2
V
VI
Input voltage (2)
–0.5
4.2
V
VO
Voltage applied to the output in the high-impedance or power-off state (2)
–0.5
4.2
V
–0.5
(2) (3)
VO
Voltage applied to the output in the high or low state
VCCB + 0.2
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
–50
50
mA
IO
Continuous current through VCCB or GND
–50
50
mA
IO
Continuous current through VCCA
–10
10
mA
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA Supply voltage, VCCA
1.65
3.6
V
VCCB Supply voltage, VCCB
1.65
3.6
V
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VCCA = 1.65 V - 1.95 V
VCCA × 0.65
VCCA = 2.30 V - 2.70 V
1.60
VCCA = 3.00 V - 3.60 V
2.00
V
VCCA = 1.65 V - 1.95 V
VCCA × 0.35
VCCA = 2.30 V - 2.70 V
0.70
VCCA = 3.00 V - 3.60 V
VO
Output voltage
0.80
0
3.6
Active state
0
VCCB
Tri-state
0
3.6
Δt/Δv Input transition rise or fall rate
TA
V
Operating free-air temperature
–40
V
V
100
ns/V
125
°C
6.4 Thermal Information
2N7001T
THERMAL METRIC (1)
DCK (SC70)
DPW (X2SON)
UNIT
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
253.5
462.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
162.6
227.7
°C/W
RθJB
Junction-to-board thermal resistance
140.6
326.5
°C/W
ψJT
Junction-to-top characterization parameter
69.8
33.8
°C/W
ψJB
Junction-to-board characterization parameter
139.7
325.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
1.65 V - 3.6 V
1.65 V - 3.6 V
IOH = –8 mA
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
2.3
IOH = –100 µA
High-level
output voltage
VOH
Low-level
output voltage
VOL
Ioff
Partial power
down current
ICCA
VCCA supply
current
VCCB supply
current
ICCB
ICCA + Combined
ICCB
supply current
VI = VIH
VI = VIL
TYP (1)
MIN
MAX
V
IOH = –12 mA
3V
3V
IOL = 100 µA
1.65 V - 3.6 V
1.65 V - 3.6 V
0.1
IOL = 8 mA
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
VI or VO = 0 V - 3.6 V
0V
0 V - 3.6 V
–8
8
VI or VO = 0 V - 3.6 V
0 V - 3.6 V
0V
–8
8
1.65 V - 3.6 V
1.65 V - 3.6 V
0V
3.6 V
3.6 V
0V
8
1.65 V - 3.6 V
1.65 V - 3.6 V
8
0V
3.6 V
3.6 V
0V
1.65 V - 3.6 V
1.65 V - 3.6 V
VI = VCCA or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
UNIT
VCCB - 0.1
V
0.7
µA
8
–8
µA
8
µA
14
µA
–8
CI
Input
capacitance
VI = 1.65 V DC + 1MHz -16 dBm sine
wave
3.3 V
0V
2
pF
CO
Output
capacitance
VI = 1.65 V DC + 1MHz -16 dBm sine
wave
0V
3.3 V
4
pF
(1)
All typical values are for TA = 25°C
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA= 1.80 ± 0.15 V
tpd
Propagation Delay
VCCA= 2.50 ± 0.20 V
VCCA = 3.30 ± 0.30 V
MIN
MAX
VCCB = 1.80 ± 0.15 V
0.5
20
VCCB = 2.50 ± 0.20 V
0.5
17
VCCB = 3.30 ± 0.30 V
0.5
14
VCCB = 1.80 ± 0.15 V
0.5
18
VCCB = 2.50 ± 0.20 V
0.5
15
VCCB = 3.30 ± 0.30 V
0.5
12
VCCB = 1.80 ± 0.15 V
0.5
16
VCCB = 2.50 ± 0.20 V
0.5
13
VCCB = 3.30 ± 0.30 V
0.5
10
UNIT
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
CpdA
CpdB
6
Power dissipation
capacitance - Port A
Power dissipation
capacitance - B Port
TEST CONDITIONS
MIN
TYP
IO = 0 mA
CL = 0 pF,
f = 1 MHz,
tr = tf = 1 ns
VCCA = VCCB = 1.8 V
1
VCCA = VCCB = 2.5 V
1.3
VCCA = VCCB = 3.3 V
1.8
IO = 0 mA
CL = 0 pF,
f = 1 MHz,
tr = tf = 1 ns
VCCA = VCCB = 1.8 V
12
VCCA = VCCB = 2.5 V
15
VCCA = VCCB = 3.3 V
18
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MAX
UNIT
pF
pF
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6.8 Typical Characteristics
Output Low Voltage (VOL) vs. Output Low Current (IOL)
VCCA = VCCB = 1.8V, TA = 25qC
1.85
0.4
1.8
0.35
Output Low Voltage (VOL) [V]
Output High Voltage (VOH) [V]
Output High Voltage (VOH) vs. Output High Current (IOH)
VCCA = VCCB = 1.8 V, TA = 25qC
1.75
1.7
1.65
1.6
1.55
1.5
0.2
0.15
0.1
0
-7
-6
-5
-4
-3
-2
Output High Current (IOH) [mA]
-1
0
0
1
2
3
4
5
6
Output Low Current (IOL) [mA]
VOH1
7
8
VOL1
Figure 1. VOH vs IOH, 1.8 V
Figure 2. VOL vs IOL, 1.8 V
Output High Voltage (VOH) vs. Output High Current (IOH)
VCCA = VCCB = 2.5V, TA = 25qC
Output Low Voltage (VOL) vs. Output Low Current (IOL)
VCCA = VCCB = 2.5V, TA = 25qC
2.55
0.4
2.5
0.35
Output Low Voltage (VOL) [V]
Output High Voltage (VOH) [V]
0.25
0.05
1.45
-8
2.45
2.4
2.35
2.3
2.25
2.2
0.3
0.25
0.2
0.15
0.1
0.05
2.15
-9
0
-8
-7
-6
-5
-4
-3
-2
Output High Current (IOH) [mA]
-1
0
0
1
2
VOH2
3
4
5
6
7
Output Low Current (IOL) [mA]
8
Figure 3. VOH vs IOH, 2.5 V
Figure 4. VOL vs IOL, 2.5 V
Output Low Voltage (VOL) vs. Output Low Current (IOL)
VCCA = VCCB = 3.3V, TA = 25qC
3.35
0.5
3.3
0.45
3.25
3.2
3.15
3.1
3.05
3
2.95
2.9
2.85
-12 -11 -10
9
VOL2
Output High Voltage (VOH) vs. Output High Current (IOH)
VCCA = VCCB = 3.3V, TA = 25qC
Output Low Voltage (VOL) [V]
Output High Voltage (VOH) [V]
0.3
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-9 -8 -7 -6 -5 -4 -3
Output High Current (IOH) [mA]
-2
-1
0
0
1
VOH3
Figure 5. VOH vs IOH, 3.3 V
2
3
4
5
6
7
8
9
Output Low Current (IOL) [mA]
10
11
12
VOL3
Figure 6. VOL vs IOL, 3.3 V
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤ 1 ns/V
Measurement Point
Output Pin
Under Test
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 7. Load Circuit
Table 1. Load Circuit Conditions
Parameter
tpd
Propagation (delay) time
VCC
RL
CL
1.65 V – 3.6 V
2 kΩ
15 pF
VCCA
Input A
VCCA / 2
VCCA / 2
0V
tpd
tpd
VOH(2)
Output B
VCCB / 2
VCCB / 2
VOL(2)
(1)
VCCI is the supply pin associated with the input port.
(2)
VOH and VOL are typical output voltage levels that occur with specified RL and CL.
Figure 8. Propagation Delay
8
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8 Detailed Description
8.1 Overview
The 2N7001T is a single-bit dual-supply buffered voltage signal converter that can be used to up or downtranslate a single unidirectional signal. The device is operational with both VCCA and VCCB supplies down to 1.65
V and up to 3.60 V. VCCA defines the input threshold voltage on the A input while VCCB defines the output voltage
on the B output.
8.2 Functional Block Diagram
VCCA
VCCB
2N7001T
A
B
ESD
ESD
GND
8.3 Feature Description
8.3.1 Up-Translation or Down-Translation from 1.65 V to 3.60 V
The VCCA and VCCB pins can both be supplied by a voltage range from 1.65 V to 3.6 V. This voltage range makes
the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, and 3.3 V).
8.3.2 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in the Absolute Maximum Raings must be followed at all
times.
8.3.3 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance shown in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, shown in the Absolute Maximum Ratings, and the maximum input leakage current, shown in the
Electrical Characteristics, using Ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
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Feature Description (continued)
8.3.4 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in Figure 9.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 9. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.5 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input pin or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.6 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the input supply voltage (VCCA), as long as they remain below
the maximum input voltage value specified in the Recommended Operating Conditions.
8.4 Device Functional Modes
Table 2 lists the functional modes of the 2N7001T device.
Table 2. Function Table
10
INPUT
OUTPUT
L (Referenced to VCCA)
L (Referenced to VCCB)
H (Referenced to VCCA)
H (Referenced to VCCB)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The 2N7001T device can be used in level-translation applications for interfacing between devices or systems that
are operating at different interface voltages.
9.2 Typical Applications
9.2.1 Processor Error Up Translation
Figure 10 shows an example of the 2N7001T being used in a unidirectional logic level-shifting application.
1.8 V
3.3 V
2N7001T
VCCA
Processor
PROC
ERR
VCCB
A
B
ESD
ESD
PROC
ERR
System
Controller
GND
Figure 10. Processor Error Up Translation Application
9.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage supply
1.8 V
Output voltage supply
3.3 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– The supply voltage of the upstream device (device that is driving input pin A) will determine the
appropriate input voltage range. For a valid logic-high, the value must exceed the high-level input voltage
(VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of
the input port.
• Output voltage range
– The supply voltage of the downstream device (device that output pin B is driving) will determine the
appropriate output voltage range.
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9.2.1.3 Application Curve
A Data Input = 1.8V
B Data Output = 3.3V
Figure 11. Up Translation (1.8 V to 3.3 V) at 1 MHz
9.2.2 Discrete FET Translation Replacement
The 2N7001T device is an excellent option for replacing discrete translators, as shown in Figure 12, and has the
following benefits regarding discrete translation implementations:
•
•
•
•
•
•
•
A single device vs a four component solution
Minimized implementation size
Lower power consumption
VCC isolation feature
Higher data rates
Integrated ESD protection
Improved glitch performance
Discrete Translator: Four Component,
Push-Pull Translation w/o ESD Protection
2N7001T: Single Small Footprint Device,
Low Power Translation with ESD Protection
DPW Package
0603
Res.
GND
SOT23
FET
A
VCCB
VCCA
B
Solution Size: 0.64mm2
DCK Package
SOT23
FET
SOT23
FET
B
1
VCCB
2
GND
3
5
VCCA
4
A
Solution Size: 4.2mm2
Solution Size: ~ 60mm2
Figure 12. Discrete Translation vs. 2N7001T Solution
12
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10 Power Supply Recommendations
The 2N7001T device uses two separate configurable power-supply rails, VCCA and VCCB. The VCCA and VCCB
power-supply rails accept any supply voltage that range from 1.65 V to 3.6 V. The A input and B output are
referenced to VCCA and VCCB respectively allowing up or down translation among the 1.8-V, 2.5-V, and 3.3-V
voltage nodes. A 0.1 µF bypass capacitor is recommended on all VCC pins.
Always apply a ground reference to the GND pin first. However, there are no additional requirement for power
supply sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, follow the common printed-circuit board layout guidelines listed below:
• Use bypass capacitors on power supplies.
• Use short trace lengths to avoid excessive loading.
An example layout is given in Figure 13 for the DPW (X2SON-5) package. This example layout includes two
0402 (metric) capacitors, and uses the measurements that are in the package outline drawing appended to the
end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via
can be used to trace out the center pin connection through another board layer, or the via can be left out of the
layout.
11.2 Layout Example
A
8 mil
VCCB
VCCA
8 mil
B
8 mil
0402
0.1 …F
Bypass
Capacitor
4 mil
G
N
D
8 mil
4 mil
0402
0.1 …F
Bypass
Capacitor
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK,
TYP
Figure 13. Example Layout for the DPW (X2SON-5) Package
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Product Folder Links: 2N7001T
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2N7001T
SCES888B – MAY 2018 – REVISED MARCH 2020
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Designing and Manufacturing with TI's X2SON Packages application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Product Folder Links: 2N7001T
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
2N7001TDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
DQ
2N7001TDPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
DP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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