551600075-001/NOPB

User's Guide SNOA520A – March 2008 – Revised May 2013 AN-1812 ADC Driver Evaluation Boards 1 General Description The ADC driver evaluation boards are designed to aid in the characterization of high-speed operational amplifier portfolio. Utilize these evaluation boards as guides for high frequency layout and as tools to aid in the design of ADC driver applications. Although specifically designed for high speed op amps, these evaluation boards can be used for op amps in the following packages with the same pinout. ADC Driver Configuration Package Device Single to Single 6-Pin SOT23 LMH6611MK or LMH6618MK Single to Differential 8-Pin SOIC LMH6612MA or LMH6619MA Differential to Differential 8-Pin SOIC LMH6612MA or LMH6619MA 2 Basic Operation 2.1 Single to Single ADC Driver This architecture has a single-ended input source connected to the input of the op amp and the singleended output of the op amp can then be fed off board to the single-ended input of an ADC. Figure 1 shows the board schematic of the single to single ADC driver in a 2nd order multiple-feedback inverting configuration. The inverting configuration is preferred over the non-inverting configuration, as it offers more linear output response. The ADC driver’s cutoff frequency is found from the equation: ´ ¶0 = 1 1 2S * R2 * R3 * C2 * C3 (1) The op amp’s gain is set by the equation: GAIN = - 2.2 R2 R1 (2) Single to Differential ADC Driver The single to differential ADC driver board schematic, in Figure 2, utilizes a dual op amp to buffer a singleended source to drive an ADC with differential inputs. One of the op amps, U1A, is configured as a unity gain buffer that drives the inverting (IN−) input of the op amp U1B and the non-inverting (IN+) input of the ADC. U1B inverts the input signal and drives the inverting input of the ADC. The ADC driver is configured for a gain of +2 to reduce the noise without sacrificing THD performance. The common mode voltage of 2.5V is supplied at the non-inverting inputs of both op amps U1A and U1B. This configuration produces differential ±2.5 VPP output signals, when the single-ended input signal of 0 to VREF is AC coupled into the non-inverting terminal of the op amp and each non-inverting terminal of the op amp is biased at the midscale of 2.5V. The two output RC anti-aliasing filters are used between the outputs of both U1A and U1B and the inputs of the ADC to minimize the effect of undesired high frequency noise coming from the input source. Each RC filter’s cutoff frequency is found from the equation: ´ ¶0 = 1 2SRC (3) All trademarks are the property of their respective owners. SNOA520A – March 2008 – Revised May 2013 Submit Documentation Feedback AN-1812 ADC Driver Evaluation Boards Copyright © 2008–2013, Texas Instruments Incorporated 1 Basic Operation www.ti.com J1 C1 R2 R1 IN+ R3 RIN C2 + V C3 V + C4 J4 V + R4 4 3 J5 C6 C7 C5 + 6 U1 R8 1 J2 OUT + C8 2 R5 GND Figure 1. Single to Single ADC Driver Board Schematic A sample Bill of Material (BOM) for a single to single ADC driver board is given in Table 1. The ADC driver will have a cutoff frequency of 500 kHz and a gain of -1. Table 1. Bill of Material 2 Designator Description Comment C1 0805 Capacitor 1 µF C2 0805 Capacitor 150 pF C3 0805 Capacitor 1 nF C4 0603 Capacitor 0.1 µF C5 Tantalum Capacitor 6.8 µF C6 0805 Capacitor 5.6 µF C7 0805 Capacitor 0.1 µF C8 0805 Capacitor 220 pF J1 SMA Connector IN+ J2 SMA Connector OUT J4, J5 Test Point Test Point R1, R2 0805 Capacitor 549 R3 0805 Capacitor 1.24k R4, R5 0805 Capacitor 14.3k R8 0805 Capacitor 22 RIN 0805 Capacitor 50 U1 6-Pin SOT23 LMH6611/LMH6618 AN-1812 ADC Driver Evaluation Boards Copyright © 2008–2013, Texas Instruments Incorporated SNOA520A – March 2008 – Revised May 2013 Submit Documentation Feedback Basic Operation www.ti.com + V 5V REF C2 8 2 ANALOG INPUT R1 C1 3 J1 R9 4 R2 + 1 U1A + C3 GND R7 R3 J5 1 R6 J2 V C4 + 6 R4 J3 5 5V REF U1B R8 7 + C5 R5 J4 IN+ 2 GND 3 IN- 5V REF Figure 2. Single to Differential ADC Driver Board Schematic A sample Bill of Material (BOM) for a single to differential ADC driver board is given in Table 2. Table 2. Bill of Materials Designator Description Comment C1 0805 Capacitor 10 µF C2 0805 Capacitor 0.1 µF C3 Tantalum Capacitor 6.8 µF C4, C5 0805 Capacitor 220 pF J1 SMA Connector Analog Input J2, J3, J4 Test Point Test Point J5 SIP3 Out R1, R2, R4, R5 0805 Capacitor 2.5k R3, R6 0805 Capacitor 560 R7, R8 0805 Capacitor 33 R9 0805 Capacitor 50 U1 8-Pin SOIC LMH6612/LMH6619 SNOA520A – March 2008 – Revised May 2013 Submit Documentation Feedback AN-1812 ADC Driver Evaluation Boards Copyright © 2008–2013, Texas Instruments Incorporated 3 Basic Operation 2.3 www.ti.com Differential to Differential ADC Driver A dual op amp can be configured as a differential to differential ADC driver to buffer a differential source to a differential input ADC, as shown in Figure 3. The differential to differential ADC driver can be formed using two single to single ADC drivers. Each output from these drivers goes to a separate input of the differential ADC. Each single to single ADC driver uses the same components and is in a multi-feedback inverting configuration. IN+ C1 R2 R1 J1 R13 R5 C5 + V V + C3 C10 C7 2 R6 3 C11 + 8 - R11 1 U1A + C13 4 C8 J2 1 R7 GND 2 3 IN+ C2 R4 R3 IN+ GND IN- R12 J3 C14 R14 R8 C6 + V + V C4 C10 C7 6 R9 J4 + V 5 J5 C12 R10 C9 + 8 U1B 7 + 4 GND Figure 3. Differential to Differential ADC Driver Board Schematic 4 AN-1812 ADC Driver Evaluation Boards Copyright © 2008–2013, Texas Instruments Incorporated SNOA520A – March 2008 – Revised May 2013 Submit Documentation Feedback Measurement Hints www.ti.com A sample Bill of Material (BOM) for a differential to differential ADC driver board is given in Table 3. The ADC driver will have a cutoff frequency of 500 kHz and a gain of -1. Table 3. Bill of Materials 3 Designator Description Comment C1, C2 0805 Capacitor 1 µF C3, C4 0805 Capacitor 1 nF C5, C6 0603 Capacitor 150 pF C7, C8, C9 0805 Capacitor 0.1 µF C10 Tantalum Capacitor 6.8 µF C11, C12 0805 Capacitor 5.6 µF C13, C14 0805 Capacitor 220 pF J1, J3 SMA Connector IN+ J2 SIP3 Out J4, J5 Test Point Test Point R1, R2, R3, R4 0805 Capacitor 549 R5, R8 0805 Capacitor 1.24k R6, R7, R9, R10 0805 Capacitor 14.3k R11, R12 0805 Capacitor 22 R13, R14 0805 Capacitor 50 U1 8-Pin SOIC LMH6612/LMH6619 Measurement Hints It is important to connect the input source ground with the supply ground. For each ADC driver configuration, it is important to account for the impedance of the signal source when setting up the resistor networks to ensure that the differential outputs have the same gain. For example, an audio precision signal generator has about 22Ω of source impedance and the typical board termination is 50Ω, so the gain and input signal must be adjusted in order to obtain the desired signal at the output of the op amp. 4 Layout Considerations The following are recommendations for PCB layout in order to obtain the optimum high frequency performance: • Place the ADC and amplifier as close together as possible. • Put the supply bypassing capacitors as close as possible to the device (