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LM3151/LM3152/LM3153 SIMPLE SWITCHER® CONTROLLER, High Input Voltage
Synchronous Step-Down
Check for Samples: LM3151, LM3152, LM3153
FEATURES
DESCRIPTION
•
•
•
•
The LM3151/2/3 SIMPLE SWITCHER Controller is an
easy to use and simplified step down power controller
capable of providing up to 12A of output current in a
typical application. Operating with an input voltage
range from 6V-42V, the LM3151/2/3 features a fixed
output voltage of 3.3V, and features switching
frequencies of 250 kHz, 500 kHz, and 750 kHz. The
synchronous architecture provides for highly efficient
designs. The LM3151/2/3 controller employs a
Constant On-Time (COT) architecture with a
proprietary Emulated Ripple Mode (ERM) control that
allows for the use of low ESR output capacitors,
which reduces overall solution size and output
voltage ripple. The Constant On-Time (COT)
regulation architecture allows for fast transient
response and requires no loop compensation, which
reduces external component count and reduces
design complexity.
1
234
•
•
•
•
•
•
•
•
•
PowerWise™ Step-down Controller
6V to 42V Wide Input Voltage Range
Fixed Output Voltage of 3.3V
Fixed Switching Frequencies of 250 kHz/500
kHz/750 kHz
No Loop Compensation Required
Fully WEBENCH® Enabled
Low External Component Count
Constant On-Time Control
Ultra-Fast Transient Response
Stable with Low ESR Capacitors
Output Voltage Pre-bias Startup
Valley Current Limit
Programmable Soft-start
TYPICAL APPLICATIONS
•
•
•
•
•
Telecom
Networking Equipment
Routers
Security Surveillance
Power Modules
Fault protection features such as thermal shutdown,
under-voltage lockout, over-voltage protection, shortcircuit protection, current limit, and output voltage prebias startup allow for a reliable and robust solution.
The LM3151/2/3 SIMPLE SWITCHER concept
provides for an easy to use complete design using a
minimum number of external components and TI’s
WEBENCH online design tool. WEBENCH provides
design support for every step of the design process
and includes features such as external component
calculation with a new MOSFET selector, electrical
simulation, thermal simulation, and Build-It boards for
prototyping.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerWise is a trademark of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
LM3151, LM3152, LM3153
SNVS562G – SEPTEMBER 2008 – REVISED MARCH 2011
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Typical Application
EN
VCC
VIN
BST
CVCC
VIN
VIN
CBST
CIN
LM3151/2/3
M1
HG
L
VOUT
SS
SW
CSS
M2
LG
FB
COUT
PGND
SGND
Connection Diagram
1
2
3
4
5
6
7
PGND
VCC
VIN
LG
EN
BST
FB
SGND
SS
N/C
EP
HG
SW
SGND
N/C
14
13
12
11
10
9
8
Figure 1. HTSSOP-14
2
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SNVS562G – SEPTEMBER 2008 – REVISED MARCH 2011
PIN DESCRIPTIONS
Pin
Name
Description
Function
1
VCC
Supply Voltage for
FET Drivers
Nominally regulated to 5.95V. Connect a 1 µF to 2.2 µF decoupling capacitor from this pin to
ground.
2
VIN
Input Supply Voltage
Supply pin to the device. Nominal input range is 6V to 42V. See ordering information for Vin
limitations.
3
EN
Enable
4
FB
Feedback
5,9
SGND
Signal Ground
6
SS
Soft-Start
7,8
N/C
Not Connected
10
SW
Switch Node
11
HG
High-Side Gate Drive
12
BST
Connection for
Bootstrap Capacitor
High-gate driver upper supply rail. Connect a 0.33 µF-0.47 µF capacitor from SW pin to this
pin. An internal diode charges the capacitor during the high-side switch off-time. Do not
connect to an external supply rail.
13
LG
Low-Side Gate Drive
Gate drive signal to the low-side NMOS switch. The low-side gate driver voltage is supplied by
VCC.
14
PGND
Power Ground
Synchronous rectifier MOSFET source connection. Tie to power ground plane. Should be tied
to SGND at a single point.
EP
EP
Exposed Pad
Exposed die attach pad should be connected directly to SGND. Also used to help dissipate
heat out of the IC.
To enable the IC apply a logic high signal to this pin greater than 1.26V typical or leave
floating. To disable the part, ground the EN pin.
Internally connected to the resistor divider network which sets the fixed output voltage. This
pin also senses the output voltage faults such a over-voltage and short circuit conditions.
Ground for all internal bias and reference circuitry. Should be connected to PGND at a single
point.
An internal 7.7 µA current source charges an external capacitor to provide the soft-start
function.
Internally not electrically connected. These pins may be left unconnected or connected to
ground.
Switch pin of controller and high-gate driver lower supply rail. A boost capacitor is also
connected between this pin and BST pin
Gate drive signal to the high-side NMOS switch. The high-side gate driver voltage is supplied
by the differential voltage between the BST pin and SW pin.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
VIN to GND
-0.3V to 47V
SW to GND
-3V to 47V
BST to SW
-0.3V to 7V
BST to GND
-0.3V to 52V
All Other Inputs to GND
ESD Rating
-0.3V to 7V
(3)
2kV
Storage Temperature Range
(1)
(2)
(3)
-65°C to +150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test Method is per JESD-22-A114.
OPERATING RATINGS (1)
VIN
6V to 42V
−40°C to + 125°C
Junction Temperature Range (TJ)
EN
(1)
0V to 5V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
ELECTRICAL CHARACTERISTICS
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 18V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CVCC = 1 µF, 0 mA to 40 mA
5.65
5.95
6.25
V
Start-Up Regulator, VCC
VCC
IVCC = 2 mA, Vin = 5.5V
40
IVCC = 30 mA, Vin = 5.5V
330
VIN - VCC
VIN - VCC Dropout Voltage
IVCCL
VCC Current Limit
VCCUVLO
VCC Under-voltage Lockout threshold
(UVLO)
VCC Increasing
VCC-UVLO-HYS
VCC UVLO Hysteresis
VCC Decreasing
tCC-UVLO-D
VCC UVLO Filter Delay
IIN
Input Operating Current
IIN-SD
(1)
VCC = 0V
65
100
4.75
5.1
mV
mA
5.40
475
mV
3
No Switching
V
µs
3.6
5.2
mA
Input Operating Current, Device Shutdown VEN = 0V
32
55
µA
IQ-BST
Boost Pin Leakage
VBST – VSW = 6V
2
nA
RDS-HG-Pull-Up
HG Drive Pull–Up On-Resistance
IHG Source = 200 mA
5
Ω
RDS-HG-Pull-Down
HG Drive Pull–Down On-Resistance
IHG Sink = 200 mA
3.4
Ω
RDS-LG-Pull-Up
LG Drive Pull–Up On-Resistance
ILG Source = 200 mA
3.4
Ω
RDS-LG-Pull-Down
LG Drive Pull–Down On-Resistance
ILG Sink = 200 mA
2
Ω
GATE Drive
(1)
4
VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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SNVS562G – SEPTEMBER 2008 – REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 18V.
Symbol
Parameter
Conditions
Min
VSS = 0V
5.9
Typ
Max
Units
7.7
9.5
mA
Soft-Start
ISS
SS Pin Source Current
ISS-DIS
SS Pin Discharge Current
200
µA
Current Limit
VCL
Current Limit Voltage Threshold
175
200
225
mV
ON/OFF Timer
tON-MIN
ON Timer Minimum Pulse Width
200
tOFF
OFF Timer Minimum Pulse Width
370
525
ns
ns
1.20
1.26
V
Enable Input
VEN
EN Pin Input Threshold Trip Point
VEN Rising
1.14
VEN-HYS
EN Pin threshold Hysteresis
VEN Falling
120
mV
IBST = 2 mA
0.7
V
IBST = 30 mA
1
V
Boost Diode
Vf
Forward Voltage
Thermal Characteristics
TSD
Thermal Shutdown
Rising
165
°C
Thermal Shutdown Hysteresis
Falling
15
°C
4 Layer JEDEC Printed Circuit
Board, 9 Vias, No Air Flow
40
2 Layer JEDEC Printed Circuit
Board. No Air Flow
140
θJA
Junction to Ambient
θJC
Junction to Case
No Air Flow
°C/W
4
°C/W
ELECTRICAL CHARACTERISTICS 3.3V OUTPUT OPTION
Symbol
Parameter
VOUT
Output Voltage
VOUT-OV
Output Voltage Over-Voltage Threshold
VIN-MAX
VIN-MIN
fS
tON
RFB
(1)
Conditions
Maximum Input Voltage
Minimum Input Voltage
(1)
(1)
Switching Frequency
On-Time
Min
Typ
Max
Units
3.234
3.3
3.366
V
3.83
4.00
4.17
V
LM3151-3.3
42
LM3152-3.3
33
LM3153-3.3
18
LM3151-3.3
6
LM3152-3.3
6
LM3153-3.3
8
LM3151-3.3, RON = 115 kΩ
250
LM3152-3.3, RON = 51 kΩ
500
LM3153-3.3, RON = 32 kΩ
750
LM3151-3.3, RON = 115 kΩ
730
LM3152-3.3, RON = 51 kΩ
400
LM3153-3.3, RON = 32 kΩ
330
FB Resistance to Ground
566
V
V
kHz
ns
kΩ
The input voltage range is dependent on minimum on-time, off-time, and therefore frequency, and is also affected by optimized
MOSFET selection.
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SIMPLIFIED BLOCK DIAGRAM
EN
LM3151/2/3
EN
AVDD
6V
VIN
VDD
6V LDO
VIN
1.20V
0.72V
0.6V
Vbias
1 M5
VCC
CIN
UVLO
GND
VCC
THERMAL
SHUTDOWN
CVCC
1.20V
RON
BST
ON TIMER
Ron
VDD
VIN
OFF TIMER
START
COMPLETE
START
COMPLETE
CBST
ISS
HG
SS
LOGIC
CSS
DrvH
LEVEL
SHIFT
DrvL
REGULATION
COMPARATOR
FB
47 pF
PMOS
input
Vref = 0.6V
DRIVER
SW
M1
L
VOUT
VCC
DRIVER
LG
Zero
Current
Detect
M2
COUT
PGND
RFB2
RFB1
0.72V
SGND
0.36V
VOUT-OV and
SHORT
CIRCUIT
PROTECTION
CURRENT LIMIT
COMPARATOR
200 mV
PGND
ERM Control
RFB = RFB1 + RFB2
6
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SNVS562G – SEPTEMBER 2008 – REVISED MARCH 2011
TYPICAL PERFORMANCE CHARACTERISTICS
Boost Diode Forward Voltage vs. Temperature
Quiescent Current vs. Temperature
Figure 2.
Figure 3.
Soft-Start Current vs. Temperature
VCC Current Limit vs. Temperature
Figure 4.
Figure 5.
VCC Dropout vs. Temperature
VCC vs. Temperature
Figure 6.
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
8
VCL vs. Temperature
On-Time vs. Temperature (250 kHz)
Figure 8.
Figure 9.
On-Time vs. Temperature (500 kHz)
On-Time vs. Temperature (750 kHz)
Figure 10.
Figure 11.
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THEORY OF OPERATION
The LM3151/2/3 synchronous step-down SIMPLE SWITCHER Controller employs a Constant On-Time (COT)
architecture which is a derivative of the hysteretic control scheme. COT relies on a fixed switch on-time to
regulate the output. The on-time of the high-side switch is set internally by resistor RON. The LM3151/2/3
automatically adjusts the on-time inversely with the input voltage to maintain a constant frequency. Assuming an
ideal system and VIN is much greater than 1V, the following approximations can be made:
The on-time, tON:
tON =
K x RON
VIN
where
•
•
K = 100 pC
RON is specified in the electrical characteristics table
Control is based on a comparator and the on-timer, with the output voltage feedback (FB) attenuated and then
compared with an internal reference of 0.6V. If the attenuated FB level is below the reference, the high-side
switch is turned on for a fixed time, tON, which is determined by the input voltage and the internal resistor, RON.
Following this on-time, the switch remains off for a minimum off-time, tOFF, as specified in the Electrical
Characteristics table or until the attenuated FB voltage is less than 0.6V. This switching cycle will continue while
maintaining regulation. During continuous conduction mode (CCM), the switching frequency depends only on
duty cycle and on-time. The duty cycle can be calculated as:
D=
tON
VOUT
=t xf |
tON + tOFF ON S
VIN
Where the switching frequency of a COT regulator is:
fS =
VOUT
K x RON
Typical COT hysteretic controllers need a significant amount of output capacitor ESR to maintain a minimum
amount of ripple at the FB pin in order to switch properly and maintain efficient regulation. The LM3151/2/3
however utilizes proprietary, Emulated Ripple Mode Control Scheme (ERM) that allows the use of ceramic output
capacitors without additional equivalent series resistance (ESR) compensation. Not only does this reduce the
need for output capacitor ESR, but also significantly reduces the amount of output voltage ripple seen in a typical
hysteretic control scheme. The output ripple voltage can become so low that it is comparable to voltage-mode
and current-mode control schemes.
Regulation Comparator
The output voltage is sampled through the FB pin and then divided down by two internal resistors and compared
to the internal reference voltage of 0.6V by the error comparator. In normal operation, an on-time period is
initiated when the sampled output voltage at the input of the error comparator falls below 0.6V. The high-side
switch stays on for the specified on-time, causing the sampled voltage on the error comparator input to rise
above 0.6V. After the on-time period, the high-side switch stays off for the greater of the following:
1. Minimum off time as specified in the electrical characteristics table
2. The error comparator sampled voltage falls below 0.6V
Over-Voltage Comparator
The over-voltage comparator is provided to protect the output from over-voltage conditions due to sudden input
line voltage changes or output loading changes. The over-voltage comparator continuously monitors the
attenuated FB voltage versus a 0.72V internal reference. If the voltage at FB rises above 0.72V the on-time pulse
is immediately terminated. This condition can occur if the input or the output load changes suddenly. Once the
over-voltage protection is activated, the HG and LG signals remain off until the attenuated FB voltage falls below
0.72V.
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Current Limit
Current limit detection occurs during the off-time by monitoring the current through the low-side switch. If during
the off-time the current in the low-side switch exceeds the user defined current limit value, the next on-time cycle
is immediately terminated. Current sensing is achieved by comparing the voltage across the low-side switch
against an internal reference value, VCL, of 200 mV. If the voltage across the low-side switch exceeds 200 mV,
the current limit comparator will trigger logic to terminate the next on-time cycle. The current limit ICL, can be
determined as follows:
-3
VCL (Tj) = VCL x [1 + 3.3 x 10 x (Tj - 27)]
VCL (Tj)
ICL (Tj) =
RDS(ON)max
where
•
•
•
•
IOCL is the user-defined average output current limit value
RDS(ON)max is the resistance value of the low-side FET at the expected maximum FET junction temperature
VCL is the internal current limit reference voltage
Tj is the junction temperature of the LM3151/2/3
Figure 12 illustrates the inductor current waveform. During normal operation, the output current ripple is dictated
by the switching of the FETs. The current through the low-side switch, Ivalley, is sampled at the end of each
switching cycle and compared to the current limit threshold voltage, VCL. The valley current can be calculated as
follows:
Ivalley = IOUT -
'IL
2
where
•
•
IOUT is the average output current
ΔIL is the peak-to-peak inductor ripple current
If an overload condition occurs, the current through the low-side switch will increase which will cause the current
limit comparator to trigger the logic to skip the next on-time cycle. The IC will then try to recover by checking the
valley current during each off-time. If the valley current is greater than or equal to ICL, then the IC will keep the
low-side FET on and allow the inductor current to further decay.
Throughout the whole process, regardless of the load current, the on-time of the controller will stay constant and
thereby the positive ripple current slope will remain constant. During each on-time the current ramps up an
amount equal to:
'I =
(VIN - VOUT) x tON
L
The valley current limit feature prevents current runaway conditions due to propagation delays or inductor
saturation since the inductor current is forced to decay following any overload conditions.
IPK
'I
IOCL
Inductor Current
ICL
IOUT
Normal Operation
Load Current
Increases
Current Limited
Figure 12. Inductor Current - Current Limit Operation
10
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Short-Circuit Protection
The LM3151/2/3 will sense a short-circuit on the output by monitoring the output voltage. When the attenuated
feedback voltage has fallen below 60% of the reference voltage, Vref x 0.6 (≈ 0.36V), short-circuit mode of
operation will start. During short-circuit operation, the SS pin is discharged and the output voltage will fall to 0V.
The SS pin voltage, VSS, is then ramped back up at the rate determined by the SS capacitor and ISS until VSS
reaches 0.7V. During this re-ramp phase, if the short-circuit fault is still present the output current will be equal to
the set current limit. Once the soft-start voltage reaches 0.7V the output voltage is sensed again and if the
attenuated VFB is still below Vref x 0.6 then the SS pin is discharged again and the cycle repeats until the shortcircuit fault is removed.
Soft-Start
The soft-start (SS) feature allows the regulator to gradually reach a steady-state operating point, which reduces
start-up stresses and current surges. At turn-on, while VCC is below the under-voltage threshold, the SS pin is
internally grounded and VOUT is held at 0V. The SS capacitor is used to slowly ramp VFB from 0V to it's final
output voltage as programmed by the internal resistor divider. By changing the soft-start capacitor value, the
duration of start-up can be changed accordingly. The start-up time can be calculated using the following
equation:
Vref x CSS
tSS =
ISS
where
•
•
•
tSS is measured in seconds
Vref = 0.6V
ISS is the soft-start pin source current, which is typically 7.7 µA (refer to electrical characteristics table)
An internal switch grounds the SS pin if VCC is below the under-voltage lockout threshold, if a thermal shutdown
occurs, or if the EN pin is grounded. By using an externally controlled switch, the output voltage can be shut off
by grounding the SS pin.
During startup the LM3151/2/3 will operate in diode emulation mode, where the low-side gate LG will turn off and
remain off when the inductor current falls to zero. Diode emulation mode allows for start up into a pre-biased
output voltage. When soft-start is greater than 0.7V, the LM3151/2/3 will remain in continuous conduction mode.
During diode emulation mode at current limit the low-gate will remain off when the inductor current is off.
The soft start time should be greater than the rise time specified by,
tSS ≥ (VOUT x COUT) / (IOCL - IOUT)
Enable/Shutdown
The EN pin can be activated by either leaving the pin floating due to an internal pull up resistor to VIN or by
applying a logic high signal to the EN pin of 1.26V or greater. The LM3151/2/3 can be remotely shut down by
taking the EN pin below 1.02V. Low quiescent shutdown is achieved when VEN is less than 0.4V. During low
quiescent shutdown the internal bias circuitry is turned off.
The LM3151/2/3 has certain fault conditions that can trigger shutdown, such as over-voltage protection, current
limit, under-voltage lockout, or thermal shutdown. During shutdown, the soft-start capacitor is discharged. Once
the fault condition is removed, the soft-start capacitor begins charging, allowing the part to start up in a controlled
fashion. In conditions where there may be an open drain connection to the EN pin, it may be necessary to add a
1000 pF bypass capacitor to this pin. This will help decouple noise from the EN pin and prevent false disabling.
Thermal Protection
The LM3151/2/3 should be operated such that the junction temperature does not exceed the maximum operating
junction temperature. An internal thermal shutdown circuit, which activates at 165°C (typical), takes the controller
to a low-power reset state by disabling the buck switch and the on-timer, and grounding the SS pin. This feature
helps prevent catastrophic failures from accidental device overheating. When the junction temperature falls back
below 150°C the SS pin is released and normal operation resumes.
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Design Guide
The design guide provides the equations required to design with the LM3151/2/3 SIMPLE SWITCHER Controller.
WEBENCH design tool can be used with or in place of this section for a more complete and simplified design
process.
1. Define Power Supply Operating Conditions
a. Maximum and Minimum DC Input voltage
b. Maximum Expected Load Current during normal operation
c. Target Switching Frequency
2. Determine which IC Controller to Use
The desired input voltage range will determine which version of the LM3151/2/3 controller will be chosen. The
higher switching frequency options allow for physically smaller inductors but efficiency may decrease.
3. Determine Inductor Required Using Figure 13
To use the nomograph below calculate the inductor volt-microsecond constant ET from the following formula:
ET = (Vinmax ± VOUT) x
VOUT
Vinmax
x 1000 (V x Ps)
fS
where
•
fS is in kHz units
The intersection of the Load Current and the Volt-microseconds lines on the chart below will determine which
inductors are capable for use in the design. The chart shows a sample of parts that can be used. The offline
calculator tools and WEBENCH will fully calculate the requirements for the components needed for the design.
47 P
100
90
80
70
60
50
L01
L13
L02
L14
H
L37
L25
L03
40
E À T (V À Ps)
33 P
H
30
L04
20
L05
L29
L42
H
3.3 P
L43
2.2 P
L44
1.5 P
L32
L45
1.0 P
L33
L46
P
0.68
L34
L47
PH
0.47
L31
L21
2
L11
L23
L12
L24
L35
6
H
6.8 P
L48
H
H
H
H
P
0.33
H
L36
1
5
H
4.7 P
L20
L22
4
L41
L30
L10
H
L28
L19
3
10 P
L40
L18
L09
4
H
L27
L17
L08
15 P
L39
L16
L07
H
L26
L15
L06
10
9
8
7
6
5
L38
22 P
7
8
9
10
12
MAXIMUM LOAD CURRENT (A)
Figure 13. Inductor Nomograph
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Table 1. Inductor Selection Table
Inductor Designator
Inductance (µH)
Current (A)
L01
47
7-9
Part Name
Vendor
L02
33
L03
22
7-9
SER2817H-333KL
COILCRAFT
7-9
SER2814H-223KL
L04
COILCRAFT
15
7-9
7447709150
WURTH
L05
10
7-9
RLF12560T-100M7R5
TDK
L06
6.8
7-9
B82477-G4682-M
EPCOS
L07
4.7
7-9
B82477-G4472-M
EPCOS
L08
3.3
7-9
DR1050-3R3-R
COOPER
L09
2.2
7-9
MSS1048-222
COILCRAFT
L10
1.5
7-9
SRU1048-1R5Y
BOURNS
L11
1
7-9
DO3316P-102
COILCRAFT
L12
0.68
7-9
DO3316H-681
COILCRAFT
L13
33
9-12
L14
22
9-12
SER2918H-223
COILCRAFT
L15
15
9-12
SER2814H-153KL
COILCRAFT
L16
10
9-12
7447709100
WURTH
L17
6.8
9-12
SPT50H-652
COILCRAFT
L18
4.7
9-12
SER1360-472
COILCRAFT
L19
3.3
9-12
MSS1260-332
COILCRAFT
L20
2.2
9-12
DR1050-2R2-R
COOPER
L21
1.5
9-12
DR1050-1R5-R
COOPER
L22
1
9-12
DO3316H-102
COILCRAFT
L23
0.68
9-12
L24
0.47
9-12
L25
22
12-15
SER2817H-223KL
COILCRAFT
L26
15
12-15
L27
10
12-15
SER2814L-103KL
COILCRAFT
L28
6.8
12-15
7447709006
WURTH
L29
4.7
12-15
7447709004
WURTH
L30
3.3
12-15
L31
2.2
12-15
L32
1.5
12-15
MLC1245-152
COILCRAFT
L33
1
12-15
L34
0.68
12-15
DO3316H-681
COILCRAFT
L35
0.47
12-15
L36
0.33
12-15
DR73-R33-R
COOPER
L37
22
15-
L38
15
15-
SER2817H-153KL
COILCRAFT
L39
10
15-
SER2814H-103KL
COILCRAFT
L40
6.8
15-
L41
4.7
15-
SER2013-472ML
COILCRAFT
L42
3.3
15-
SER2013-362L
COILCRAFT
L43
2.2
15-
L44
1.5
15-
HA3778-AL
COILCRAFT
L45
1
15-
B82477-G4102-M
EPCOS
L46
0.68
15-
L47
0.47
15-
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Table 1. Inductor Selection Table (continued)
Inductor Designator
Inductance (µH)
Current (A)
L48
0.33
15-
Part Name
Vendor
4. Determine Output Capacitance
Typical hysteretic COT converters similar to the LM3151/2/3 require a certain amount of ripple that is generated
across the ESR of the output capacitor and fed back to the error comparator. Emulated Ripple Mode control built
into the LM3151/2/3 will recreate a similar ripple signal and thus the requirement for output capacitor ESR will
decrease compared to a typical Hysteretic COT converter. The emulated ripple is generated by sensing the
voltage signal across the low-side FET and is then compared to the FB voltage at the error comparator input to
determine when to initiate the next on-time period.
COmin = 70 / (fs2 x L)
(1)
The maximum ESR allowed to prevent over-voltage protection during normal operation is:
ESRmax = (80 mV x L) / ETmin
ETmin is calculated using VIN-MIN
The minimum ESR must meet both of the following criteria:
ESRmin ≥ (15 mV x L) / ETmax
ESRmin ≥ [ETmax / (VIN - VOUT)]/ CO
ETmax is calculated using VIN-MAX.
Any additional parallel capacitors should be chosen so that their effective impedance will not negatively attenuate
the output ripple voltage.
5. MOSFET Selection
The high-side and low-side FETs must have a drain to source (VDS) rating of at least 1.2 x VIN.
The gate drive current from VCC must not exceed the minimum current limit of VCC. The drive current from VCC
can be calculated with:
IVCCdrive = Qgtotal x fS
where
•
Qgtotal is the combined total gate charge of the high-side and low-side FETs
Use the following equations to calculate the current limit, ICL, as shown in Figure 12.
-3
VCL (Tj) = VCL x [1 + 3.3 x 10 x (Tj - 27)]
VCL (Tj)
ICL (Tj) =
RDS(ON)max
where
•
Tj is the junction temperature of the LM3151/2/3
The plateau voltage of the FET VGS vs Qg curve, as shown in Figure 14 must be less than VCC - 750 mV.
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Figure 14. Typical MOSFET Gate Charge Curve
See following design example for estimated power dissipation calculation.
6. Calculate Input Capacitance
The main parameters for the input capacitor are the voltage rating, which must be greater than or equal to the
maximum DC input voltage of the power supply, and its rms current rating. The maximum rms current is
approximately 50% of the maximum load current.
CIN =
Iomax x D x (1-D)
fs x 'VIN-MAX
where
ΔVIN-MAX is the maximum allowable input ripple voltage
•
A good starting point for the input ripple voltage is 5% of VIN.
When using low ESR ceramic capacitors on the input of the LM3151/2/3 a resonant circuit can be formed with
the impedance of the input power supply and parasitic impedance of long leads/PCB traces to the LM3151/2/3
input capacitors. It is recommended to use a damping capacitor under these circumstances, such as aluminum
electrolytic that will prevent ringing on the input. The damping capacitor should be chosen to be approximately 5
times greater than the parallel ceramic capacitors combination. The total input capacitance should be greater
than 10 times the input inductance of the power supply leads/pcb trace. The damping capacitor should also be
chosen to handle its share of the rms input current which is shared proportionately with the parallel impedance of
the ceramic capacitors and aluminum electrolytic at the LM3151/2/3 switching frequency.
The CBYP capacitor should be placed directly at the VIN pin. The recommended value is 0.1 µF.
7. Calculate Soft-Start Capacitor
ISS x tSS
Vref
CSS =
where
•
•
tSS is the soft-start time in seconds
Vref = 0.6V
8. CVCC, and CBST and CEN
CVCC should be placed directly at the VCC pin with a recommended value of 1 µF to 2.2 µF. For input voltage
ranges that include voltages below 8V a 1 µF capacitor must be used for CVCC. CBST creates a voltage used to
drive the gate of the high-side FET. It is charged during the SW off-time. The recommended value for CBST is
0.47 µF. The EN bypass capacitor, CEN, recommended value is 1000 pF when driving the EN pin from open
drain type of signal.
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Design Example
VIN
VCC
EN
CVCC
CEN
VIN
VIN
M1
HG
CBYP
LM3151/2/3
CIN
BST
CBST
L
SS
VOUT
SW
CSS
COUT
FB
LG
SGND
M2
PGND
Figure 15. Design Example Schematic
1.Define Power Supply Operating Conditions
a. VOUT = 3.3V
b. VIN-MIN = 6V, VIN-TYP = 12V, VIN-MAX = 24V
c. Typical Load Current = 12A, Max Load Current = 15A
d. Soft-Start time tSS = 5 ms
2. Determine which IC Controller to Use
The LM3151 and LM3152 allow for the full input voltage range. However, from buck converter basic theory, the
higher switching frequency will allow for a smaller inductor. Therefore, the LM3152-3.3 500 kHz part is chosen so
that a smaller inductor can be used.
3. Determine Inductor Required
a. ET = (24-3.3) x (3.3/24) x (1000/500) = 5.7 V µs
b. From the inductor nomograph a 12A load and 5.7 V µs calculation corresponds to a L44 type of inductor.
c. Using the inductor designator L44 in Table 1 the Coilcraft HA3778-AL 1.65 µH inductor is chosen.
4. Determine Output Capacitance
The voltage rating on the output capacitor should be greater than or equal to the output voltage. As a rule of
thumb most capacitor manufacturers suggests not to exceed 90% of the capacitor rated voltage. In the case of
multilayer ceramics the capacitance will tend to decrease dramatically as the applied voltage is increased
towards the capacitor rated voltage. The capacitance can decrease by as much as 50% when the applied
voltage is only 30% of the rated voltage. The chosen capacitor should also be able to handle the rms current
which is equal to:
Irmsco = IOUT x
r
12
(2)
For this design the chosen ripple current ratio, r = 0.3, represents the ratio of inductor peak-to-peak current to
load current Iout. A good starting point for ripple ratio is 0.3 but it is acceptable to choose r between 0.25 to 0.5.
The nomographs in this datasheet all use 0.3 as the ripple current ratio.
Irmsco = 12 x
0.3
12
(3)
Irmsco = 1A
tON = (3.3V/12V) / 500 kHz = 550 ns
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Minimum output capacitance is:
COmin = 70 / (fS2 x L)
COmin = 70 / (500 kHz2 x 1.65 µH) = 169 µF
The maximum ESR allowed to prevent over-voltage protection during normal operation is:
ESRmax = (80 mV x L) / ET
ESRmax = (80 mV x 1.65 µH) / 5.7 V µs
ESRmax = 23 mΩ
The minimum ESR must meet both of the following criteria:
ESRmin ≥ (15 mV x L) / ET
ESRmin ≥ [ET / (VIN - VOUT)] / CO
ESRmin ≥ (15 mV x 1.65 µH) / 5.7 V µs = 4.3 mΩ
ESRmin ≥ [5.7 V µs / (12 - 3.3)] / 169 µF = 3.9 mΩ
Based on the above criteria two 150 µF polymer aluminum capacitors with a ESR = 12 mΩ each for a effective
ESR in parallel of 6 mΩ was chosen from Panasonic. The part number is EEF-UE0J151P.
5. MOSFET Selection
The LM3151/2/3 are designed to drive N-channel MOSFETs. For a maximum input voltage of 24V we should
choose N-channel MOSFETs with a maximum drain-source voltage, VDS, greater than 1.2 x 24V = 28.8V. FETs
with maximum VDS of 30V will be the first option. The combined total gate charge Qgtotal of the high-side and lowside FET should satisfy the following:
Qgtotal ≤ IVCCL / fs
Qgtotal ≤ 65 mA / 500 kHz
Qgtotal ≤ 130 n
(4)
(5)
where
•
IVCCL is the minimum current limit of VCC over the temperature range, specified in the electrical characteristics
table
The MOSFET gate charge Qg is gathered from reading the VGS vs Qg curve of the MOSFET datasheet at the
VGS = 5V for the high-side, M1, MOSFET and VGS = 6V for the low-side, M2, MOSFET.
The Renesas MOSFET RJK0305DPB has a gate charge of 10 nC at VGS = 5V, and 12 nC at VGS = 6V. This
combined gate charge for a high-side, M1, and low-side, M2, MOSFET 12 nC + 10 nC = 22 nC is less than 130
nC calculated Qgtotal.
The calculated MOSFET power dissipation must be less than the max allowed power dissipation, Pdmax, as
specified in the MOSFET datasheet. An approximate calculation of the FET power dissipated Pd, of the high-side
and low-side FET is given by:
High-Side MOSFET
2
Pcond = Iout x RDS(ON) x D
Psw =
8.5
6.8
1
+
x Vin x Iout x Qgd x fs x
Vcc - Vth Vth
2
Pdh = Pcond + Psw
2
Pcond = 12 x 0.01 x 0.275 = 0.396W
Psw =
8.5
6.8
1 x 12 x 12 x 1.5 nC x 500 kHz x
+
= 0.278W
6 ± 2.5 2.5
2
Pdh = 0.396 + 0.278 = 0.674W
The max power dissipation of the RJK0305DPB is rated as 45W for a junction temperature that is 125°C higher
than the case temperature and a thermal resistance from the FET junction to case, θJC, of 2.78°C/W.
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When the FET is mounted onto the PCB, the PCB will have some additional thermal resistance such that the
total system thermal resistance of the FET package and the PCB, θJA, is typically in the range of 30°C/W for this
type of FET package. The max power dissipation, Pdmax, with the FET mounted onto a PCB with a 125°C
junction temperature rise above ambient temperature and θJA = 30°C/W, can be estimated by:
Pdmax = 125°C / 30°C/W = 4.1W
The system calculated Pdh of 0.674W is much less than the FET Pdmax of 4.1W and therefore the
RJK0305DPB max allowable power dissipation criteria is met.
Low-Side MOSFET
Primary loss is conduction loss given by:
Pdl = Iout2 x RDS(ON) x (1-D) = 122 x 0.01 x (1-0.275) = 1W
Pdl is also less than the Pdmax specified on the RJK0305DPB MOSFET datasheet.
However, it is not always necessary to use the same MOSFET for both the high-side and low-side. For most
applications it is necessary to choose the high-side MOSFET with the lowest gate charge and the low-side
MOSFET is chosen for the lowest allowed RDS(ON). The plateau voltage of the FET VGS vs Qg curve must be less
than VCC - 750 mV.
The current limit, IOCL, is calculated by estimating the RDS(ON) of the low-side FET at the maximum junction
temperature of 100°C. Then the following calculation of IOCL is:
IOCL = ICL + ΔIL / 2
ICL = 200 mV / 0.014 = 14.2A
IOCL = 14.2A + 3.6 / 2 = 16A
6. Calculate Input Capacitance
The input capacitor should be chosen so that the voltage rating is greater than the maximum input voltage which
for this example is 24V. Similar to the output capacitor, the voltage rating needed will depend on the type of
capacitor chosen. The input capacitor should also be able to handle the input rms current which is approximately
0.5 x IOUT. For this example the rms input current is approximately 0.5 x 12A = 6A.
The minimum capacitance with a maximum 5% input ripple ΔVIN-MAX = (0.05 x 12) = 0.6V:
CIN = [12 x 0.275 x (1-0.275)] / [500 kHz x 0.6] = 8 µF
To handle the large input rms current 2 ceramic capacitors are chosen at 10 µF each with a voltage rating of 50V
and case size of 1210, that can handle 3A of rms current each. A 100 µF aluminum electrolytic is chosen to help
dampen input ringing.
CBYP = 0.1 µF ceramic with a voltage rating greater than maximum VIN
7. Calculate Soft-Start Capacitor
The soft start-time should be greater than the input voltage rise time and also satisfy the following equality to
maintain a smooth transition of the output voltage to the programmed regulation voltage during startup.
tSS ≥ (VOUT x COUT) / (IOCL - IOUT)
5 ms > (3.3V x 300 µF) / (1.2 x 12A - 12A)
5 ms > 0.412 ms
The desired soft-start time, tSS, of 5 ms satisfies the equality as shown above. Therefore, the soft-start capacitor,
CSS, is calculated as:
CSS = (7.7 µA x 5 ms) / 0.6V = 0.064 µF
Let CSS = 0.068 µF, which is the next closest standard value. This should be a ceramic cap with a voltage rating
greater than 10V.
8. CVCC, CEN, and CBST
CVCC = 1µF ceramic with a voltage rating greater than 10V
CEN = 1000 pF ceramic with a voltage rating greater than 10V
CBST = 0.47 µF ceramic with a voltage rating greater than 10V
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Bill of Materials
Designator
Value
Parameters
Manufacturer
Part Number
CBST
0.47 µF
Ceramic, X7R, 16V, 10%
TDK
C2012X7R1C474K
CBYP
0.1 µF
Ceramic, X7R, 50V, 10%
TDK
C2012X7R1H104K
C1608X7R1H102K
CEN
1000 pF
Ceramic, X7R, 50V, 10%
TDK
CIN1
100 µF
AL, EEV-FK, 63V, 20%
Panasonic
EEV-FK1J101P
CIN2, CIN3
10 µF
Ceramic, X5R, 35V, 10%
Taiyo Yuden
GMK325BJ106KN-T
COUT1, COUT2
150 µF
AL, UE, 6.3V, 20%
Panasonic
EEF-UE0J151R
CSS
0.068 µF
Ceramic, 16V, 10%
CVCC
1 µF
Ceramic, X7R, 16V, 10%
Kemet
C0805C105K4RACTU
L1
1.65 µH
Shielded Drum Core, A, 2.53 mΩ
Coilcraft Inc.
HA3778-AL
M1, M2
30V
8 nC, RDS(ON) @4.5V = 10 mΩ
U1
0603YC683KAT2A
Renesas
RJK0305DB
Texas Instruments
LM3152MH-3.3
PCB Layout Considerations
It is good practice to layout the power components first, such as the input and output capacitors, FETs, and
inductor. The first priority is to make the loop between the input capacitors and the source of the low side FET to
be very small and tie the grounds of each directly to each other and then to the ground plane through vias. As
shown in the figure below, when the input cap ground is tied directly to the source of the low side FET, parasitic
inductance in the power path, along with noise coupled into the ground plane, are reduced.
The switch node is the next item of importance. The switch node should be made only as large as required to
handle the load current. There are fast voltage transitions occurring in the switch node at a high frequency, and if
the switch node is made too large it may act as an antennae and couple switching noise into other parts of the
circuit. For high power designs it is recommended to use a multi-layer board. The FET’s are going to be the
largest heat generating devices in the design, and as such, care should be taken to remove the heat. On multi
layer boards using exposed-pad packages for the FET’s such as the power-pak SO-8, vias should be used under
the FETs to the same plane on the interior layers to help dissipate the heat and cool the FETs. For the typical
single FET Power-Pak type FETs the high-side FET DAP is Vin. The Vin plane should be copied to the other
interior layers to the bottom layer for maximum heat dissipation. Likewise, the DAP of the low-side FET is
connected to the SW node and it’s shape should be duplicated to the interior layers down to the bottom layer for
maximum heat dissipation.
See the Evaluation Board application note AN-1900 (literature number (SNVA371) for an example of a typical
multilayer board layout, and the Demonstration Board Reference Design App Note for a typical 2 layer board
layout. Each design allows for single sided component mounting.
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VIN
M1
L
M2
CIN
COUT
Figure 16. Schematic of Parasitics
HG
D
G
D
S
M1
S
+
-
S
D
D
VIN
L
VOUT
CIN
S
xx
S
S
LG
D
D
COUT
D
G
HG
LG
xx
PGND
vias to
ground plane
D
M2
LM3151/2/3
Figure 17. PCB Placement of Power Stage
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3151MH-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3151
-3.3
LM3151MHE-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3151
-3.3
LM3151MHX-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3151
-3.3
LM3152MH-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3152
-3.3
LM3152MHE-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3152
-3.3
LM3152MHX-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3152
-3.3
LM3153MH-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3153
-3.3
LM3153MHE-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3153
-3.3
LM3153MHX-3.3/NOPB
ACTIVE
HTSSOP
PWP
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3153
-3.3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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