5962-9566602QDA

厂商：
BURR-BROWN(德州仪器)
封装：
CFlatpack14
描述：
QUAD OPERATIONAL AMPLIFIER

数据手册：

下载5962-9566602QDA.pdf

立即购买

数据手册
价格&库存

5962-9566602QDA 数据手册

 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 D D D D D D Output Swing Includes Both Supply Rails Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz Low Input Bias Current . . . 1 pA Typ Fully Specified for Both Single-Supply and Split-Supply Operation Very Low Power . . . 34 µA Per Channel Typ Common-Mode Input Voltage Range Includes Negative Rail D Low Input Offset Voltage D D D 850 µV Max at TA = 25°C Wide Supply Voltage Range 2.7 V to 8 V Macromodel Included Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards description 3 VDD = 3 V VOH − High-Level Output Voltage − V The TLV2252 and TLV2254 are dual and quadruple low-voltage operational amplifiers from Texas Instruments. Both devices exhibit rail-to-rail output performance for increased dynamic range in single- or split-supply applications. The TLV225x family consumes only 34 µA of supply current per channel. This micropower operation makes them good choices for battery-powered applications. This family is fully characterized at 3 V and 5 V and is optimized for low-voltage applications. The noise performance has been dramatically improved over previous generations of CMOS amplifiers. The TLV225x has a noise level of 19 nV/√Hz at 1kHz, four times lower than competitive micropower solutions. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.5 TA = − 40°C 2 TA = 25°C 1.5 TA = 85°C 1 ÁÁ ÁÁ TA = 125°C 0.5 The TLV225x, exhibiting high input impedance and low noise, are excellent for small-signal 0 conditioning for high-impedance sources, such as 600 800 0 200 400 piezoelectric transducers. Because of the micro| IOH | − High-Level Output Current − µ A power dissipation levels combined with 3-V Figure 1 operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV225xA family is available and has a maximum input offset voltage of 850 µV. The TLV2252/4 also make great upgrades to the TLV2322/4 in standard designs. They offer increased output dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows them to be used in a wider range of applications. For applications that require higher output drive and wider input voltage range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their small size and low power consumption, make them ideal for high density, battery-powered equipment. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments. Copyright  1997−2006, Texas Instruments Incorporated !"#$%" & '##% & "! (')* %" %+ #" ' %& "!"#$ %" &( ! %"& (# %, %#$& "! & &%#'$%& &% # -##%.+ #" ' %" (#" &&/ "& "% &&#*. *' %&%/ "! ** (#$%#&+ (#" ' %& "$(*% %" 010 ** (#$%#& # %&% '*&& "%,#-& "% + ** "%,# (#" ' %& (#" ' %" (#" &&/ "& "% &&#*. *' %&%/ "! ** (#$%#&+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C SMALL OUTLINE† (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP‡ (PW) CERAMIC FLATPACK (U) −40°C to 125°C 850 µV 1500 µV TLV2252AID TLV2252ID — — — — TLV2252AIP TLV2252IP TLV2252AIPWLE — — — −40°C to 125°C 850 µV 1500 µV TLV2252AQD TLV2252QD — — — — — — — — — — −55°C to 125°C 850 µV 1500 µV — — TLV2252AMFK TLV2252MFK TLV2252AMJG TLV2252MJG — — — — TLV2252AMU TLV2252MU † The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2252CDR). ‡ The PW package is available only left-end taped and reeled. § Chips are tested at 25°C. TLV2254 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C SMALL OUTLINE† (D) CHIP CARRIER (FK) CERAMIC DIP (J) PLASTIC DIP (N) TSSOP‡ (PW) CERAMIC FLATPACK (W) −40°C to 125°C 850 µV 1500 µV TLV2254AID TLV2254ID — — — — TLV2254AIN TLV2254IN TLV2254AIPWLE — — — −40°C to 125°C 850 µV 1500 µV TLV2254AQD TLV2254QD — — — — — — — — — — −55°C to 125°C 850 µV 1500 µV — — TLV2254AMFK TLV2254MFK TLV2254AMJ TLV2254MJ — — — — TLV2254AMW TLV2254MW † The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2254CDR). ‡ The PW package is available only left-end taped and reeled. § Chips are tested at 25°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I, TLV2252AI TLV2252Q, TLV2252AQ D, P, OR PW PACKAGE (TOP VIEW) 1 8 2 7 3 6 4 5 VDD + 2OUT 2IN − 2IN + TLV2252M, TLV2252AM . . . JG PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD − /GND 1 8 2 7 3 6 4 5 VDD + 2OUT 2IN − 2IN + TLV2252M, TLV2252AM . . . U PACKAGE (TOP VIEW) NC 1OUT 1IN − 1IN + VCC − /GND 1 NC VCC + 2OUT 2IN − 2IN + 10 2 9 3 8 4 7 5 6 5 17 6 16 7 15 14 8 9 10 11 12 13 3 12 4 11 5 10 6 9 7 8 7 4OUT 4IN − 4IN + VDD − / GND 3IN + 3IN − 3OUT 4OUT 4IN − 4IN + VDD − / GND 3IN + 3IN − 3OUT 14 8 TLV2254M, TLV2254AM . . . FK PACKAGE (TOP VIEW) NC 2OUT NC 2IN − NC 1IN+ NC VDD+ NC 2IN+ 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2IN − 2OUT 3 2 1 20 19 18 13 1 1OUT 1IN − 1IN + VDD+ 2IN + 2IN − 2OUT NC 1OUT NC VDD+ NC 4 14 2 TLV2254I, TLV2254AI . . . PW PACKAGE (TOP VIEW) NC VDD− /GND NC 2IN+ NC NC 1IN − NC 1IN + NC 1 1IN − 1OUT NC 4OUT 4IN − TLV2252M, TLV2252AM . . . FK PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD + 2IN + 2IN − 2OUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4IN+ NC VDD −/ GND NC 3IN+ NC 3OUT 3IN − 1OUT 1IN − 1IN + VDD − /GND TLV2254I, TLV2254AI, TLV2254Q, TLV2254AQ . . . D OR N PACKAGE TLV2254M, TLV2254AM . . . J OR W PACKAGE (TOP VIEW) 3 4 IN − IN + Q1 Q5 R4 Q2 R3 Q3 Q4 equivalent schematic (each amplifier) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q10 R6 Q9 3 Capacitors 6 18 56 76 TLV2254 † Includes both amplifiers and all ESD, bias, and trim circuitry 9 30 Resistors Diodes 38 TLV2252 Transistors R1 Q13 C1 Q12 VDD −/ GND Q11 R5 ACTUAL DEVICE COMPONENT COUNT† Q8 COMPONENT Q7 Q6 VDD + R2 Q15 Q14 D1 Q17 Q16 OUT Template Release Date: 7−11−94 2 2 222 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD Input voltage range, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD − −0.3 V to VDD+ Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Q Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, P, and PW packages . . . . . . . 260°C J, JG, U, and W packages . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to VDD − . 2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below VDD − − 0.3 V. 3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C 25 C POWER RATING DERATING FACTOR ABOVE TA = 25°C 85°C TA = 85 C POWER RATING 125°C TA = 125 C POWER RATING D−8 725 mW 5.8 mW/°C 377 mW 145 mW D−14 950 mW 7.6 mW/°C 494 mW 190 mW FK 1375 mW 11.0 mW/°C 715 mW 275 mW J 1375 mW 11.0 mW/°C 715 mW 275 mW JG 1050 mW 8.4 mW/°C 546 mW 210 mW N 1150 mW 9.2 mW/°C 598 mW 230 mW P 1000 mW 8.0 mW/°C 520 mW 200 mW PW−8 525 mW 4.2 mW/°C 273 mW 105 mW PW−14 700 mW 5.6 mW/°C 364 mW 140 mW U 700 mW 5.5 mW/°C 370 mW 150 mW W 700 mW 5.5 mW/°C 370 mW 150 mW recommended operating conditions TLV225xI MIN Supply voltage, VDD Input voltage range, VI Common-mode input voltage, VIC 2.7 VDD − VDD − TLV225xQ MAX 8 VDD + − 1.3 VDD + − 1.3 Operating free-air temperature, TA −40 125 NOTE 1: All voltage values, except differential voltages, are with respect to VDD − . POST OFFICE BOX 655303 MIN 2.7 VDD − VDD − −40 • DALLAS, TEXAS 75265 TLV225xM MAX 8 VDD + − 1.3 VDD + − 1.3 125 MIN 2.7 VDD − VDD − −55 MAX 8 UNIT V VDD + − 1.3 VDD + − 1.3 V 125 °C V 5  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TEST CONDITIONS TA† TLV2252I MIN 25°C MAX 200 1500 Full range VIC = 0, RS = 50 Ω Input offset current 0.003 0.003 µV/mo 25°C 0.5 −40°C to 85°C |VIO | ≤ 5 mV Full range IOH = − 20 µA VOH High-level output voltage VOL AVD Large-signal differential voltage amplification 0.5 1000 1 1 25°C 2.98 IOH = − 75 µA Full range 2.8 2.8 IOH = − 150 µA 25°C 2.8 IOL = 500 µA Full range VIC = 1.5 V, IOL = 1 A Full range VIC = 1.5 V, VO = 1 V to 2 V RL = 100 kΩ‡ RL = 1 MΩ‡ V 10 80 25°C 80 100 100 150 25°C 150 200 100 Full range 10 250 mV 200 300 25°C V 2.8 10 Full range VIC = 1.5 V, −0.3 to 2.2 2.98 2.9 IOL = 50 µA pA 1000 0 to 2 0 to 1.7 2.9 25°C 60 150 1000 −0.3 to 2.2 pA 1000 60 150 0 to 2 0 to 1.7 60 150 25°C VIC = 1.5 V, Low-level output voltage 60 150 −40°C to 85°C RS = 50 Ω Ω, µV 25°C 25°C 25 C VICR 850 1000 UNIT µV/°C Full range Common-mode input voltage range 200 MAX 0.5 25°C Input bias current TYP 0.5 Full range IIB MIN 1750 25°C 25 C to 85°C VDD ± = ± 1.5 V, VO = 0, TLV2252AI TYP 300 100 250 10 V/mV 25°C 800 800 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω 25°C 65 Full range 60 75 65 60 77 dB † Full range is − 40°C to 125°C. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA† kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load IDD Supply current VO = 1.5 V, Full range No load TLV2252I MIN TYP 25°C 80 95 Full range 80 TLV2252AI MAX MIN TYP 80 100 MAX UNIT dB 80 25°C 68 125 68 125 150 150 µA † Full range is − 40°C to 125°C. TLV2252I operating characteristics at specified free-air temperature, VDD = 3 V PARAMETER SR Slew rate at unity gain Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In Equivalent input noise current TEST CONDITIONS TLV2252I TA† MIN TYP 0.1 TLV2252AI MAX MIN TYP 0.07 0.1 MAX UNIT VO = 1.1 V to 1.9 V, RL = 100 kkΩ‡, CL = 100 pF‡ 25 C 25°C 0.07 Full range 0.05 f = 10 Hz 25°C 35 35 f = 1 kHz 25°C 19 19 f = 0.1 Hz to 1 Hz 25°C 0.6 0.6 f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 25°C 0.6 0.6 25°C 0.187 0.187 MHz 25°C 60 60 kHz 25°C 63° 63° 25°C 15 15 Gain-bandwidth product f = 1 kHz, CL = 100 pF‡ RL = 50 kΩ‡, BOM Maximum output-swing bandwidth VO(PP) = 1 V, RL = 50 kΩ‡, AV = 1, CL = 100 pF‡ φm Phase margin at unity gain RL = 50 kΩ‡, CL = 100 pF‡ Gain margin † Full range is − 40°C to 125°C. ‡ Referenced to 1.5 V POST OFFICE BOX 655303 V/µs • DALLAS, TEXAS 75265 0.05 nV/√Hz µV V fA /√Hz dB 7  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage 25°C 25 C to 85°C Input offset voltage longterm drift (see Note 4) IIO Input offset current TLV2252I MIN VICR VIC = 0, RS = 50 Ω Input bias current Common-mode input voltage range |VIO | ≤ 5 mV, High-level output voltage IOH = − 75 µA AVD Low-level output voltage Large-signal differential voltage amplification IOL = 50 µA VIC = 2.5 V, IOL = 500 µA VIC = 2.5 V, IOL = 1 A VIC = 2.5 V, VO = 1 V to 4 V RL = 1 MΩ‡ µV 25°C 0.003 0.003 µV/mo 25°C 0.5 60 0.5 60 −40°C to 85°C 150 150 Full range 1000 1000 1 60 1 150 150 Full range 1000 1000 25°C 0 to 4 Full range 0 to 3.5 −0.3 to 4.2 0 to 4 25°C 4.9 Full range 4.8 25°C 4.8 −0.3 to 4.2 4.98 4.94 4.9 4.94 4.88 4.8 0.01 4.88 0.01 0.06 25°C 0.09 0.06 0.15 0.09 0.15 25°C 0.2 Full range 100 Full range 10 350 0.15 0.15 0.3 0.2 0.3 25°C V 4.8 Full range pA V 0 to 3.5 4.98 pA 60 −40°C to 85°C Full range RL = 100 kΩ‡ 850 1000 UNIT µV/°C 25°C VIC = 2.5 V, 200 MAX 0.5 25°C IOH = − 150 µA VOL 1500 TYP 0.5 RS = 50 Ω IOH = − 20 µA VOH 200 MIN 1750 25°C IIB MAX Full range VDD ± = ± 2.5 V, VO = 0, TLV2252AI TYP V 0.3 0.3 100 350 10 V/mV 25°C 1700 1700 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 2.7 V, RS = 50 Ω VO = 2.5 V, 25°C 70 Full range 70 83 70 70 83 dB † Full range is − 40°C to 125°C. ‡ Referenced to 2.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA† kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load IDD Supply current VO = 2.5 V, No load TLV2252I MIN TYP 25°C 80 95 Full range 80 TLV2252AI MAX MIN TYP 80 95 MAX dB 80 25°C 70 Full range 125 UNIT 70 125 150 150 µA † Full range is − 40°C to 125°C. TLV2252I operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS VO = 1.5 V to 3.5 V, CL = 100 pF‡ RL = 100 kΩ‡, TLV2252I TA† MIN TYP 25°C 0.07 0.12 Full range 0.05 TLV2252AI MAX MIN TYP 0.07 0.12 MAX UNIT SR Slew rate at unity gain V/µs Equivalent input noise voltage f = 10 Hz 25°C 36 36 Vn f = 1 kHz 25°C 19 19 Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 25°C 0.7 0.7 VN(PP) f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 In Equivalent input noise current 25°C 0.6 0.6 Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 50 kΩ‡ AV = 1 0.2% 0.2% THD + N 1% 1% Gain-bandwidth product f = 50 kHz, CL = 100 pF‡ RL = 50 kΩ‡, 25°C 0.2 0.2 MHz BOM Maximum output-swing bandwidth VO(PP) = 2 V, RL = 50 kΩ‡, AV = 1, CL = 100 pF‡ 25°C 30 30 kHz φm Phase margin at unity gain RL = 50 kΩ‡, CL = 100 pF‡ 25°C 63° 63° 25°C 15 15 0.05 nV/√Hz µV V fA /√Hz 25°C AV = 10 Gain margin † Full range is − 40°C to 125°C. ‡ Referenced to 2.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB 9  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TA† TEST CONDITIONS TLV2254I MIN 25°C MAX 200 1500 Full range VIC = 0, RS = 50 Ω VICR 0.003 0.003 µV/mo 25°C 0.5 VOH High-level output voltage VOL AVD Large-signal differential voltage amplification 0.5 150 150 1000 1 1 1000 Full range −0.3 to 2.2 0 to 2 0 to 1.7 25°C 2.98 IOH = − 75 µA 2.9 Full range 2.8 2.8 IOH = − 150 µA 25°C 2.8 Full range VIC = 1.5 V, IOL = 500 µA Full range VIC = 1.5 V, IOL = 1 A Full range RL = 100 kΩ‡ 80 80 100 150 150 200 100 Full range 10 225 mV 200 300 25°C RL = 1 MΩ‡ V 10 100 25°C V 2.8 10 25°C pA 2.98 2.9 25°C −0.3 to 2.2 0 to 1.7 25°C VIC = 1.5 V, VO = 1 V to 2 V 60 1000 0 to 2 pA 1000 60 Full range |VIO | ≤ 5 mV IOL = 50 µA 60 150 25°C VIC = 1.5 V, Low-level output voltage 60 150 IOH = − 20 µA µV 25°C −40°C to 85°C Input bias current RS = 50 Ω, 850 1000 UNIT µV/°C 25°C Common-mode input voltage range 200 MAX 0.5 Full range IIB TYP 0.5 −40°C to 85°C Input offset current MIN 1750 25°C 25 C to 85°C VDD ± = ± 1.5 V, VO = 0, TLV2254AI TYP 300 100 225 10 V/mV 25°C 800 800 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, N package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, RS = 50 Ω VO = 1.5 V, 25°C 65 Full range 60 75 65 60 77 dB † Full range is − 40°C to 125°C. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS TLV2254I MIN TYP 95 Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load 25°C 80 kSVR Full range 80 IDD Supply current (four amplifiers) VO = 1.5 V, Full range No load TLV2254AI MAX MIN TYP 80 100 MAX UNIT dB 80 25°C 135 250 135 300 250 300 µA † Full range is − 40°C to 125°C. TLV2254I operating characteristics at specified free-air temperature, VDD = 3 V SR TLV2254I PARAMETER TEST CONDITIONS TA† MIN TYP VO = 0.7 V to 1.7 V, k ‡, RL = 100 kΩ CL = 100 pF‡ 25 C 25°C 0.07 0.1 Slew rate at unity gain Full range 0.05 Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In Equivalent input noise current TLV2254AI MAX MIN TYP 0.07 0.1 MAX UNIT V/ s V/µs 0.05 f = 10 Hz 25°C 35 35 f = 1 kHz 25°C 19 19 f = 0.1 Hz to 1 Hz 25°C 0.6 0.6 f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 25°C 0.6 0.6 nV/√Hz µV V fA /√Hz Gain-bandwidth product f = 1 kHz, RL = 50 kΩ ‡, CL = 100 pF ‡ 25°C 0.187 0.187 MHz BOM Maximum output-swing bandwidth VO(PP) = 1 V, AV = 1, RL = 50 kΩ‡, CL = 100 pF ‡ 25°C 60 60 kHz φm Phase margin at unity gain 25°C 63° 63° 25°C 15 15 Gain margin RL = 50 kΩ‡, CL = 100 pF ‡ dB † Full range is − 40°C to 85°C. ‡ Referenced to 1.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† MIN 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage 25 C 25°C to 85°C Input offset voltage long-term drift (see Note 4) IIO TLV2254I TYP MAX 200 1500 Full range VDD ± = ± 2.5 V, VO = 0, VIC = 0, RS = 50 Ω Common-mode input voltage range 0.003 0.003 µV/mo 25°C 0.5 25°C RS = 50 Ω Full range IOH = − 20 µA VOH High-level output voltage IOH = − 150 µA IOL = 50 µA VIC = 2.5 V, VOL AVD Low-level output voltage Large-signal differential voltage amplification VIC = 2.5 V, IOL = 500 µA VIC = 2.5 V, IOL = 1 A VIC = 2.5 V, VO = 1 V to 4 V RL = 100 kΩ‡ RL = 1 MΩ‡ 60 0.5 150 1 4.9 Full range 4.8 25°C 4.8 25°C −0.3 to 4.2 4.98 4.94 4.9 4.94 4.88 Full range 4.8 4.88 0.01 0.06 0.09 Full range 0.06 0.15 0.09 0.15 25°C 0.2 Full range 100 Full range 10 350 0.15 0.15 0.3 0.2 0.3 25°C V 4.8 0.01 25°C V 0 to 3.5 4.98 25°C pA 1000 0 to 4 0 to 3.5 60 150 1000 −0.3 to 4.2 pA 1000 60 150 0 to 4 60 150 1000 1 25°C IOH = − 75 µA µV 25°C −40°C to 85°C |VIO | ≤ 5 mV, 850 1000 UNIT µV/°C Full range VICR 200 MAX 0.5 25°C Input bias current TYP 0.5 Full range IIB MIN 1750 −40°C to 85°C Input offset current TLV2254AI V 0.3 0.3 100 350 10 V/mV 25°C 1700 1700 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, N package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 2.7 V, RS = 50 Ω VO = 2.5 V, 25°C 70 Full range 70 83 70 70 83 dB † Full range is − 40°C to 125°C. ‡ Referenced to 2.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load IDD Supply current (four amplifiers) VO = 2.5 V, TLV2254I MIN TYP 25°C 80 95 Full range 80 MAX MIN TYP 80 95 MAX UNIT dB 80 25°C No load TLV2254AI 140 Full range 250 140 300 250 300 µA A † Full range is − 40°C to 125°C. TLV2254I operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS RL = 100 kΩ ‡, TLV2254I TA† MIN TYP 25°C 0.07 0.12 Full range 0.05 TLV2254AI MAX MIN TYP 0.07 0.12 MAX UNIT SR Slew rate at unity gain VO = 1.4 V to 2.6 V, CL = 100 pF ‡ Equivalent input noise voltage f = 10 Hz 25°C 36 36 Vn f = 1 kHz 25°C 19 19 Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 25°C 0.7 0.7 VN(PP) f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 In Equivalent input noise current 25°C 0.6 0.6 Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 50 kΩ ‡ AV = 1 0.2% 0.2% THD + N 1% 1% Gain-bandwidth product f = 50 kHz, CL = 100 pF ‡ RL = 50 kΩ ‡, 25°C 0.2 0.2 MHz BOM Maximum outputswing bandwidth VO(PP) = 2 V, RL = 50 kΩ ‡, AV = 1, CL = 100 pF ‡ 25°C 30 30 kHz φm Phase margin at unity gain RL = 50 kΩ ‡, CL = 100 pF ‡ 25°C 63° 63° 25°C 15 15 V/µs 0.05 nV/√Hz µV V fA /√Hz 25°C AV = 10 Gain margin † Full range is − 40°C to 125°C. ‡ Referenced to 2.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB 13  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† TLV2252Q, TLV2252M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current 25°C Common-mode input voltage range VIC = 0, RS = 50 Ω Low-level output voltage VIC = 1.5 V, VIC = 1.5 V, AVD Large-signal differential voltage amplification VIC = 1.5 V, VO = 1 V to 2 V IOL = 500 µA IOL = 1 A RL = 100 kΩ‡ RL = 1 MΩ‡ µV 0.003 0.003 µV/mo 25°C 0.5 60 0.5 1000 1 0 to 2 0 to 1.7 60 −0.3 to 2.2 1 0 to 2 0 to 1.7 2.98 2.9 Full range 2.8 2.8 25°C 2.8 2.8 10 100 Full range −0.3 to 2.2 200 Full range 100 Full range 10 V 10 150 100 250 150 165 300 200 300 25°C pA V 165 25°C pA 2.98 2.9 25°C 60 1000 25°C 25°C 60 1000 1000 25°C IOL = 50 µA 850 1000 25°C |VIO | ≤ 5 mV IOH = − 75 µA 200 UNIT MAX µV/°C 25°C RS = 50 Ω Ω, TYP 0.5 125°C IOH = − 150 µA VIC = 1.5 V, VOL 1500 125°C IOH = − 20 µA VOH 200 MIN 0.5 Full range High-level output voltage MAX 1750 25°C 25 C to 85°C 25°C 25 C VICR TYP Full range VDD ± = ± 1.5 V, VO = 0, TLV2252AQ, TLV2252AM mV 300 300 100 250 10 V/mV 25°C 800 800 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, RS = 50 Ω VO = 1.5 V, kSVR Supply voltage rejection VDD /∆V / VIO) ratio ((∆V VDD = 2.7 V to 8 V, VIC = VDD /2, No load IDD Supply current VO = 1.5 V, No load 25°C 65 Full range 60 25°C 80 Full range 80 25°C Full range 75 65 77 dB 60 95 80 100 dB 80 68 125 150 68 125 150 µA † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M operating characteristics at specified free-air temperature, VDD = 3 V PARAMETER TA† TEST CONDITIONS VO = 0.8 V to 1.4 V, CL = 100 pF‡ RL = 100 kΩ‡, TLV2252Q, TLV2252M MIN TYP 25°C 0.07 0.1 Full range 0.05 TLV2252AQ, TLV2252AM MAX MIN TYP 0.07 0.1 UNIT MAX SR Slew rate at unity gain Equivalent input noise voltage f = 10 Hz 25°C 35 35 Vn f = 1 kHz 25°C 19 19 Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 25°C 0.6 0.6 VN(PP) f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 In Equivalent input noise current 25°C 0.6 0.6 25°C 0.187 0.187 MHz 25°C 60 60 kHz 25°C 63° 63° Gain margin 25°C † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 1.5 V 15 15 Gain-bandwidth product f = 1 kHz, CL = 100 pF‡ RL = 50 kΩ‡, BOM Maximum output-swing bandwidth VO(PP) = 1 V, RL = 50 kΩ‡, AV = 1, CL = 100 pF‡ φm Phase margin at unity gain RL = 50 kΩ‡, CL = 100 pF‡ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V/µs 0.05 nV/√Hz µV V fA /√Hz dB 15  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† TLV2252Q, TLV2252M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage longterm drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode input voltage range 25°C VOL High-level output voltage Low-level output voltage Large-signal differential voltage amplification 200 1500 VIC = 0, RS = 50 Ω VIC = 2.5 V, IOL = 500 µA VIC = 2.5 V, VO = 1 V to 4 V IOL = 1 A RL = 100 kΩ‡ RL = 1 MΩ‡ µV 0.003 0.003 µV/mo 25°C 0.5 60 0.5 1000 1 25°C 0 to 4 60 Full range 0 to 3.5 −0.3 to 4.2 1 4.9 Full range 4.8 25°C 4.8 0 to 4 −0.3 to 4.2 4.9 4.94 4.88 25°C 0.09 4.8 4.88 0.01 0.15 0.09 0.15 0.2 Full range 100 Full range 10 350 0.15 0.15 0.3 0.2 0.3 25°C V 4.8 Full range pA 4.98 4.94 0.01 pA V 0 to 3.5 25°C 25°C 60 1000 4.98 25°C 60 1000 1000 25°C IOL = 50 µA 850 1000 25°C RS = 50 Ω IOH = − 150 µA VIC = 2.5 V, 200 UNIT MAX µV/°C 125°C IOH = − 75 µA TYP 0.5 25°C |VIO | ≤ 5 mV, MIN 0.5 125°C VIC = 2.5 V, AVD MAX 1750 25°C 25 C to 85°C IOH = − 20 µA VOH TYP Full range VDD ± = ± 2.5 V, VO = 0, TLV2252AQ, TLV2252AM V 0.3 0.3 100 350 10 V/mV 25°C 1700 1700 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω 25°C 70 Full range 70 kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load 25°C 80 Full range 80 83 70 83 70 95 80 80 95 dB dB † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 2.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS TLV2252Q, TLV2252M MIN IDD Supply current VO = 2.5 V, No load 25°C TLV2252AQ, TLV2252AM TYP MAX 70 125 Full range MIN UNIT TYP MAX 70 125 150 150 µA † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. TLV2252Q, and TLV2252M operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER SR Slew rate at unity gain TA† TEST CONDITIONS TLV2252Q, TLV2252M MIN TYP 0.12 VO = 1.25 V to 2.75 V, RL = 100 kkΩ‡, CL = 100 pF‡ 25 C 25°C 0.07 Full range 0.05 MAX TLV2252AQ, TLV2252AM MIN TYP 0.07 0.12 UNIT MAX V/µs 0.05 f = 10 Hz 25°C 36 36 f = 1 kHz 25°C 19 19 f = 0.1 Hz to 1 Hz 25°C 0.7 0.7 f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 25°C 0.6 0.6 0.2% 0.2% 1% 1% 25°C 0.2 0.2 MHz 25°C 30 30 kHz 25°C 63° 63° Gain margin 25°C † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 2.5 V 15 15 Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In Equivalent input noise current Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 50 kΩ‡ AV = 1 THD + N Gain-bandwidth product f = 50 kHz, CL = 100 pF‡ RL = 50 kΩ‡, BOM Maximum output-swing bandwidth VO(PP) = 2 V, RL = 50 kΩ‡, AV = 1, CL = 100 pF‡ φm Phase margin at unity gain RL = 50 kΩ‡, CL = 100 pF‡ nV/√Hz µV V fA /√Hz 25°C AV = 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB 17  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† TLV2254Q, TLV2254M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage longterm drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode input voltage range 25°C VOL High-level output voltage Low-level output voltage Large-signal differential voltage amplification 200 1500 VIC = 0, RS = 50 Ω 0.003 µV/mo 25°C 0.5 1 0.5 25°C 25 C 0 to 2 60 Full range 0 to 1.7 −0.3 to 2.2 1 0 to 2 −0.3 to 2.2 2.98 Full range 2.8 2.8 25°C 2.8 10 VIC = 1.5 V, IOL = 500 µA 25°C 100 Full range V 2.8 10 150 100 165 200 Full range Full range 10 225 150 165 300 200 300 100 pA 2.98 2.9 25°C pA V 0 to 1.7 2.9 25°C 60 1000 25°C 25°C 60 1000 1000 IOL = 50 µA RL = 1 MΩ‡ 60 1000 25°C RL = 100 kΩ‡ µV 0.003 IOH = − 150 µA VIC = 1.5 V, VIC = 1.5 V, VO = 1 V to 2 V 850 1000 25°C |VIO | ≤ 5 mV IOL = 1 A 200 UNIT MAX µV/°C 125°C IOH = − 75 µA TYP 0.5 25°C RS = 50 Ω Ω, MIN 0.5 125°C VIC = 1.5 V, AVD MAX 1750 25°C 25 C to 125°C IOH = − 20 µA VOH TYP Full range VDD ± = ± 1.5 V, VO = 0, TLV2254AQ, TLV2254AM mV 300 300 100 225 10 V/mV 25°C 800 800 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, N package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, RS = 50 Ω VO = 1.5 V, kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load 25°C 65 Full range 60 25°C 80 Full range 80 75 65 77 60 95 80 dB 100 dB 80 † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TLV2254Q, TLV2254M TA† TEST CONDITIONS MIN IDD Supply current (four amplifiers) VO = 1.5 V, 25°C No load TLV2254AQ, TLV2254AM TYP MAX 135 250 Full range MIN UNIT TYP MAX 135 250 300 300 µA † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. TLV2254Q, and TLV2254M operating characteristics at specified free-air temperature, VDD = 3 V PARAMETER SR Slew rate at unity gain Vn Equivalent input noise voltage VN(PP) Peak-to-peak equivalent input noise voltage In Equivalent input noise current TA† TEST CONDITIONS VO = 0.5 V to 1.7 V, RL = 100 kΩ‡, CL = 100 pF‡ TLV2254Q, TLV2254M MIN TYP 25°C 0.07 0.1 Full range 0.05 TLV2254AQ, TLV2254AM MAX MIN TYP 0.07 0.1 UNIT MAX V/µs 0.05 f = 10 Hz 25°C 35 35 f = 1 kHz 25°C 19 19 f = 0.1 Hz to 1 Hz 25°C 0.6 0.6 f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 25°C 0.6 0.6 nV/√Hz µV V fA /√Hz Gain-bandwidth product f = 1 kHz, RL = 50 kΩ ‡, CL = 100 pF ‡ 25°C 0.187 0.187 MHz BOM Maximum output-swing bandwidth VO(PP) = 1 V, AV = 1, RL = 50 kΩ‡, CL = 100 pF ‡ 25°C 60 60 kHz φm Phase margin at unity gain 25°C 63° 63° 15 15 RL = 50 kΩ‡, CL = 100 pF ‡ Gain margin 25°C † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 1.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB 19  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† TLV2254Q, TLV2254M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode input voltage range 25°C High-level output voltage Low-level output voltage Large-signal differential voltage amplification 1500 VIC = 0, RS = 50 Ω IOL = 500 µA VIC = 2.5 V, IOL = 1 A VIC = 2.5 V, VO = 1 V to 4 V RL = 100 kΩ‡ RL = 1 MΩ‡ 850 1000 µV 25°C 0.003 0.003 µV/mo 25°C 0.5 60 0.5 1000 1 25°C 25 C 0 to 4 60 Full range 0 to 3.5 −0.3 to 4.2 1 4.9 Full range 4.8 25°C 4.8 0 to 4 −0.3 to 4.2 4.9 4.94 4.88 0.09 Full range 4.8 4.88 0.01 0.15 0.09 0.15 0.2 Full range 100 Full range 10 350 0.15 0.15 0.3 0.2 0.3 25°C V 4.8 25°C pA 4.98 4.94 0.01 pA V 0 to 3.5 25°C 25°C 60 1000 4.98 25°C 60 1000 1000 25°C IOL = 50 µA 200 UNIT MAX µV/°C RS = 50 Ω IOH = − 75 µA TYP 0.5 25°C |VIO | ≤ 5 mV, MIN 0.5 125°C VIC = 2.5 V, AVD 200 125°C IOH = − 150 µA VIC = 2.5 V, VOL MAX 1750 25°C 25 C to 125°C IOH = − 20 µA VOH TYP Full range VDD ± = ± 2.5 V, VO = 0, TLV2254AQ, TLV2254AM V 0.3 0.3 100 350 10 V/mV 25°C 1700 1700 ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, N package 25°C 8 8 pF zo Closed-loop output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 2.7 V, RS = 50 Ω VO = 2.5 V, 25°C 70 Full range 70 83 70 70 83 dB Supply voltage 25°C 80 95 80 95 VDD = 4.4 V to 8 V, rejection ratio dB VIC = VDD /2, No load Full range 80 80 (∆VDD /∆VIO) † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 2.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. kSVR 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TLV2254Q, TLV2254M TA† MIN Supply current (four amplifiers) IDD 25°C VO = 2.5 V, No load TLV2254AQ, TLV2254AM TYP MAX 140 250 Full range MIN UNIT TYP MAX 140 250 300 300 A µA † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. TLV2254Q, and TLV2254M operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS RL = 100 kΩ ‡, TA† TLV2254Q, TLV2254M MIN TYP 25°C 0.07 0.12 Full range 0.05 TLV2254AQ, TLV2254AM MAX MIN TYP 0.07 0.12 UNIT MAX Slew rate at unity gain VO = 0.5 V to 3.5 V, CL = 100 pF ‡ Equivalent input noise voltage f = 10 Hz 25°C 36 36 Vn f = 1 kHz 25°C 19 19 Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 25°C 0.7 0.7 VN(PP) f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 In Equivalent input noise current 25°C 0.6 0.6 Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, RL = 50 kΩ ‡ AV = 1 0.2% 0.2% THD + N 1% 1% Gain-bandwidth product f = 50 kHz, CL = 100 pF ‡ RL = 50 kΩ ‡, 25°C 0.2 0.2 MHz BOM Maximum outputswing bandwidth VO(PP) = 2 V, RL = 50 kΩ ‡, AV = 1, CL = 100 pF ‡ 25°C 30 30 kHz φm Phase margin at unity gain RL = 50 kΩ ‡, CL = 100 pF ‡ 25°C 63° 63° Gain margin 25°C † Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part. ‡ Referenced to 2.5 V 15 15 SR V/µs 0.05 nV/√Hz µV V fA /√Hz 25°C AV = 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB 21  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution vs Common-mode voltage 2−5 6, 7 αVIO IIB /IIO Input offset voltage temperature coefficient Distribution 8 − 11 Input bias and input offset currents vs Free-air temperature 12 VI Input voltage vs Supply voltage vs Free-air temperature 13 14 VOH VOL High-level output voltage vs High-level output current 15, 18 Low-level output voltage vs Low-level output current 16, 17, 19 VO(PP) Maximum peak-to-peak output voltage vs Frequency 20 IOS Short-circuit output current vs Supply voltage vs Free-air temperature 21 22 VID AVD Differential input voltage vs Output voltage 23, 24 Differential voltage amplification vs Load resistance 25 AVD Large-signal differential voltage amplification vs Frequency vs Free-air temperature 26, 27 28, 29 zo Output impedance vs Frequency 30, 31 CMRR Common-mode rejection ratio vs Frequency vs Free-air temperature 32 33 kSVR Supply-voltage rejection ratio vs Frequency vs Free-air temperature 34, 35 36 IDD Supply current vs Supply voltage 37, 38 SR Slew rate vs Load capacitance vs Free-air temperature VO VO Inverting large-signal pulse response 41, 42 Voltage-follower large-signal pulse response 43, 44 VO VO Inverting small-signal pulse response 45, 46 Vn Equivalent input noise voltage vs Frequency Input noise voltage Over a 10-second period 51 Integrated noise voltage vs Frequency 52 Total harmonic distortion plus noise vs Frequency 53 Gain-bandwidth product vs Supply voltage vs Free-air temperature 54 55 Phase margin vs Frequency vs Load capacitance 26, 27 56 Gain margin vs Load capacitance 57 Unity-gain bandwidth vs Load capacitance 58 Overestimation of phase margin vs Load capacitance 59 THD + N φm B1 22 Voltage-follower small-signal pulse response POST OFFICE BOX 655303 39 40 47, 48 • DALLAS, TEXAS 75265 49, 50  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE 20 20 1020 Amplifiers From 1 Wafer Lot VDD = ± 2.5 V TA = 25°C Precentage of Amplifiers − % Precentage of Amplifiers − % 1020 Amplifiers From 1 Wafer Lot VDD = ± 1.5 V TA = 25°C 15 10 5 0 −1.6 −0.8 0 0.8 VIO − Input Offset Voltage − mV 15 10 5 0 −1.6 1.6 Figure 2 DISTRIBUTION OF TLV2254 INPUT OFFSET VOLTAGE 35 35 682 Amplifiers From 1 Wafer Lot VDD ± = ± 1.5 V 30 TA = 25°C 682 Amplifiers From 1 Wafer Lot VDD ± = ± 2.5 V 30 TA = 25°C Percentage of Amplifiers − % Percentage of Amplifiers − % 1.6 Figure 3 DISTRIBUTION OF TLV2254 INPUT OFFSET VOLTAGE 25 20 15 10 5 0 −1.6 −0.8 0 0.8 VIO − Input Offset Voltage − mV 25 20 15 10 5 −0.8 0 0.8 VIO − Input Offset Voltage − mV 1.6 0 −1.6 Figure 4 −0.8 0 0.8 VIO − Input Offset Voltage − mV 1.6 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE 1 1 VDD = 3 V RS = 50 Ω TA = 25°C 0.8 VIO − Input Offset Voltage − mV 0.6 VIO − Input Offset Voltage − mV VDD = 5 V RS = 50 Ω TA = 25°C 0.8 0.4 0.2 0 −0.2 0.6 0.4 0.2 0 −0.2 ÁÁ ÁÁ −0.4 ÁÁ ÁÁ −0.6 −0.4 −0.6 −0.8 −0.8 −1 −1 0 1 −1 −1 3 2 0 Figure 6 4 15 10 5 −1 0 1 α VIO − Temperature Coefficient − µ V / °C 2 62 Amplifiers From 1 Wafer Lot VDD± = ± 2.5 V P Package 20 T = 25°C to 85°C A 15 10 5 0 −2 −1 0 1 α VIO − Temperature Coefficient − µ V / °C Figure 8 Figure 9 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 24 5 25 62 Amplifiers From 1 Wafer Lot VDD± = ± 1.5 V P Package TA = 25°C to 85°C Percentage of Amplifiers − % Percentage of Amplifiers − % 3 DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † 25 0 −2 2 Figure 7 DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † 20 1 VIC − Common-Mode Input Voltage − V VIC − Common-Mode Input Voltage − V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2254 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 25 62 Amplifiers From 1 Wafer Lot VDD± = ± 1.5 V P Package TA = 25°C to 85°C 20 62 Amplifiers From 1 Wafer Lot VDD ± = ± 2.5 V P Package 20 TA = 25°C to 85°C Percentage of Amplifiers − % Percentage of Amplifiers − % 25 DISTRIBUTION OF TLV2254 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 15 10 5 15 10 5 0 −2 −1 0 1 0 2 −2 −1 0 1 αVIO − Temperature Coefficient of Input Offset Voltage − µV / °C αVIO − Temperature Coefficient of Input Offset Voltage − µV / °C Figure 11 INPUT VOLTAGE vs SUPPLY VOLTAGE INPUT BIAS AND INPUT OFFSET CURRENTS† vs FREE-AIR TEMPERATURE 35 30 2.5 VDD± = ± 2.5 V VIC = 0 VO = 0 RS = 50 Ω 1.5 25 20 10 IIB 1 0.5 0 ÁÁ ÁÁ 15 | VIO | ≤ 5 mV −0.5 −1 −1.5 IIO 5 0 25 RS = 50 Ω TA = 25°C 2 VI − Input Voltage − V IIIB IB and IIIO IO − Input Bias and Input Offset Currents − pA Figure 10 2 −2 −2.5 105 45 65 85 TA − Free-Air Temperature − °C 125 1 1.5 2 2.5 3 3.5 | VDD ± | − Supply Voltage − V 4 Figure 13 Figure 12 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT VOLTAGE†‡ vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT 5 3 VDD = 5 V VDD = 3 V ÁÁ VOH − High-Level Output Voltage − V VI − Input Voltage − V 4 3 | VIO | ≤ 5 mV 2 1 0 −1 −55 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C 125 ÁÁ ÁÁ ÁÁ 2.5 TA = − 40°C 2 TA = 25°C 1.5 TA = 85°C 1 TA = 125°C 0.5 0 0 200 LOW-LEVEL OUTPUT VOLTAGE†‡ vs LOW-LEVEL OUTPUT CURRENT 1.4 1.2 VOL − Low-Level Output Voltage − V VDD = 3 V TA = 25°C 1 VIC = 0 0.8 VIC = 0.75 V 0.6 VIC = 1.5 V 0.4 ÁÁ ÁÁ ÁÁ 0.2 0 0 1 2 3 4 5 IOL − Low-Level Output Current − mA VDD = 3 V VIC = 1.5 V 1.2 TA = 125°C 1 TA = 85°C 0.8 TA = 25°C 0.6 0.4 TA = − 40°C 0.2 0 0 1 2 3 4 IOL − Low-Level Output Current − mA Figure 16 Figure 17 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 26 800 Figure 15 LOW-LEVEL OUTPUT VOLTAGE‡ vs LOW-LEVEL OUTPUT CURRENT VOL − Low-Level Output Voltage − V 600 | IOH | − High-Level Output Current − µ A Figure 14 ÁÁ ÁÁ 400 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE†‡ vs LOW-LEVEL OUTPUT CURRENT 5 1.4 VDD = 5 V VIC = 2.5 V ÁÁ ÁÁ 1.2 4 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VDD = 5 V TA = − 40°C 3 TA = 25°C 2 TA = 85°C ÁÁ ÁÁ 1 TA = 125°C 0 0 200 400 600 TA = 125°C 1 TA = 85°C 0.8 TA = 25°C 0.6 0.4 TA = − 40°C 0.2 0 800 0 | IOH | − High-Level Output Current − µA 1 2 Figure 18 5 6 SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE 10 5 RI = 50 kΩ TA = 25°C VDD = 5 V I OS − Short-Circuit Output Current − mA VO(PP) − Maximum Peak-to-Peak Output Voltage − V 4 Figure 19 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡ vs FREQUENCY ÁÁ ÁÁ ÁÁ 3 IOL − Low-Level Output Current − mA 4 3 VDD = 3 V 2 1 0 10 2 9 8 6 5 10 5 VO = VDD/2 TA = 25°C VIC = VDD/2 4 3 2 1 VID = 100 mV 0 −1 10 3 10 4 f − Frequency − Hz VID = − 100 mV 7 2 3 Figure 20 6 4 5 VDD − Supply Voltage − V 7 8 Figure 21 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DIFFERENTIAL INPUT VOLTAGE‡ vs OUTPUT VOLTAGE SHORT-CIRCUIT OUTPUT CURRENT † vs FREE-AIR TEMPERATURE 1000 VO = 2.5 V VDD = ± 5 V 10 9 8 VID = − 100 mV 7 6 5 4 3 2 1 600 400 200 0 −200 −400 −600 −800 VID = 100 mV 0 −1 −75 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VDD = 3 V RI = 50 kΩ VIC = 1.5 V TA = 25°C 800 V ID − Differential Input Voltage − µ V I OS − Short-Circuit Output Current − mA 11 −1000 125 0 0.5 1 1.5 2 VO − Output Voltage − V Figure 22 DIFFERENTIAL VOLTAGE AMPLIFICATION†‡ vs LOAD RESISTANCE V ID − Differential Input Voltage − µ V AVD − Differential Voltage Amplification − V/mV 1000 VDD = 5 V VIC = 2.5 V RL = 50 kΩ TA = 25°C 600 400 200 0 −200 −400 −600 −800 −1000 0 1 3 2 4 VO − Output Voltage − V 5 10 4 VO(PP) = 2 V TA = 25°C 10 3 VDD = 5 V 10 2 VDD = 3 V 101 ÁÁ ÁÁ 1 1 101 10 2 RL − Load Resistance − kΩ Figure 24 Figure 25 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 28 3 Figure 23 DIFFERENTIAL INPUT VOLTAGE‡ vs OUTPUT VOLTAGE 800 2.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 3  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE† AMPLIFICATION AND PHASE MARGIN vs FREQUENCY AVD A VD − Large-Signal Differential Voltage Amplification − dB 60 ÁÁ ÁÁ ÁÁ 180° VDD = 5 V RL = 50 kΩ CL= 100 pF TA = 25°C 135° 40 90° Phase Margin 20 45° Gain 0 0° −20 φom m − Phase Margin 80 −45° −40 10 3 10 4 10 5 10 6 f − Frequency − Hz −90° 10 7 Figure 26 LARGE-SIGNAL DIFFERENTIAL VOLTAGE† AMPLIFICATION AND PHASE MARGIN vs FREQUENCY AVD A VD − Large-Signal Differential Voltage Amplification − dB 60 ÁÁ ÁÁ ÁÁ 180° VDD = 3 V RL= 50 kΩ CL= 100 pF TA = 25°C 135° 40 Phase Margin 20 45° Gain 0 0° −20 −40 10 3 90° φom m − Phase Margin 80 −45° 10 4 10 5 10 6 f − Frequency − Hz −90° 10 7 Figure 27 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL†‡ VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE LARGE-SIGNAL DIFFERENTIAL†‡ VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE 10 4 VDD = 3 V VIC = 1.5 V VO = 0.5 V to 2.5 V AVD − Large-Signal Differential Voltage Amplification − V/mV AVD − Large-Signal Differential Voltage Amplification − V/mV 10 4 RL = 1 MΩ 10 3 RL = 50 kΩ 10 2 101 −75 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VDD = 5 V VIC = 2.5 V VO = 1 V to 4 V RL = 1 MΩ 10 3 RL = 50 kΩ 10 2 101 −75 125 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 28 Figure 29 OUTPUT IMPEDANCE‡ vs FREQUENCY OUTPUT IMPEDANCE‡ vs FREQUENCY 1000 1000 VDD = 5 V TA = 25°C z o − Output Impedance − Ω z o − Output Impedance − Ω VDD = 3 V TA = 25°C 100 125 AV = 100 10 AV = 10 1 100 AV = 100 10 AV = 10 1 AV = 1 AV = 1 0.1 10 2 10 3 10 4 f− Frequency − Hz 10 5 10 6 0.1 10 2 Figure 30 10 3 10 4 f− Frequency − Hz 10 5 Figure 31 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 6  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO†‡ vs FREE-AIR TEMPERATURE COMMON-MODE REJECTION RATIO† vs FREQUENCY 94 VDD = 5 V VIC = 2.5 V CMMR − Common-Mode Rejection Ratio − dB CMRR − Common-Mode Rejection Ratio − dB 100 TA = 25°C 80 VDD = 3 V VIC = 1.5 V 60 40 20 0 10 1 10 2 10 4 10 3 f − Frequency − Hz 10 5 92 90 VDD = 5 V 88 VDD = 3 V 86 84 82 80 0 25 50 75 100 − 75 − 50 − 25 TA − Free-Air Temperature − °C 10 6 Figure 33 Figure 32 SUPPLY-VOLTAGE REJECTION RATIO† vs FREQUENCY SUPPLY-VOLTAGE REJECTION RATIO† vs FREQUENCY 100 VDD = 3 V TA = 25°C k SVR − Supply-Voltage Rejection Ratio − dB k SVR − Supply-Voltage Rejection Ratio − dB 100 80 60 kSVR + 40 kSVR − 20 ÁÁ ÁÁ ÁÁ 0 −20 10 1 125 10 2 10 3 10 4 f − Frequency − Hz 10 5 10 6 ÁÁ ÁÁ ÁÁ VDD = 5 V TA = 25°C kSVR + 80 60 kSVR − 40 20 0 −20 101 10 2 10 3 10 4 10 5 10 6 f − Frequency − Hz Figure 34 Figure 35 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. ‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS TLV2252 SUPPLY CURRENT † vs SUPPLY VOLTAGE SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE Á Á 120 VDD = 2.7 V to 8 V VIC = VO = VDD / 2 VO = 0 No Load 100 I DD − Supply Current − µ A k SVR − Supply-Voltage Rejection Ratio − dB 110 105 100 60 ÁÁ ÁÁ 95 90 −75 −50 TA = − 40°C 80 TA = 85°C TA = 25°C 40 20 0 −25 0 25 50 75 100 TA − Free-Air Temperature − °C 125 0 1 2 3 4 5 6 VDD − Supply Voltage − V Figure 36 SLEW RATE‡ vs LOAD CAPACITANCE 0.2 240 VO = 0 No Load 0.18 VDD = 5 V AV = − 1 TA = 25°C 0.16 SR − Slew Rate − V/ µ s I DD − Supply Current − µ A 200 TA = − 40°C 160 120 TA = 85°C TA = 25°C 80 0.14 SR − 0.12 0.1 SR + 0.08 0.06 0.04 40 0.02 0 0 1 2 3 4 5 6 | VDD ± | − Supply Voltage − V 7 8 0 101 Figure 38 10 2 10 3 CL − Load Capacitance − pF Figure 39 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 32 8 Figure 37 TLV2254 SUPPLY CURRENT † vs SUPPLY VOLTAGE ÁÁ ÁÁ ÁÁ 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 4  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS SLEW RATE†‡ vs FREE-AIR TEMPERATURE INVERTING LARGE-SIGNAL PULSE RESPONSE† 0.2 0.16 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = −1 TA = 25°C 2.5 SR − VO − Output Voltage − V SR − Slew Rate − V/ µ s 3 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 0.12 SR + 0.08 0.04 2 1.5 1 0.5 0 −75 0 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C 125 0 10 20 Figure 40 40 50 60 70 t − Time − µs 80 90 100 Figure 41 INVERTING LARGE-SIGNAL PULSE RESPONSE† VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE† 5 3 VDD = 5 V RL = 50 kΩ CL = 100 pF 4 A = −1 V TA = 25°C VDD = 3 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 2.5 VO − Output Voltage − V VO − Output Voltage − V 30 3 2 1 2 1.5 1 0.5 0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 t − Time − µs 20 30 40 50 60 70 80 90 100 t − Time − µs Figure 42 Figure 43 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INVERTING SMALL-SIGNAL PULSE RESPONSE† VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE† 0.95 5 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 0.9 VO − Output Voltage − V VO − Output Voltage − V 4 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = − 1 TA = 25°C 3 2 0.85 0.8 0.75 0.7 1 0.65 0.6 0 0 10 20 30 40 50 60 t − Time − µs 70 80 0 90 100 10 30 40 50 t − Time − µs Figure 44 Figure 45 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE† INVERTING SMALL-SIGNAL PULSE RESPONSE† 0.95 2.65 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = − 1 TA = 25°C VDD = 3 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 0.9 VO VO − Output Voltage − V 2.6 VO VO − Output Voltage − V 20 2.55 2.5 0.85 0.8 0.75 0.7 2.45 0.65 0.6 2.4 0 10 20 30 t − Time − µs 40 50 0 Figure 46 10 20 30 t − Time − µs 40 Figure 47 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 50  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS EQUIVALENT INPUT NOISE VOLTAGE† vs FREQUENCY VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE† 60 2.65 VO VO − Output Voltage − V 2.6 V n − Equivalent Input Noise Voltage − nV/ Hz VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 2.55 2.5 2.45 2.4 0 10 20 30 t − Time − µs 40 50 VDD = 3 V RS = 20 Ω TA = 25°C 40 30 20 10 0 10 1 50 10 2 10 3 f − Frequency − Hz Figure 48 Figure 49 EQUIVALENT INPUT NOISE VOLTAGE† vs FREQUENCY INPUT NOISE VOLTAGE OVER A 10-SECOND PERIOD† 1000 VDD = 5 V RS = 20 Ω TA = 25°C VDD = 5 V f = 0.1 Hz to 10 Hz TA = 25°C 750 500 Noise Voltage − nV V n − Equivalent Input Noise Voltage − nV/ Hz 60 50 10 4 40 30 20 250 0 −250 −500 10 −750 0 101 10 2 10 3 f − Frequency − Hz 10 4 −1000 0 2 4 6 8 10 t − Time − s Figure 51 Figure 50 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INTEGRATED NOISE VOLTAGE† vs FREQUENCY THD + N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE† vs FREQUENCY Integrated Noise Voltage − µ V 100 Calculated Using Ideal Pass-Band Filter Low Frequency = 1 Hz TA = 25°C 10 1 0.1 101 1 10 2 10 3 f − Frequency − Hz 10 4 10 5 1 AV = 100 0.1 AV = 10 0.01 AV = 1 VDD = 5 V RL = 50 kΩ TA = 25°C 0.001 101 10 2 10 3 Figure 52 GAIN-BANDWIDTH PRODUCT†‡ vs FREE-AIR TEMPERATURE 300 VDD = 5 V f = 10 kHz RL = 50 kHz CL = 100 pF Gain-Bandwidth Product − kHz 220 210 200 190 260 220 180 140 180 100 −75 170 0 1 4 6 2 3 5 VDD − Supply Voltage − V 7 8 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 55 Figure 54 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. 36 10 5 Figure 53 GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE Gain-Bandwidth Product − kHz 10 4 f − Frequency − Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE 75° GAIN MARGIN vs LOAD CAPACITANCE 20 Rnull = 200 Ω TA = 25°C Rnull = 500 Ω Rnull = 500 Ω 60° Gain Margin − dB φom m − Phase Margin 15 45° Rnull = 100 Ω Rnull = 50 Ω 30° Rnull = 10 Ω 50 kΩ VI 0° 101 Rnull = 100 Ω 10 Rnull = 50 Ω Rnull = 10 Ω 50 kΩ 15° Rnull = 200 Ω 5 VDD + Rnull − + Rnull = 0 Rnull = 0 CL TA = 25°C VDD − 10 2 10 3 CL − Load Capacitance − pF 0 101 10 4 10 4 10 2 10 3 CL − Load Capacitance − pF Figure 56 Figure 57 OVERESTIMATION OF PHASE MARGIN† vs LOAD CAPACITANCE UNITY-GAIN BANDWIDTH vs LOAD CAPACITANCE 25 TA = 25°C 200 TA = 25°C Rnull = 500 Ω Overestimation of Phase Margin B1 − Unity-Gain Bandwidth − kHz 175 ÁÁ ÁÁ 10 5 150 125 100 75 50 20 15 Rnull = 100 Ω 10 Rnull = 200 Ω Rnull = 50 Ω Rnull = 10 Ω 5 25 0 101 0 101 10 2 10 3 10 4 CL − Load Capacitance − pF 10 5 10 2 10 3 10 4 CL − Load Capacitance − pF † See application information 10 5 Figure 59 Figure 58 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V. ‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION driving large capacitive loads The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56 and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins (Rnull = 0). A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of 10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first adds a zero to the transfer function and the second reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, equation 1 can be used. ǒ ∆φ m1 + tan –1 2 × π × UGBW × R null ×C Ǔ (1) L Where : ∆φ m1 + improvement in phase margin UGBW + unity-gain bandwidth frequency R null + output series resistance C L + load capacitance The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To use equation 1, UGBW must be approximated from Figure 58. Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The overestimation is caused by the decrease in the frequency of the pole associated with the load, providing additional phase shift and reducing the overall improvement in phase margin. Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to optimize the design of circuits driving large capacitance loads. 50 kΩ VDD + VI 50 kΩ Rnull − + CL VDD − / GND Figure 60. Series-Resistance Circuit 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using the TLV2252 typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D D D D D D D D D D D D Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 3 VCC + 9 RSS 92 FB 10 J1 DP VC J2 IN + 11 RD1 VAD DC 12 C1 R2 − 53 HLIM − + C2 6 − − − + VLN + GCM GA VLIM 8 − RD2 54 4 91 + VLP 7 60 + − + DLP 90 RO2 VB IN − VCC − − + ISS RP 2 1 DLN EGND + − RO1 DE 5 + VE OUT .SUBCKT TLV225x 1 2 3 4 5 C1 11 12 6.369E−12 C2 6 7 25.00E−12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 57.62E6 −60E6 60E6 60E6 −60E6 GA 6 0 11 12 26.86E−6 GCM 0 6 10 99 2.686E−9 ISS 3 10 DC 3.1E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 RD1 60 11 37.23E3 RD2 60 12 37.23E3 R01 8 5 84 R02 7 99 84 RP 3 4 71.43E3 RSS 10 99 64.52E6 VAD 60 4 −.5 VB 9 0 DC 0 VC 3 53 DC .605 VE 54 4 DC .605 VLIM 7 8 DC 0 VLP 91 0 DC −0.235 VLN 0 92 DC 7.5 .MODEL DX D (IS=800.0E−18) .MODEL JX PJF (IS=500.0E−15 BETA=139E−6 + VTO=−.05) .ENDS Figure 61. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9550401Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629550401Q2A TLV2262 MFKB 5962-9550401QHA NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9550401QHA TLV2262M 5962-9550401QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9550401QPA TLV2262M 5962-9550403Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629550403Q2A TLV2262 AMFKB 5962-9550403QHA ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9550403QHA TLV2262AM 5962-9550403QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9550403QPA TLV2262AM 5962-9566601Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566601Q2A TLV2252 MFKB 5962-9566601QHA NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9566601QHA TLV2252M 5962-9566601QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9566601QPA TLV2252M 5962-9566602Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566602Q2A TLV2254 MFKB 5962-9566602QCA NRND CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566602QC A TLV2254MJB 5962-9566602QDA NRND CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566602QD A TLV2254MWB 5962-9566603Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566603Q2A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV2252 AMFKB 5962-9566603QHA NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9566603QHA TLV2252AM 5962-9566603QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9566603QPA TLV2252AM 5962-9566604Q2A NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566604Q2A TLV2254 AMFKB 5962-9566604QCA NRND CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566604QC A TLV2254AMJB 5962-9566604QDA NRND CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566604QD A TLV2254AMWB TLV2252AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252A TLV2252AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252A TLV2252AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252A TLV2252AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252A TLV2252AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV2252AI TLV2252AIPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY252A TLV2252AIPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY252A TLV2252AIPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI -40 to 125 TLV2252AIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY252A TLV2252AIPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY252A TLV2252AMFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566603Q2A Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV2252 AMFKB TLV2252AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9566603QPA TLV2252AM TLV2252AMUB NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9566603QHA TLV2252AM TLV2252AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2252CP ACTIVE PDIP P 8 TBD Call TI Call TI 0 to 70 TLV2252ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252I TLV2252IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252I TLV2252IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252I TLV2252IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2252I TLV2252IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV2252IP TLV2252MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566601Q2A TLV2252 MFKB TLV2252MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9566601QPA TLV2252M TLV2252MUB NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9566601QHA TLV2252M TLV2252QD OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2252QDR OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2254AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2254AI TLV2254AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2254AI TLV2254AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2254AI Addendum-Page 3 V2252A Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV2254AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V2254AI TLV2254AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV2254AIN TLV2254AIPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY2254A TLV2254AIPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY2254A TLV2254AIPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125 TLV2254AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY2254A TLV2254AIPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TY2254A TLV2254AMFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566604Q2A TLV2254 AMFKB TLV2254AMJB NRND CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566604QC A TLV2254AMJB TLV2254AMWB NRND CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566604QD A TLV2254AMWB TLV2254AQD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254A TLV2254AQDR OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 125 TLV2254ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254I TLV2254IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254I TLV2254IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254I TLV2254IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254I TLV2254IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV2254IN Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV2254MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629566602Q2A TLV2254 MFKB TLV2254MJB NRND CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566602QC A TLV2254MJB TLV2254MWB NRND CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9566602QD A TLV2254MWB TLV2262AMFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629550403Q2A TLV2262 AMFKB TLV2262AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9550403QPA TLV2262AM TLV2262AMUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9550403QHA TLV2262AM TLV2262MFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629550401Q2A TLV2262 MFKB TLV2262MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9550401QPA TLV2262M TLV2262MUB NRND CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9550401QHA TLV2262M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2252, TLV2252A, TLV2252AM, TLV2252M, TLV2254, TLV2254A, TLV2254AM, TLV2254M, TLV2262AM, TLV2262M : • Catalog: TLV2252A, TLV2252, TLV2254A, TLV2254, TLV2262A, TLV2262 • Automotive: TLV2252-Q1, TLV2252A-Q1, TLV2252A-Q1, TLV2252-Q1, TLV2254-Q1, TLV2254A-Q1, TLV2254A-Q1, TLV2254-Q1, TLV2262A-Q1, TLV2262-Q1 • Enhanced Product: TLV2252-EP, TLV2252A-EP, TLV2252A-EP, TLV2252-EP, TLV2254-EP, TLV2254A-EP, TLV2254A-EP, TLV2254-EP • Military: TLV2252M, TLV2252AM, TLV2254M, TLV2254AM NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 6 PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2015 • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 7 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2252AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2252AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2252IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2254AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2254AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2254IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2252AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2252AIPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2252IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2254AIDR SOIC D 14 2500 367.0 367.0 38.0 TLV2254AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2254IDR SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated

下载 PDF

5962-9566602QDA 价格&库存

-> 查询更多价格&库存

很抱歉，暂时无法提供与“5962-9566602QDA”相匹配的价格&库存，您可以联系我们找货

免费人工找货

搜索历史

5962-9566602QDA

推荐型号

相关技术文章