74ABT16853DGGRE4

SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 D D D D D D D D D D SN54ABT16853 . . . WD PACKAGE SN74ABT16853 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus  Family State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Parity-Error Flag With Parity Generator/Checker Latch for Storage of the Parity-Error Flag Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1OEB 1LE 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR 2LE 2OEB description The ’ABT16853 dual 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus, with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The ’ABT16853 provide true data at the outputs. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEA 1CLR 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2CLR 2OEA A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB and Widebus are trademarks of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 description (continued) The SN54ABT16853 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16853 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUT AND I/O AI Σ OF H BI† Σ OF H A B NA NA A B NA NA CLR LE L H X X H L X L NA H L H H NA X X NA NA NC Store error flag X X L H X X X NA NA H Clear error-flag register H H X L H X X L L Odd X L H Even H L H L X X Odd Odd Odd Even L H NA H L A data to B bus and generate parity B data to A bus and check parity NC X Z Z Z H H Isolation§ (parity check) L NA NA A Even H L NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. 2 FUNCTION OEA Even PARITY ERR‡ OEB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NA A data to B bus and generate inverted parity SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 logic diagram (each transceiver) (positive logic) A1–A8 8 8x 8 B1–B8 EN 8x 8 EN OEB OEA PARITY 8 8 MUX 1 1 2k 9 1 P 1 G1 ERR LE CLR ERROR-FLAG FUNCTION TABLE INPUTS CLR LE L L H L L H H H INTERNAL TO DEVICE OUTPUT POINT P ERRn–1† L H X OUTPUT ERR L H L X X L L H H H X X H L L H H X FUNCTION Pass L Sample Clear Store † State of ERR before changes at CLR, LE, or point P POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 error-flag waveforms H OEB L H OEA L Even Bi + PARITY Odd H LE L H CLR L H ERR L Pass Store Sample Clear absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT16853 VCC VIH Supply voltage VIL VI Low-level input voltage VOH IOH High-level output voltage ERR High-level output current Except ERR IOL ∆t/∆v Low-level output current High-level input voltage SN74ABT16853 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 Input transition rise or fall rate Outputs enabled TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. –55 UNIT V V 0.8 V VCC 5.5 V –24 –32 mA 48 64 mA 10 10 ns/V 85 °C VCC 5.5 125 0 –40 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH All outputs except ERR TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, 5V VCC = 4 4.5 VOL Vhys IOH Ioff ICEX II IIL IO‡ VCC = 4 4.5 5V SN54ABT16853 MIN –1.2 MAX SN74ABT16853 MIN –1.2 2.5 3 2.5 IOH = –3 mA IOH = –24 mA 3 3.4 3 IOH = –32 mA IOL = 24 mA 2* MAX –1.2 3 IOL = 64 mA 2.7 Outputs high Control inputs A or B ports A or B ports A or B ports VCC = 4.5 V, VCC = 0, VOH = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 5.5 V VCC = 0, VCC = 5.5 V, VI = GND VO = 2.5 V 0.55 0.3 0.55* 0.55 0.55 VCC =5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled Ci Control inputs Cio A or B ports VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 20 µA ±100 µA µA 50 50 50 ±1 ±1 ±1 ±100 ±100 ±100 –50 –180 –50 –50 –180 –50 µA –50 µA –180 mA 50 50 50 µA –50 –50 –50 µA 1.5 2 2 2 32 40 40 40 1 2 2 2 50 50 50 VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC¶ 20 ±100 –100 V mV 20 –50 V 2 0.25 VCC = 5 5.5 5 V, V VI = VCC or GND UNIT V 2 100 ERR IOZH§ IOZL§ ICC TA = 25°C MIN TYP† MAX mA µA 3 pF 9 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § The parameters IOZH and IOZL include the input leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw Pulse duration tsu Setup time th Hold time LE high or low CLR low A, B, and PARITY before LE↓ SN54ABT16853 MAX MIN MAX SN74ABT16853 MIN 8.5 8.5 8.5 4 4 4 10 10 10 CLR before LE↓ 0 0 0 A, B, and PARITY after LE↓ 0 0 0 CLR after LE↓ 0 0 0 UNIT MAX ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A or OE PARITY tPLH CLR ERR PARAMETER tPZH tPZL OE A or B tPHZ tPLZ OE A or B tPZH tPZL OE PARITY tPHZ tPLZ OE PARITY tPLH tPHL LE ERR tPLH tPHL A B, A, B or PARITY ERR VCC = 5 V, TA = 25°C SN54ABT16853 MIN TYP MAX MIN MAX MIN MAX 1.5 2.5 3.3 1.5 4.2 1.5 4.1 2 3.1 3.9 2 4.5 2 4.3 2 4.6 5.9 2 7.3 2 7.1 2 4.8 6.2 2 7.6 2 7.2 2 3.7 5.1 2 5.9 2 5.7 2 3.9 4.9 2 5.8 2 5.6 2.5 4.3 5.1 2.5 6.2 2.5 6 2 3.6 4.5 2 5.5 2 5.4 1.5 3 3.8 1.5 4.7 1.5 4.3 2 3.6 5 2 5.8 2 5.7 2.5 4.4 5.8 2.5 6.7 2.5 6.5 1.5 3.2 4 1.5 4.8 1.5 4.7 1.5 2.9 3.7 1.5 4.2 1.5 4.1 2 3.5 4.2 2 5 2 4.8 2 3.4 4.4 2 5.2 2 4.9 2 4.5 6.3 2 7.5 2 7.2 2 4.8 6.3 2 7.7 2 7.4 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 SN74ABT16853 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns ns ns SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open ERR S1 tPHL (see Note E) tPLH (see Note F) 7V 7V LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V th 3V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPHL is measured at 1.5 V. F. tPLH is measured at VOL + 0.3 V. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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