74ABTH162245DGVRG4

SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 D D D D D D D D D D SN54ABTH162245 . . . WD PACKAGE SN74ABTH162245 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus  Family A-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE description The ’ABTH162245 devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABTH162245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH162245 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† 48 1OE 1DIR 1 G3 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR 24 G6 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 47 2 1 2 46 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 35 5 14 33 16 32 17 30 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . 128 mA SN54/74ABTH162245 (A port) . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 recommended operating conditions (see Note 3) SN54ABTH162245 VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage IOH SN74ABTH162245 MIN 0 0 UNIT V V 0.8 V VCC –32 V B port VCC –24 A port –12 –12 B port 48 64 A port 12 12 Outputs enabled 10 10 mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port VOH B port VCC = 4.5 V, VCC = 5 V, II = –18 mA IOH = –1 mA VCC = 4.5 V IOH = –1 mA IOH = –3 mA VCC = 5 V, IOH = –12 mA IOH = –3 mA VCC = 4.5 V IOH = –3 mA IOH = –24 mA B port VCC = 4.5 V –1.2 3 3 3 3.1 2.6 3 3 2.5 2.5 IOL = 48 mA IOL = 64 mA 5V VCC = 4 4.5 Ioff VCC = 0, VI or VO = 0 to 4.5 V A port B port ICEX ICC A or B ports Data inputs ∆ICC§ Control inputs Ci Cio VI = 0.8 V VI = 2 V V 0.8 0.8 0.45 0.45 100 mV ±1 ±1 ±20 ±20 100 100 –100 –100 VO = 2 2.5 5V VCC = 5.5 V, VO = 5.5 V Outputs high VCC = 5.5 V, IO = 0, VI = VCC or GND –25 –90 –25 –100 –50 –180 –50 –180 50 50 Outputs high 2 2 Outputs low 32 32 2 2 2 2 Outputs disabled VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND µ µA µA ±100 VCC = 5 5.5 5V V, V 0.55 VCC = 5.5 V,, VI = VCC or GND II(h ld) I(hold) V 2 100 Control inputs UNIT 2 A or B ports IO‡ –1.2 2.5 Vhys II SN74ABTH162245 MIN TYP† MAX 2.5 IOH = –32 mA IOL = 12 mA A port VOL SN54ABTH162245 MIN TYP† MAX TEST CONDITIONS µA mA µA mA mA 1.5 VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 1.5 3 3 pF 6 6 pF † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A B tPLH tPHL B A tPZH tPZL OE B tPHZ tPLZ OE B tPZH tPZL OE A tPHZ tPLZ OE A PARAMETER VCC = 5 V, TA = 25°C SN54ABTH162245 MIN TYP MAX MIN MAX MIN MAX 1 2.2 3.4 1 4.1 1 3.9 1 2.3 3.7 1 4.4 1 4.2 1 2.7 4.1 1 4.9 1 4.6 1.5 3.1 4.6 1.5 5.2 1.5 5.1 1 3.6 5.2 1 6.4 1 6.3 1 3.7 5.4 1 6.5 1 6.4 2 4.4 5.8 2 6.4 2 6.3 1.5 3.3 4.7 1.5 5.6 1.5 5.2 1.5 4.1 6 1.5 7.2 1.5 7.1 1.5 4.3 6.1 1.5 7.3 1.5 7 2 4.5 6.1 2 6.8 2 6.6 1.5 3.7 5.1 1.5 6.1 1.5 5.7 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 SN74ABTH162245 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns SN54ABTH162245, SN74ABTH162245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at Open (see Note B) 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPLZ tPZL VOH Output 3V Output Control 3.5 V 1.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ABTH162245DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABTH162245 SN74ABTH162245DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABTH162245 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of