74AC11074NSR

74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D, N, OR PW PACKAGE (TOP VIEW) Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1CLK 1D 1CLR VCC 2CLR 2D 2CLK description This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The 74AC11074 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK D Q L H X X H Q L H L X X H H† L L X X L H† H H ° H H L H H ° L L H H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 1 S 14 13 12 7 2 C1 3 1D 1Q 1Q R 6 8 9 5 10 2Q 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . 1.25 W N package . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V MIN NOM MAX 3 5 5.5 0.9 Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature V 3.85 VIL Low-level output current V 2.1 3.15 VCC = 5.5 V VCC = 3 V IOL UNIT VCC = 4.5 V VCC = 5.5 V 1.35 V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V –24 VCC = 5.5 V –24 VCC = 3 V VCC = 4.5 V 12 V V –4 24 VCC = 5.5 V mA mA 24 0 10 ns/V –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH VOL IOH = –4 mA Ci TA = 25°C MIN TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 3.8 MAX 4.5 V 3.94 5.5 V 4.94 IOH = –75 mA† 5.5 V 3V 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 5.5 V 0.1 0.1 IOL = 12 mA IOL = 75 mA† VI = VCC or GND 4.8 3.85 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V IO = 0 5.5 V 5V V 1.65 5.5 V VI = VCC or GND, VI = VCC or GND UNIT V IOH = –24 24 mA A IOL = 24 mA II ICC VCC 3.5 ±0.1 ±1 µA 4 40 µA pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time after CLK↑ 0 MIN MAX UNIT 0 100 MHz 100 PRE or CLR low 4 4 CLK low or high 5 5 Data high or low 5 5 PRE or CLR inactive 1 1 0 0 ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time after CLK↑ 0 MIN MAX UNIT 0 125 MHz 125 PRE or CLR low 4 4 CLK low or CLK high 4 4 3.5 3.5 1 1 0 0 Data high or low PRE or CLR inactive ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q MIN TA = 25°C TYP MAX MIN MAX 100 125 100 1.5 5.8 9.3 1.5 10 1.5 6.5 11.4 1.5 12.2 1.5 7.7 10.5 1.5 11.3 1.5 7.3 9.7 1.5 10.6 UNIT MHz ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q MIN TA = 25°C TYP MAX MIN MAX 125 150 1.5 4.2 6.6 125 1.5 7.1 1.5 4.7 8.2 1.5 9 1.5 5.4 7.5 1.5 8.2 1.5 5 6.9 1.5 7.5 UNIT MHz ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 30 UNIT pF 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) VCC 500 Ω Input 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS VCC Input (see Note B) 50% VCC 50% VCC tPHL tPLH VCC Timing Input (see Note B) 50% VCC In-Phase Output 50% VCC 0V th tsu Data Input 50% VCC 0V Out-of-Phase Output VOH 50% VCC VOL tPLH tPHL VCC 50% VCC 0V 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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